About VIT University About VLSI design Lab Founded in 1984 as Vellore Engineering College, the institute was

declared a University in recognition of its academic excellence by the Ministry of Human Resources Development, Government of India in 2001. The University has since grown by leaps and bounds establishing excellent infrastructure spread over an impeccacably clean and green 250 acre campus - on way to fulfill the vision of the founder and Chancellor Dr. G. Viswanathan to make it truly world class. VIT today comprises of six constituent Schools and interdisciplinary Centers offering undergraduate, graduate, post graduate and research programs upto PhD level. VIT is the first educational institution of India to get ISO 9002 certificate by the DNV of The Netherlands. It is again the first Institute in India to get accreditation from IEE (UK). Further it has also been accredited by NBA (AICTE) and NAAC (UGC). In the last seven years, VIT had more than 100 visiting professors, some of them staying 6 to 12 weeks for offering accelerated courses as well as participating in Workshops and Seminars for the benefit of students of VIT and also the industry around. About the School of Electronics Engineering The School offers B.Tech [ECE] and five M.Tech programs. Facilities for research leading to Ph.D. are available in many emerging areas. A major emphasis in both the undergraduate and post graduate program is teaching and learning process. School is actively involved in R&D activities and has sponsored projects from various agencies like DST, ISRO (RESPOND), and BRNS etc. It has MOUs with industries and other reputed institution and R&D organization of our country and other parts of the world. The VLSI Design Laboratory is equipped with ASIC DESIGN LAB supported by CADENCE Cadence Tools with 60 User License FPGA/SOPC Lab supported by ALTERA MENTOR GRAPHICS Tools with 60 User License ANALOG SYSTEM DESIGN LAB supported by TEXAS INSTUMENTS This lab is being utilized by Engineers from VLSI, Embedded, Sensors and Mechatronics divisions for innovations in their Academic as well as Research projects. Objective of the Training The goal of this training is to provide students/ Faculty an exposure to the fascinating world of analog and mixed-signal signal processing. As part of the training the participants can build analog systems using analog ICs and study their macro models, characteristics and limitations. This training focus on system design along with basic circuit design. Who Can Attend? Faculty from Institution who are teaching or proposing to teach Analog System Design Research Scholars/ Students ( UG/PG) Last date for Registration: On or before Date of confirmation : 05-10-11 : 07-10-11 Note: DD should be taken in favour of VIT payable at Vellore. No. of participants restricted to 40 only. Course Fee: For Faculty/R&D organization Rs. 2750/- [course fee + accommodation] Rs. 2000/- [course fee only] For Students Rs. 2250/- [course fee + accommodation] Rs. 1500/- [course fee only]

Course description:
Design, simulation and Hardware implementation of Following topics using TINA TI and ASLKv 2010 Starter Kit

Second-order filters Self-tuned filters Voltage-controlled oscillators (VCO) Function generators Phase-locked loop (PLL) Automatic gain control (AGC) DC-DC converter Low Drop Out (LDO) regulator Circuit Design Simulation and Parametric Analysis Layout Design DRC, LVS Post Layout Simulation

Design and Simulation of circuit using Cadence

Registration Form
Name : ....................................................................

Speakers:
Need for Analog: By Dr.K.R.K. Rao Texas Instruments, India Dr. C.P. Ravikumar, Director UniTi, Texas Instruments, India Analog Lab Set at VIT: By Mr.Sultan Ahmed, Cranes Software Analog System Design Using ASKLv2010: By Mr.R. Sakthivel , Asst. Prof (Sr.), VIT Circuit Design Using Cadence: By Mr. Jagannadha Naidu K, Asst. Prof, VIT Registration form and DD send to:

Department:

Hands on Training UNIVERSITY On(Estd. u/s 3 of UGC Act 1956)

Vellore 632014, Tamilnadu.India www.vit.ac.in

VIT

Organization :

Experience: ..

Address for Correspondence: ................................................................................................

Hands on Training in

Analog System Design

(10, 11, 12 October 2011)

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School of Electronics Engineering

In Association with

Email: ................................................................................................

VIT University Vellore 632014. TN Contact No : E-mail:

Phone: ...............................................................................................

Accommodation Required Yes

No

Course coordinators: For further details contact

Demand Draft Details: Faculty Amount DD No. Bank Dated Student / Research Scholar : . : . : .. : ..

Mr.R. Sakthivel , Assistant Professor(Sr.) Email: rsakthivel@vit.ac.in contact No: 09994627570 Mr. Jagannadha Naidu K, Assistant Professor
Email : jagannadhanaidu.k@vit.ac.in Contact No: 09943062343

By VLSI DIVISION

School of Electronics Engineering VIT University

Signature: ... (Use Photocopy of the above form, if required)

VIT: A place to learn; A chance to grow