LAB 5, E3-238 ANALOG VLSI CIRCUITS, INDIAN INSTITUTE OF SCIENCE, BANGALORE (560012), KARNATAKA, INDIA

E3-238: Analog VLSI Circuits

Lab 5
November, 2022

PROBLEM DESCRIPTION
In this homework, you are to design a basic two-stage CMOS operational amplifier (op-amp), as shown
in Figure 1, for the specifications given inTable 1. The op-amp consists of a differential input stage
(𝑀𝑀1 and 𝑀𝑀2) driving a current mirror load(𝑀𝑀3 and 𝑀𝑀4) followed by a common-source amplifier
stage (𝑀𝑀7). The devices 𝑀𝑀5 and 𝑀𝑀7 form the tail current source for the differential stage and the
current source load for thecommon- source stage. 𝐶𝐶𝑐𝑐 and 𝑅𝑅𝑧𝑧 are the compensation capacitor and the
zero-nulling resistor.

Figure 1 A basic two-stage operational amplifier.

Table 1 Design specifications @ [Supply voltage = 𝟏𝟏.8 𝑽𝑽, Load CL = 𝟏𝟏𝟏𝟏𝟏𝟏 𝒇𝒇𝒇𝒇, and Temperature = 𝟐𝟐𝟐𝟐° 𝑪𝑪]
S.N. Parameter Symbol Value
1. Open-loop, differential-mode, DC voltage gain 𝐴𝐴0 ≥ 1000 𝑉𝑉/𝑉𝑉
(60 𝑑𝑑𝑑𝑑)
2. Unity-gain frequency 𝑓𝑓UG ≥ 10 𝑀𝑀𝑀𝑀𝑀𝑀
3. Phase margin 𝑃𝑃𝑃𝑃 ≥ 75°
4. Common-mode rejection ratio 𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 ≥ 50 𝑑𝑑𝑑𝑑
5. Power dissipation 𝑃𝑃𝑑𝑑 ≤ 30 𝜇𝜇𝜇𝜇

The designing of the op-amp consists of selecting device sizes and biasing conditions,
compensating the op-amp for stability, and simulating the op-amp open-loop gain (𝐴𝐴0), unity-gain
frequency (𝑓𝑓UG), phase margin (𝑃𝑃𝑃𝑃), common-mode rejection ratio (𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶), common- mode range
(𝐶𝐶𝐶𝐶𝐶𝐶), output swing (𝑆𝑆), Slew rate (SR) and power dissipation (𝑃𝑃𝑑𝑑).

GUIDELINES FOR DESIGNING

1. Breakup the op-amp design problem into the designing of the differential and the common-
source amplifier stages.
2. Recognize the gain-bandwidth-power-swing trade-off in each stage by simulating the core
devices with the ideal bias sources.
3. Design the individual stages for the pre-specified gain, bandwidth, power, and swing with an
approximated load condition. Have enough margins in the design to accommodate the
impairments due to stage cascading, bias networks, and frequency compensation network.
4. Cascade the stages and obtain the overall performance with ideal bias sources.
5. If required, iterate the designing for new values of gain, bandwidth, power, and swing.

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LAB 5, E3-238 ANALOG VLSI CIRCUITS, INDIAN INSTITUTE OF SCIENCE, BANGALORE (560012), KARNATAKA, INDIA

GUIDELINES FOR CHARACTERIZATION

Having selected the device sizes and biasing conditions, you plug your design into a testbench to
characterize its performance. In the testbench, you set the necessary biasing, loading, and excitation to
simulate a characteristic. In general, you may need to create multiple testbenches to simulate various
op-amp parameters. You can also reuse a testbench with different combination of analyses to simulate
multiple parameters. It is not always necessary to create a single generic testbench that allows
simulation of all the parameters. Below is a general guideline to characterize the op-amp using DC, AC,
and transient analyses in conjunction with the appropriate testbench.

DC analysis

1. Obtain the common-mode range (CMR) curve by plotting the output voltage (Vout) with respect
tothe common-mode input voltage (Vic). (Sweep Vic rail-to-rail)
2. Obtain the DC voltage transfer characteristic (VTC) curve by sweeping the differential input
voltage (Vid )and plotting the output voltage (Vout).
3. Find the input-referred DC offset voltage (Voffset) which drives the output voltage to mid-rail
voltage.
4. Compute the differential-mode DC voltage gain curve by taking derivative of the VTC with
respect to Vid.
5. At Vic = VDD/2 and Vid = Voffset, obtain the following values:
a. DC differential-mode voltage gain (𝐴𝐴0)
b. DC common-mode voltage gain(𝐴𝐴𝑐𝑐𝑐𝑐0)
c. Bias current into both the input terminals (Ibias,in1 and Ibias,in2 )
d. Bias current (Ibias = (Ibias,in1 + Ibias,in2)/2)
e. Offset current (Ioffset = | Ibias,in1 − Ibias,in2 |)
f. Positive and negative output saturation limits (𝑉𝑉− to 𝑉𝑉+)
g. Power dissipation (Pdiss =VDD* IDD)

AC analysis

Set the DC condition for DC analysis (3) i.e. output voltage to mid-rail. Set the Vin,CM to mid
rail. Add another AC source Vin,AC in series with the differential input Vin,DC.
1. Obtain the frequency response by plotting magnitude and phase of the differential-mode voltage
gain versus frequency from 1Hz to 10 GHz with 100 points/decade step size.
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LAB 5, E3-238 ANALOG VLSI CIRCUITS, INDIAN INSTITUTE OF SCIENCE, BANGALORE (560012), KARNATAKA, INDIA

2. Find the 0 𝑑𝑑𝑑𝑑 magnitude crossover frequency (𝑓𝑓0𝑑𝑑𝑑𝑑)

3. Find the phase at 𝑓𝑓0𝑑𝑑𝑑𝑑(𝑃𝑃ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑓𝑓0𝑑𝑑𝑑𝑑)
4. Calculate the phase margin in degree (𝑃𝑃𝑃𝑃 = 180 + 𝑃𝑃ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑓𝑓0𝑑𝑑𝑑𝑑 )

Stability analysis

Connect the op-amp in the voltage follower configuration (unity gain feedback) and set the common
mode voltage to mid-rail. Use vstb to break the loop in stb analysis as shown in the class.
1. Plot open loop gain and phase
2. Calculate gain and phase margins.

Transient analysis

1. Connect the op-amp in the voltage follower configuration (unity gain feedback) and set the
common mode voltage to mid-rail. Excite the input (non-invertingterminal) with a (positive
and negative) step signal with large (~ VDD./2) amplitude.
2. Find the positive and negative slew rate (slope of the output V/s) from the transient response.

GUIDELINES FOR REPORT SUBMISSION

Include the following in the report:
1. A design schematic labeled with device sizes and bias voltages and currents.
2. All the testbench schematics.
3. DC analysis: DC transfer curve for the op-amp in the open-loop configuration.
4. AC analysis: Frequency response (both magnitude and phase) for the uncompensated and
compensated op-amp in the open-loop configuration.
5. Stability analysis: Frequency response (both magnitude and phase) for the uncompensated
and compensated op-amp in the closed-loop configuration.
6. Transient analysis: Step response for the uncompensated and compensated op-amp
in the unity feedbackconfiguration.
7. A table listing all the op-amp parameters.
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