Micropower Ultra-Sensitive Hall-Effect Switches: A3213 and A3214

A3213 and A3214
Micropower Ultra-Sensitive Hall-Effect Switches
FEATURES AND BENEFITS DESCRIPTION

• AEC-Q100 automotive qualified The A3213 and A3214 integrated circuits are ultra-sensitive,
• Micropower operation pole-independent Hall-effect switches with a latched digital
• Operate with north or south pole output. They are especially suited for operation in battery-
• 2.4 to 5.5 V battery operation operated, hand-held equipment such as cell and cordless
• Chopper stabilized telephones and palmtop computers. A 2.4 to 5.5 V operation
□□ Superior temperature stability and a unique clocking scheme reduce the average operating
□□ Extremely low switchpoint drift power requirements: the A3213 to 825 µW, the A3214 to
□□ Insensitive to physical stress 14 µW (typical, at 2.75 V). Except for operating duty cycle
• High ESD protection and average operating current, the A3213 and A3214 are
• Solid-state reliability identical.
• Small size
Unlike other Hall-effect switches, either a north or south
• Easily assembly into applications due to magnetic pole
pole of sufficient strength will turn the output on; in the
independence
absence of a magnetic field, the output is off. The polarity
PACKAGES: independence and minimal power requirement allows these
Not to scale devices to easily replace reed switches for superior reliabil-
ity and ease of manufacturing, while eliminating the require-
ment for signal conditioning.
Improved stability is made possible through chopper sta-
bilization (dynamic offset cancellation), which reduces the
NOT FOR
residual offset voltage normally caused by device overmold-
NEW DESIGN
ing, temperature dependencies, and thermal stress.
3-pin SOT23W Continued on the next page…

(suffix LH)
3-pin SIP, 3-pin SIP,
matrix HD style chopper style
(suffix UA) (suffix UA)
SUPPLY
SWITCH
TIMING
LOGIC
OUTPUT
OFFSET CANCELLATION
X
DYNAMIC
SAMPLE
& HOLD
LATCH
GROUND
Dwg. FH-020-5
Functional Block Diagram
27622.62-DS Rev. 28 October 31, 2016

A3213 and
A3214
DESCRIPTION (continued)
These devices include, on a single silicon chip, a Hall-voltage Devices are rated for operation over a temperature range of
generator, small-signal amplifier, chopper stabilization, a latch, –40°C to 85°C or –40°C to 150°C. Two package styles provide a
and a MOSFET output. Advanced BiCMOS processing is used magnetically optimized package for most applications. ‘LH’ is a
to take advantage of low-voltage and low-power requirements, miniature low-profile surface-mount package, ‘UA’ is a three-
component matching, very low input-offset errors, and small lead SIP for through-hole mounting. Each package is lead (Pb)
component geometries. free (suffix, –T) , with a 100% matte-tin-plated leadframe.
SPECIFICATIONS
SELECTION GUIDE
Ambient [1], TA DC IDD(AVG)(typ)
Part Number Mounting Packing [1]
(°C) (%) (µA)
LH package 7-in. reel
A3213ELHLT-T
Surface Mount 3000 pieces/reel
A3213ELHLX-T –40 to 85
25 309
UA package Bulk
A3213EUA-T [2]
SIP through hole 500 pieces/bag
UA package Bulk
A3213LUA-T [2] –40 to 150
A3214ELHLT-T
A3214ELHLX-T –40 to 85 0.10 6
UA package Bulk
A3214EUA-T [2]
1 Contact Allegro for additional packing and operating temperature range options.
2 The chopper-style UA package is not for new design; the matrix HD style UA package is recommended for new designs.
ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Units
Supply Voltage VDD 6 V
Magnetic Flux Density B Unlimited G
Output Off Voltage VOUT 6 V
Output Current IOUT 1 mA
Range E –40 to 85 °C
Operating Ambient Temperature TA
Range L –40 to 150 °C
Maximum Junction Temperature TJ(max) 165 °C
Storage Temperature Tstg –65 to 170 °C
Allegro MicroSystems, LLC 2

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3213 and
A3214
GND
X
1 2 3
1 2
GND
VOUT
VDD
VOUT
VDD
LH Package, 3-Pin SOT23W Pinout Diagram UA Package, 3-Pin SIP Pinout Diagram
Terminal List Table

Number
Name Description
LH UA
1 1 VDD Input power supply; tie to GND with bypass capacitor
3 2 GND Ground
2 3 VOUT Output signal

A3213 and
A3214
ELECTRICAL CHARACTERISTICS: Valid over operating voltage and temperature range, unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ. [1] Max. Units
Supply Voltage Range VDD Operating [2] 2.4 3.0 5.5 V
Output Leakage Current IOFF VOUT = 5.5 V, BRPN < B < BRPS – <1.0 1.0 µA
Output On Voltage VOUT(ON) Output on, IOUT = 1 mA, VDD = 3.0 V – 100 300 mV
Awake Time tawake – 60 90 µs
A3213 – 240 360 µs
Period tperiod
A3214, TA = 25°C, VDD = 3 V – 60 90 ms
A3213 – 25 – %
Duty Cycle DC
A3214 – 0.10 – %
Chopping Frequency fC – 340 – kHz
IDD(EN) Chip awake (enabled) – – 2.0 mA
IDD(DIS) Chip asleep (disabled) – – 8.0 µA
Supply Current
A3213 – 309 850 µA
IDD(AVG)
A3214 – 6 22 µA
1 TypicalData is at TA = 25°C and VDD = 3.0 V and is for design information only.
2 Operate and release points will vary with supply voltage. B
OPx = operate point (output turns ON); BRPx = release point (output turns OFF).
MAGNETIC CHARACTERISTICS [3]: valid over operating voltage and temperature range, unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ. [5] Max. Units [6]
BOPS South pole to branded side – 42 70 G
Operate Points [4]
BOPN North pole to branded side –70 –48 – G
BRPS South pole to branded side 10 32 – G
Release Points [4]
BRPN North pole to branded side – –38 –10 G
Hysteresis Bhys |BOPx - BRPx| – 10 – G
3 As used here, negative flux densities are defined as less than zero (algebraic convention) and -50 G is less than +10 G.
4B
OPx = operate point (output turns ON); BRPx = release point (output turns OFF).
5 Typical Data is at T = 25°C and V
A DD = 3.0 V and is for design information only.
6 1 gauss (G) is exactly equal to 0.1 millitesla (mT).

A3213 and
A3214
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions [1] Value Units
Package LH, 1-layer PCB with copper limited to solder pads 228 °C/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area each side
Package Thermal Resistance RθJA 110 °C/W
connected by thermal vias
Package UA, 1-layer PCB with copper limited to solder pads 165 °C/W
1 Additional thermal information available on Allegro website.
VDD(max)
Maximum Allowable VDD (V)
VDD(min)
Power Dissipation versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
Power Dissipation, PD (mW)
1200 2-
l
1100 (R aye
θJ rP
A = C
1000 11 B, P
1-la 0 º ac
900 C/ ka
(R yer PC W
) ge L
800 θJA = B, P H
165 ack
700 ºC/ age
W) UA
600
500 1-lay
400 er P
(R CB,
300 θJA =
228 Packag
ºC/W e LH
200 )
100
0
20 40 60 80 100 120 140 160 180
Temperature (°C)

A3213 and
A3214
TYPICAL OPERATING CHARACTERISTICS
A3213 and A3214 A3213 and A3214

Switchpoints versus Ambient Temperature Switchpoints versus Ambient Temperature
VDD = 2.4 V VDD = 5.5 V
80 80
60 60
Magnetic Flux Density, B (G)

BOP(S) BOP(S)
40 40
BRP(S) BRP(S)
20 20
0 0
-20 -20
BRP(N)
BRP(N)
-40 -40
-60 BOP(N) -60

BOP(N)
-80 -80
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100
Ambient Temperature, TA (°C) Ambient Temperature, TA (°C)
A3213 and A3214

Switchpoints versus Supply Voltage
TA = 25°C
80
60
BOP(S)
40
20 BRP(S)
-20
BRP(N)
-40
-60
BOP(N)
-80
0 1 2 3 4 5 6
Supply Voltage, VDD (V)
A3213 A3214
Average Supply Current versus Temperature Average Supply Current versus Temperature
900 24
Supply Current, IDD(AVG) (µA)
750 20
600 16 VDD = 5.5 V

VDD = 5.5 V
450 12
VDD = 3.0 V
300 8
VDD = 3.0 V
VDD = 2.4 V
150 4
VDD = 2.4 V
0 0
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100
Ambient Temperature, TA (°C) Ambient Temperature, TA (°C)
A3213 A3214
Average Supply Current versus Supply Voltage Average Supply Current versus Supply Voltage
TA = 25°C TA = 25°C
900 24
750 20
600 16
450 12
300 8
150 4
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
Supply Voltage, VDD (V) Supply Voltage, VDD (V)

A3213 and
A3214
FUNCTIONAL DESCRIPTION
Low Average Power +V
Internal timing circuitry activates the IC for 60 µs and deac-
SAMPLE
& HOLD
tivates it for the remainder of the period (240 µs (typ) for the
A3213 and 60 ms (typ) for the A3214). A short "awake" time
allows for stabilization prior to the sampling and data latching
on the falling edge of the timing pulse. The output during the
"sleep" time is latched in the last sampled state. The supply cur-
rent is not affected by the output state.
X
PERIOD
60 µs "AWAKE"
IDD(EN)
"SLEEP"
SAMPLE &
OUTPUT LATCHED
IDD(DIS) Dwg. EH-012-1

0
Chopper-Stabilized Technique B
+V
The Hall element can be considered as a resistor array similar to
a Wheatstone bridge. A large portion of the offset is a result of
the mismatching of these resistors. These devices use a dynamic
offset cancellation technique, with an internal high-frequency —
clock to reduce the residual offset voltage of the Hall element
that is normally caused by device overmolding, temperature
dependencies, and thermal stress. The chopper-stabilizing tech- HALL
VOLTAGE
nique cancels the mismatching of the resistor circuit by chang-
ing the direction of the current flowing through the Hall plate
using CMOS switches and Hall voltage measurement taps, while
+
maintaing the Hall-voltage signal that is induced by the external
magnetic flux. The signal is then captured by a sample-and-hold Dwg. AH-011-2
circuit and further processed using low-offset bipolar circuitry.

This technique produces devices that have an extremely stable
Operation
quiescent Hall output voltage, are immune to thermal stress, and The output of this device switches low (turns on) when a mag-
have precise recoverability after temperature cycling. This tech- netic field perpendicular to the Hall element exceeds the operate
nique will also slightly degrade the device output repeatability. point BOPS (or is less than BOPN). After turn-on, the output is
A relatively high sampling frequency is used in order that faster capable of sinking up to 1 mA and the output voltage is VOUT(ON).
signals can be processed. When the magnetic field is reduced below the release point BRPS
(or increased above BRPN), the device output switches high (turns
More detailed descriptions of the circuit operation can be found
off). The difference in the magnetic operate and release points is
in Technical Paper STP 97-10, Monolithic Magnetic Hall Sensing
the hysteresis (Bhys) of the device. This built-in hysteresis allows
Using Dynamic Quadrature Offset Cancellation and Technical
clean switching of the output even in the presence of external
Paper STP 99-1, Chopper-Stabilized Amplifiers With A Track-
mechanical vibration and electrical noise.
and-Hold Signal Demodulator.
As used here, negative flux densities are defined as less than zero
(algebraic convention) and -50 G is less than +10 G.

A3213 and
A3214
Applications
Allegro's pole-independent sensing technique allows for opera-
tion with either a north pole or south pole magnet orientation,
enhancing the flexibility of the device in application assembling.
The technology provides the same output polarity for either pole
face.
It is strongly recommended that an external bypass capacitor be
connected (in close proximity to the Hall element) between the
supply and ground of the device to reduce both external noise
and noise generated by the chopper-stabilization technique. This
is especially true due to the relatively high impedance of battery
supplies.
The simplest form of magnet that will operate these devices is
a bar magnet with either pole near the branded surface of the
device. Many other methods of operation are possible. Exten-
sive applications information on magnets and Hall-effect devices
is also available on the Allegro website: www.allegromicro.com.
OUTPUT OFF
5V VOUT
MAX
B OPN B OPS
OUTPUT
OUTPUT VOLTAGE
10 pF
GND
50 k Ω
X VDD
SUPPLY
(3 V BATTERY)
0.1 µF
BRPN BRPS
OUTPUT ON OUTPUT ON
0
-B 0 +B
MAGNETIC FLUX

A3213 and
A3214
CUSTOMER PACKAGE DRAWING
For Reference Only – Not for Tooling Use

(Reference DWG-2840)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.12
2.98 –0.08
D
1.49
4° ±4°
A
3
+0.020
0.180 –0.053
0.96 D
+0.19
+0.10 1.91 –0.06 2.40
2.90 –0.20
0.70
D
1.00
0.25 MIN
1 2
0.55 REF
0.25 BSC 0.95
Seating Plane
Branded Face Gauge Plane B PCB Layout Reference View
8X 10°
REF
1.00 ±0.13
NNT
+0.10
0.05 –0.05
0.95 BSC
0.40 ±0.10
N = Last three digits of device part number
T = Temperature Code (Letter)
A Active Area Depth, 0.28 mm
B Reference land pattern layout; all pads a minimum of 0.20 mm from all adjacent pads;
C Standard Branding Reference View
adjust as necessary to meet application process requirements and PCB layout tolerances
C Branding scale and appearance at supplier discretion
D Hall elements, not to scale
Figure 1: Package LH, 3-Pin (SOT-23W)

A3213 and
A3214
For Reference Only – Not for Tooling Use

(Reference DWG-9049)
Dimensions in millimeters – NOT TO SCALE
45°
+0.08
4.09
–0.05 1.52 ±0.05
E C
2.04
2 X 10°
1.44 E E Mold Ejector
+0.08 Pin Indent
3.02
–0.05
Branded 45°
Face
2.16 MAX
0.51 REF
A 0.79 REF
1 2 3
+0.05 +0.03
0.43 0.41
–0.07 –0.06
1.27 NOM
NNT
15.75 ±0.25
1
D Standard Branding Reference View

= Supplier emblem
N = Last three digits of device part number
T = Temperature code
A Dambar removal protrusion (6X)
B Gate and tie bar burr area
C Active Area Depth, 0.50 mm REF
D Branding scale and appearance at supplier discretion
E Hall element, not to scale
Figure 2: Package UA, 3-Pin SIP, Matrix Style

A3213 and
A3214
+0.08
4.09 –0.05
45°
B
C
E
2.04
1.52 ±0.05
1.44 E
Mold Ejector
+0.08 Pin Indent
3.02 –0.05
E
Branded 45°
Face
2.16
MAX D Standard Branding Reference View
0.79 REF
0.51
REF
A
NOT FOR NNT
NEW DESIGN
1 2 3
1
= Supplier emblem
+0.03 N = Last two digits of device part number
0.41 –0.06
15.75 ±0.51 T = Temperature code
For Reference Only; not for tooling use (reference DWG-9049)

Dimensions in millimeters
A Dambar removal protrusion (6X)

B Gate burr area
C Active Area Depth, 0.50 mm REF
D Branding scale and appearance at supplier discretion
E Hall element, not to scale
+0.05 1.27 NOM

0.43 –0.07
Figure 3: Package UA, 3-Pin SIP, Chopper Style

A3213 and
A3214
Revision History
Number Date Description
25 October 29, 2012 Update product selection
26 January 6, 2015 Added LX option to Selection Guide
27 September 22, 2015 Corrected LH package Active Area Depth value; added AEC-Q100 qualification under Features
and Benefits
28 October 31, 2016 Chopper-style UA package designated as not for new design
Copyright ©2016, Allegro MicroSystems, LLC

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com


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A3213 and A3214

Micropower Ultra-Sensitive Hall-Effect Switches

FEATURES AND BENEFITS DESCRIPTION

3-pin SOT23W Continued on the next page…

Functional Block Diagram

27622.62-DS Rev. 28 October 31, 2016

ABSOLUTE MAXIMUM RATINGS

Allegro MicroSystems, LLC 2

Terminal List Table

Allegro MicroSystems, LLC 3

Allegro MicroSystems, LLC 4

Power Dissipation versus Ambient Temperature

Allegro MicroSystems, LLC 5

TYPICAL OPERATING CHARACTERISTICS

A3213 and A3214 A3213 and A3214

Magnetic Flux Density, B (G)

-60 BOP(N) -60

Ambient Temperature, TA (°C) Ambient Temperature, TA (°C)

A3213 and A3214

Supply Voltage, VDD (V)

600 16 VDD = 5.5 V

Ambient Temperature, TA (°C) Ambient Temperature, TA (°C)

Allegro MicroSystems, LLC 6

Low Average Power +V

Internal timing circuitry activates the IC for 60 µs and deac-

IDD(DIS) Dwg. EH-012-1

circuit and further processed using low-offset bipolar circuitry.

Allegro MicroSystems, LLC 7

Allegro MicroSystems, LLC 8

CUSTOMER PACKAGE DRAWING

For Reference Only – Not for Tooling Use

A Active Area Depth, 0.28 mm

C Branding scale and appearance at supplier discretion

D Hall elements, not to scale

Figure 1: Package LH, 3-Pin (SOT-23W)

Allegro MicroSystems, LLC 9

For Reference Only – Not for Tooling Use

D Standard Branding Reference View

A Dambar removal protrusion (6X)

B Gate and tie bar burr area

C Active Area Depth, 0.50 mm REF

D Branding scale and appearance at supplier discretion

E Hall element, not to scale

Figure 2: Package UA, 3-Pin SIP, Matrix Style

Allegro MicroSystems, LLC 10

For Reference Only; not for tooling use (reference DWG-9049)

A Dambar removal protrusion (6X)

+0.05 1.27 NOM

Figure 3: Package UA, 3-Pin SIP, Chopper Style

Allegro MicroSystems, LLC 11

Copyright ©2016, Allegro MicroSystems, LLC

For the latest version of this document, visit our website:

Allegro MicroSystems, LLC 12

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