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Regulator
To All Subcircuits
Low-Pass VOUT
Sample and Hold
Filter
Dynamic Offset
Cancellation
Amp Control
Current Limit
GND
A1120-DS, Rev. 11
A1120, A1121
and A1125 Chopper Stabilized Precision Hall Effect Switches
Selection Guide
Switchpoints
(Typ.) Output In South (Positive)
Part Number Packing1 Mounting Ambient, TA
Magnetic Field
BOP BRP
A1120ELHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1120ELHLT-T2 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40ºC to 85ºC
A1120EUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
35 25
A1120LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1120LLHLT-T2 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40ºC to 150ºC
A1120LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
On (logic low)
A1121ELHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1121ELHLT-T2 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40ºC to 85ºC
A1121EUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
95 70
A1121LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1121LLHLT-T2 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40ºC to 150ºC
A1121LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
A1125ELHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
–40ºC to 85ºC
A1125EUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
35 25 Off (logic high)
A1125LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
–40ºC to 150ºC
A1125LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
*Contact Allegro for additional packing options.
2Available through authorized Allegro distributors only.
Pin-out Diagrams
GND
Package LH Package UA
1 2 1 2 3
VCC
VOUT
GND
VCC
VOUT
Terminal List
Number
Name Description
Package LH Package UA
VCC Connects power supply to chip 1 1
VOUT Output from circuit 2 3
GND Ground 3 2
ELECTRICAL CHARACTERISTICS Valid valid over full operating voltage and ambient temperature ranges; unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ.1 Max. Unit2
Electrical Characteristics
Forward Supply Voltage VCC Operating, TJ < 165°C 3 – 24 V
A1120,
VOUT = 24 V, B < BRP – – 10 μA
Output Leakage Current IOUTOFF A1121
A1125 VOUT = 24 V, B > BOP – – 10 μA
A1120,
IOUT = 20 mA, B > BOP – 185 500 mV
Output Saturation Voltage VOUT(SAT) A1121
A1125 IOUT = 20 mA, B < BRP – 185 500 mV
A1120,
B > BOP 30 – 60 mA
Output Current Limit IOM A1121
A1125 B < BRP 30 – 60 mA
VCC > 3.0 V, B < BRP(min) – 10 G,
Power-On Time3 tPO – – 25 μs
B > BOP(max) + 10 G
Chopping Frequency fC – 800 – kHz
Output Rise Time3,4 tr RL = 820 Ω, CS = 20 pF – 0.2 2 μs
Output Fall Time3,4 tf RL = 820 Ω, CS = 20 pF – 0.1 2 μs
A1120,
VCC = 12 V, B > BOP – – 4 mA
ICC(ON) A1121
A1125 VCC = 12 V, B < BRP – – 4 mA
Supply Current
A1120,
VCC = 12 V, B < BRP – – 4 mA
ICC(OFF) A1121
A1125 VCC = 12 V, B > BOP – – 4 mA
Reverse Supply Current IRCC VRCC = –30 V – – –5 mA
Supply Zener Clamp Voltage VZ ICC = 5 mA; TA = 25°C 28 – – V
Zener Impedance IZ ICC = 5 mA; TA = 25°C – 50 – Ω
Magnetic Characteristics
A1120,
– 35 50 G
Operate Point BOP A1125
A1121 50 95 135 G
A1120,
5 25 – G
Release Point BRP A1125
A1121 40 70 110 G
A1120,
– 10 – G
Hysteresis BHYS A1125 (BOP – BRP)
A1121 10 25 42 G
1Typical
data are are at TA = 25°C and VCC = 12 V, and are for initial design estimations only.
21G (gauss) = 0.1 mT (millitesla).
3Guaranteed by device design and characterization.
4C = oscilloscope probe capacitance.
S
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions Value Units
Package LH, 1-layer PCB with copper limited to solder pads 228 ºC/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area each
Package Thermal Resistance RθJA 110 ºC/W
side connected by thermal vias
Package UA, 1-layer PCB with copper limited to solder pads 165 ºC/W
21
20
19
18
17
16
15
14
13
12
Package LH, 2-layer PCB
11 (RQJA = 110 ºC/W)
10
9 Package UA, 1-layer PCB
8 (RQJA = 165 ºC/W)
7
6 Package LH, 1-layer PCB
5 (RQJA = 228 ºC/W)
4
3 VCC(min)
2
20 40 60 80 100 120 140 160 180
1900
1800
1700
1600
1500
1400
1300
Power Dissipation, PD (mW)
1200 Pa
1100 (R cka
QJ ge
A = L
1000 11 H, 2
Pac 0 º -la
900 C/ ye
800 (R kage W
) r PC
QJA = UA B
165 1-la,
700 ºC/ yer
W) PC
600 B
500 Pac
k
400 (R age LH
,
300 QJA =
228 1-laye
ºC/W r PC
200 ) B
100
0
20 40 60 80 100 120 140 160 180
Temperature (°C)
Characteristic Performance
A1120, A1121, and A1125 Electrical Characteristics
Average Supply Current (On) versus Ambient Temperature Average Supply Current (On) versus Average Supply Voltage
6.0 6.0
5.5 5.5
5.0 5.0
4.5 4.5
4.0
ICC(av) (mA)
ICC(av) (mA)
4.0 VCC (V) TA (°C)
3.5 3.5
3.0 –40
3.0 3.0
12
2.5 2.5 25
24
2.0 2.0
150
1.5 1.5
1.0 1.0
0.5 0.5
0 0
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
Average Supply Current (Off) versus Ambient Temperature Average Supply Current (Off) versus Average Supply Voltage
6.0 6.0
5.5 5.5
5.0 5.0
4.5 4.5
4.0 VCC (V) 4.0 TA (°C)
ICC(av) (mA)
ICC(av) (mA)
3.5 3.5
3.0 –40
3.0 3.0
12
2.5 2.5 25
24
2.0 2.0
150
1.5 1.5
1.0 1.0
0.5 0.5
0 0
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
Average Output Saturation Voltage versus Ambient Temperature Average Output Saturation Voltage versus Supply Voltage
300 300
250 250
200 200
VOUT(sat) (V)
VOUT(sat) (V)
0 0
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
Average Operate Point versus Ambient Temperature Average Operate Point versus Average Supply Voltage
50 50
45 45
40 40
35 35
VCC (V) TA (°C)
30 30
BOP (G)
BOP (G)
3.0 –40
25 25 25
20 24 20 150
15 15
10 10
5 5
0 0
-60 -40 -20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
Average Release Point versus Ambient Temperature Average Release Point versus Average Supply Voltage
50 50
45 45
40 40
35 35
BRP (G)
BRP (G)
Average Switchpoint Hysteresis versus Ambient Temperature Average Switchpoint Hysteresis versus Supply Voltage
20 20
18 18
16 16
14 14
BHYS (G)
BHYS (G)
Operate Point versus Ambient Temperature Operate Point versus Average Supply Voltage
140 140
130 130
120 120
BOP (G)
100 3.0 100 –40
12 25
90 90
24 150
80 80
70 70
60 60
50 50
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
Release Point versus Ambient Temperature Release Point versus Average Supply Voltage
110 110
100 100
90 90
BRP (G)
BRP (G)
50 50
40 40
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22
TA (°C) VCC (V)
Switchpoint Hysteresis versus Ambient Temperature Switchpoint Hysteresis versus Supply Voltage
40 40
35 35
30 30
BHYS (G)
BHYS (G)
15 15
10 10
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160 2 6 10 14 18 22 26
TA (°C) VCC (V)
Functional Description
VS
V+ V+
VCC VCC
Switch to High
Switch to High
Switch to Low
Switch to Low
VCC RL
VOUT
VOUT
A112x
VOUT
Output
CBYP
VOUT(SAT) VOUT(SAT) 0.1 μF GND
0 0
0 B+ 0 B+
BOP
BOP
BRP
BRP
BHYS BHYS
(A) (B) (C)
Figure 1. Device switching behavior. In panels A and B, on the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength.
This behavior can be exhibited when using an electrical circuit such as that shown in panel C.
Chopper Stabilization Technique The chopper stabilization technique uses a 400 kHz high fre-
When using Hall effect technology, a limiting factor for quency clock. For demodulation process, a sample and hold
switchpoint accuracy is the small signal voltage developed across technique is used, where the sampling is performed at twice the
the Hall element. This voltage is disproportionally small relative chopper frequency (800 kHz). This high-frequency operation
to the offset that can be produced at the output of the Hall ele- allows a greater sampling rate, which results in higher accuracy
ment. This makes it difficult to process the signal while main- and faster signal-processing capability. This approach desensi-
taining an accurate, reliable output over the specified operating tizes the chip to the effects of thermal and mechanical stresses,
temperature and voltage ranges. and produces devices that have extremely stable quiescent Hall
output voltages and precise recoverability after temperature
Chopper stabilization is a unique approach used to minimize cycling. This technique is made possible through the use of a
Hall offset on the chip. The patented Allegro technique, namely BiCMOS process, which allows the use of low-offset, low-noise
Dynamic Quadrature Offset Cancellation, removes key sources amplifiers in combination with high-density logic integration and
of the output drift induced by thermal and mechanical stresses. sample-and-hold circuits.
This offset reduction technique is based on a signal modulation-
The repeatability of magnetic field-induced switching is affected
demodulation process. The undesired offset signal is separated slightly by a chopper technique. However, the Allegro high
from the magnetic field-induced signal in the frequency domain, frequency chopping approach minimizes the affect of jitter and
through modulation. The subsequent demodulation acts as a makes it imperceptible in most applications. Applications that are
modulation process for the offset, causing the magnetic field more likely to be sensitive to such degradation are those requiring
induced signal to recover its original spectrum at baseband, while precise sensing of alternating magnetic fields; for example, speed
the dc offset becomes a high-frequency signal. The magnetic sensing of ring-magnet targets. For such applications, Allegro
sourced signal then can pass through a low-pass filter, while the recommends its digital device families with lower sensitivity
modulated DC offset is suppressed. This configuration is illus- to jitter. For more information on those devices, contact your
trated in figure 2. Allegro sales representative.
Regulator
Clock/Logic
Low-Pass
Hall Element Filter
Sample and
Hold
Amp
+0.12
2.98 –0.08
1.49 D +4°
4° –0°
3 A
+0.020
0.180–0.053
0.96 D
1.00
1 2
1.00 ±0.13
NNT
+0.10 1
0.05 –0.05
0.95 BSC C Standard Branding Reference View
0.40 ±0.10
N = Last two digits of device part number
T = Temperature code
For Reference Only; not for tooling use (reference dwg. 802840)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Active Area Depth, 0.28 mm REF
B Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C Branding scale and appearance at supplier discretion
+0.08
4.09 –0.05
45°
B
C
E
2.04
1.52 ±0.05
1.44 E
Mold Ejector
+0.08 Pin Indent NNT
3.02 –0.05
E
Branded 45°
Face 1
2.16 D Standard Branding Reference View
MAX
= Supplier emblem
0.79 REF N = Last two digits of device part number
A T = Temperature code
0.51
REF
1 2 3