RAVINDRA COLLEGE OF ENGINEERING FOR WOMEN::KURNOOL

Department of Electronics and Communication Engineering 2018-19

Grade of the subject: Programming / Theory Class: B.Tech III-I Sem A-SEC
Subject name: DIGITAL SYSTEM DESIGN Faculty name: T.KISHORE
S.NO Date Topics to be covered as per JNTUA syllabus Topics covered deviation Reason for
Deviation

1 3/7/2018 BRIDGE COURSE codevita classes

2 5/7/2018 BRIDGE COURSE codevita classes
3 6/7/2018 BRIDGE COURSE codevita classes
4 6/7/2018 BRIDGE COURSE codevita classes
UNIT-1 CMOS LOGIC:
5 7/7/2018 codevita classes
INTRODUCTION TO LOGIC FAMILIES
6 10/7/2018 CMOS LOGIC BRIDGE COURSE
7 10/7/2018 CMOS NAND and NOR GATES BRIDGE COURSE
UNIT-1 CMOS LOGIC:
8 11/7/2018 NON INVERTING GATES INTRODUCTION TO LOGIC
FAMILIES
9 12/7/2018 CMOS AND OR INVERTER and OR AND INVERT CMOS LOGIC
10 13/7/2018 CMOS LOGIC FAMILIES CMOS NAND and NOR GATES
11 14/7/2018 BIPOLAR LOGIC NON INVERTING GATES
12 17/7/2018 TRANSISTOR LOGIC NON INVERTING GATES
13 17/7/2018 TTL FAMILIES NON INVERTING GATES
14 CMOS/TTL INTERFACING CMOS AND OR INVERTER and OR
18/7/2018 AND INVERT
CMOS AND OR INVERTER and OR
15 EMITTER COUPLED LOGIC
19/7/2018 AND INVERT

16 FAMILIARITY WITH STANDARD 74XX AND CMOS LOGIC FAMILIES

20/7/2018 CMOS 40XX SERIES ICS-SPECIFICATIONS.
17 21/7/2018 PROBLEMS YES ORIENTATION DAY
UNIT-2 HARDWARE DESCRIPTION
18 LANGUAGES CMOS LOGIC FAMILIES
24/7/2018 DESIGN FLOW
19 24/7/2018 PROGRAM STRUCTURE YES BANDH
20 25/7/2018 TYPES & CONSTANTS
21 26/7/2018 FUNCTIONS AND PROCEDURES BIPOLAR LOGIC YES
22 31/7/2018 LIBRARIES AND PACKAGES PROGRAM STRUCTURE
23 1/8,2/18 STRUCTURAL DESGN ELEMENTS TYPES & CONSTANTS
24 3/8,4/18 BEHAVIORAL DESIGN ELEMENTS FUNCTIONS AND PROCEDURES
25 7/8,7/8 BEHAVIORAL DESIGN ELEMENTS FUNCTIONS AND PROCEDURES
26 8/8,9/8 TIME DIMENSION AND SIMULATION SYNTHESI FUNCTIONS AND PROCEDURES

27 TEST BENCHES, VHDL FEATURES FOR FUNCTIONS AND PROCEDURES yes

10/8,14/8,16/8,17/8 SEQUENTIAL LOGIC DESGN, SYNTHESIS
28 18/8,21/8 PROBLEMS

29
21/8,23/8 UNIVERSITY QUESTION PAPER DISCUSSION
UNIT-3 COMBINATIONAL LOGIC DESIGN UNIT-3 COMBINATIONAL LOGIC
30 PRACTICES DESIGN PRACTICES no
24/8,25/8 DECODERS DECODERS
31 28/8 ENCODERS ENCODERS
32 28/8 MULTIPLEXERS MULTIPLEXERS
33 29/8,30/8 COMPARATORS MULTIPLEXERS
34 8/31/2018 ADDERS COMPARATORS
35 1/9/2018 THREE STATE DEVICES
36 3/9/2018 MULTIPLEXERS MULTIPLEXERS
37 4/9/2018 DE MULTIPLEXERS DE MULTIPLEXERS
38 5/9/2018 ADDERS ADDERS
39 6/9/2018 ADDERS ADDERS
40 7/9/2018 SUBTRACTORS SUBTRACTORS no
41 8/9/2018 COMBINATIONAL MULTIPLIERS
42 9/9/2018 COMBINATIONAL MULTIPLIERS COMBINATIONAL MULTIPLIERS
DESIGNING USING COMBINATIONAL
43 DESIGNING USING COMBINATIONAL PLD'S
10/9/2018 PLD'S
DESIGNING USING COMBINATIONAL
44 DESIGNING USING COMBINATIONAL PLD'S
11/9/2018 PLD'S
12/9/2018 DESIGNING USING COMBINATIONAL
45 DESIGNING USING COMBINATIONAL PLD'S PLD'S
46 13/9/2018 PLA'S PLA'S
47 14/9/2018 PAL'S PAL'S
48 16/9/2018 PROM'S CMOS PLD'S
49 17/9/18
50 18/9/18
51 19/9/18
52 20/9/18
FIRST MID TERM EXAMINATION
 FIRST MID TERM EXAMINATION
53 22/9/2018
54 24/9/2018
55 25/9/2018
56 26/9/2018
COMBINATIONAL MULTIPLIERS, VHDL
57
27/9/2018 MODELS FOR THE ABOVE ICS
COMBINATIONAL MULTIPLIERS, VHDL
58 MODELS FOR THE ABOVE ICS
27/9/2018
3/10/2018 COMBINATIONAL MULTIPLIERS, VHDL
59
MODELS FOR THE ABOVE ICS
UNIT-4 SEQUENTIAL MACHINE DESIGN
60 PRACTICES
4/10/2018 REVIEW OF DESIGN OF STATE MACHINES

61 STANDARD BUILDING BLOCK ICS FOR SHIFT

5/10/2018 REGISTERS
62 7/10/2018 PARALLEL / SERIAL CONVERSION
63 10/10/2018 SHIFT REGISTER
64 11/10/2018 COUNTERS,LSFR COUNTER
65 12/10/2018 RING COUNTERS
66 14/10/2018 JOHNSON COUNTERS
67 17/10/2018 PROBLEMS

68
18/10/2018 UNIVERSITY QUESTION PAPER DISCUSSION
UNIT-5 DESIGN EXAMPLES
69
21/10/2018 BARREL SHIFTER+C34
70 24/10/2018 COMPARATORS
71 25/10/2018 FLOATING POINT ENCODER
72 26/10/2018 DUAL PARITY ENCODER
73 28/10/2018 SEQUENTIAL LOGIC DESIGN:LATCHES
74 31/10/2018 FLIP FLOPS, COUNTERS

75 SHIFT REGISTERS AND THEIR VHDL MODELS

1/11/2018
76 2/11,3/11 DUAL PARITY ENCODER
77 PLD'S

78
UNIVERSITY QUESTION PAPER DISCUSSION
79 REVISION
80 REVISION
Verified by HOD FEEDBACK
deviation-10 periods satisfactory

deviation-02 periods satisfactory

no deviation satisfactory

deviation-one period satisfactory

NO DEVIATION satisfactory

NO DEVIATION satisfactory
 RAVINDRA COLLEGE OF ENGINEERING FOR WOMEN::KURNOOL
Department of Electronics and Communication Engineering
Class: III B.TEC
Name of the Subject: DIGITAL SYSTEM DESIGN Name of the Faculty: T.KISHORE
Periods
N Date Topics to be covered as per JNTUA syllabus Topics covered
a
m
e

o
f

t 1 2/7/2018 BRIDGE COURSE

h
2 3/7/2018 BRIDGE COURSE
e
3 5/7/2018 BRIDGE COURSE
M4 5/7/2018 BRIDGE COURSE
o
n
t 5 6/7,7/7
UNIT-1 CMOS LOGIC: INTRODUCTION TO LOGIC FAMILIES
h
6 9/7,10/7 CMOS LOGIC BRIDGE COURSE
7 12/7,12/7,13/7 CMOS NAND and NOR GATES BRIDGE COURSE
UNIT-1 CMOS LOGIC:
8 14/7,16/7 NON INVERTING GATES INTRODUCTION TO LOGIC
July FAMILIES
9 17/7/2018 CMOS AND OR INVERTER and OR AND INVERT CMOS LOGIC
10 19/7,19/7 CMOS LOGIC FAMILIES CMOS NAND and NOR GATES
11 20/7,21/7 BIPOLAR LOGIC NON INVERTING GATES
12 21/7/2018 TRANSISTOR LOGIC
13 23/7/2018 TTL FAMILIES NON INVERTING GATES
CMOS AND OR INVERTER and OR
14 23/7 CMOS/TTL INTERFACING
AND INVERT
15 24/7/2018 EMITTER COUPLED LOGIC

16 CMOS LOGIC FAMILIES

26/7/2018 FAMILIARITY WITH STANDARD 74XX AND CMOS 40XX SERIES ICS-SPECIFICATIONS.
17 27/7; 28/7/2018PROBLEMS

UNIT-2 HARDWARE DESCRIPTION LANGUAGES DESIGN CMOS LOGIC FAMILIES

18
FLOW
30/7,31/7
19 2/8,2/8,3/8 PROGRAM STRUCTURE PROGRAM STRUCTURE
20 4/8,6/8 TYPES & CONSTANTS TYPES & CONSTANTS
21 7/8/2018 FUNCTIONS AND PROCEDURES BIPOLAR LOGIC
22 9/8,9/8 LIBRARIES AND PACKAGES FUNCTIONS AND PROCEDURES
 23 10/8/2018 STRUCTURAL DESGN ELEMENTS FUNCTIONS AND PROCEDURES
24 13/8 BEHAVIORAL DESIGN ELEMENTS FUNCTIONS AND PROCEDURES
August25 14/8 BEHAVIORAL DESIGN ELEMENTS FUNCTIONS AND PROCEDURES
26 16/8,16/8 TIME DIMENSION AND SIMULATION SYNTHESIS FUNCTIONS AND PROCEDURES
27 17/8,18/8 TEST BENCHES, VHDL FEATURES FOR SEQUENTIAL LOGIC DESGN, SYNTHESIS FUNCTIONS AND PROCEDURES
28 20/8,21/8,23/8 PROBLEMS

30 UNIT-3 E15COMBINATIONAL LOGIC

UNIT-3 COMBINATIONAL LOGIC DESIGN PRACTICES DESIGN PRACTICES
24/8,25/8 DECODERS DECODERS
31 28/8 ENCODERS ENCODERS
32 28/8 MULTIPLEXERS COMPARATORS
33 29/8,30/8 COMPARATORS COMPARATORS
34 8/31/2018 ADDERS ADDERS
35 1/9/2018 THREE STATE DEVICES THREE STATE DEVICES
36 3/9/2018 MULTIPLEXERS MULTIPLEXERS
37 4/9/2018 DE MULTIPLEXERS DE MULTIPLEXERS
38 5/9/2018 ADDERS ADDERS
39 6/9/2018 ADDERS ADDERS
40 7/9/2018 SUBTRACTORS SUBTRACTORS
41 8/9/2018 COMBINATIONAL MULTIPLIERS

42 COMBINATIONAL MULTIPLIERS COMBINATIONAL MULTIPLIERS

9/9/2018
DESIGNING USING COMBINATIONAL
43 DESIGNING USING COMBINATIONAL PLD'S
10/9/2018 PLD'S
DESIGNING USING COMBINATIONAL
44 11/9/2018 DESIGNING USING COMBINATIONAL PLD'S
PLD'S
DESIGNING USING COMBINATIONAL
45 12/9/2018 DESIGNING USING COMBINATIONAL PLD'S
PLD'S
46 13/9/2018 PLA'S PLA'S
47 14/9/2018 PAL'S PAL'S
48 16/9/2018 PROM'S CMOS PLD'S
49 17/9/18

50
18/9/18
51 19/9/18
52 20/9/18 FIRST MID TERM EXAMINATION
October
53 22/9/2018
 FIRST MID TERM EXAMINATION
October
54 24/9/2018
55 25/9/2018
56 26/9/2018
57 27/9/2018 COMBINATIONAL MULTIPLIERS, VHDL MODELS FOR THE ABOVE ICS
58 27/9/2018 COMBINATIONAL MULTIPLIERS, VHDL MODELS FOR THE ABOVE ICS
59 3/10/2018 COMBINATIONAL MULTIPLIERS, VHDL MODELS FOR THE ABOVE ICS
60 4/10/2018 UNIT-4 SEQUENTIAL MACHINE DESIGN PRACTICES
REVIEW OF DESIGN OF STATE MACHINES
61 5/10/2018 STANDARD BUILDING BLOCK ICS FOR SHIFT REGISTERS
62 7/10/2018 PARALLEL / SERIAL CONVERSION
63 10/10/2018 SHIFT REGISTER
64 11/10/2018 COUNTERS,LSFR COUNTER
November
65 12/10/2018 RING COUNTERS
66 14/10/2018 JOHNSON COUNTERS
67 17/10/2018 PROBLEMS
68 18/10/2018 UNIVERSITY QUESTION PAPER DISCUSSION
69 21/10/2018 UNIT-5 DESIGN EXAMPLES BARREL SHIFTER+C34
70 24/10/2018 COMPARATORS
71 25/10/2018 FLOATING POINT ENCODER
72 26/10/2018 DUAL PARITY ENCODER
73 28/10/2018 SEQUENTIAL LOGIC DESIGN:LATCHES
74 31/10/2018 FLIP FLOPS, COUNTERS
75 1/11/2018 SHIFT REGISTERS AND THEIR VHDL MODELS
76 2/11,3/11 DUAL PARITY ENCODER
77 PLD'S
78 UNIVERSITY QUESTION PAPER DISCUSSION
79 REVISION
80 REVISION
 Class: III B.TECH-B,I-SEM

deviation Reason for Verified by HOD FEEDBACK S

Deviation

codevita classes
codevita classes
codevita classes
codevita classes

codevita classes

YES ORIENTATION DAY

YES BANDH

YES deviation-10 periods

satisfactory

no no deviation satisfactory
yes deviation-02 periods satisfactory

no no deviation satisfactory

no no deviation satisfactory

no no deviation satisfactory

no deviation satisfactory