EXPERIMENT NO:1

HDL CODE TO REALIZE ALL LOGIC GATES

AIM
To develop the source code for logic gates by using VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. XILINX 9.2i
2. FPGA-SPARTAN-3

LOGIC DIAGRAM
VERILOG SOURCE CODE

module logicgates(a,b,c);

input a;

input b;

output [6:0]c;

assign c[0] = a&b;

assign c[1] = a|b;

assign c[2] = a^b;

assign c[3] = ~(a&b);

assign c[4] = ~(a|b);

assign c[5] = ~(a^b);

assign c[6] = ~a;

endmodule

Test Bench:

module tb_logicgates;

reg a,b;

wire [6:0]c;

logicgates U1(a,b,c);

initial begin

a=1’b0;b=1’b0;

#5

a=1’b1;b=1’b1;

#10

$stop();
end

endmodule

SIMULATION RESULT

RESULT
Thus the outputs of all logic gates are verified by synthesizing and simulating the verilog
code.

VIVA QUESTIONS

1. Which gate output will be a LOW for any case when one or more inputs are zero.

2. If a signal passing through a gate is inhibited by sending a low into one of the inputs, and
the output is HIGH the gate is

3. Which logic gate can be used as a single transistor.

4. How many NAND circuits are contained in a 7400 NAND IC?

5. How many truth table entries are necessary for a four-input circuit?

6. Which IC’s can be used for AND ,OR ,INVERTER gates

7. Which IC’s can be used for NAND ,NOR gates.

 EXPERIMENT NO : 2
DESIGN OF 2-TO-4 DECODER
AIM
To develop the source code for decoder by using verilog and obtain the simulation,
synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. XILINX 9.2i
2. FPGA-SPARTAN-3.

LOGIC DIAGRAM

A1 A0 EN C3 C2 C1 C0
X X 0 0 0 0 0
0 0 1 0 0 0 1
0 1 1 0 0 1 0
1 0 1 0 1 0 0
1 1 1 1 0 0 0

VERILOG SOURCE CODE

module decoder(a,c,en);

input [1:0]a;

input en;

output [3:0]c;

reg [3:0]c;
always @(a,en)

begin

if(en= =1'b0)

c=4'b0000;

else

case(a)

2'b00: c=4'b0001;

2'b01: c=4'b0010;

2'b10: c=4'b0100;

2'b11: c=4'b1000;

endcase

end

endmodule

Test Bench:

module tb_decoder;

reg [1:0]a;

reg en;

wire [3:0]c;

decoder U1(a,c,en);

initial begin

a=2’b00;

en=1’b0;

#5

a=2’b00;
en=1’b1;

#5

a=2’b01;

#10

$stop();

end

endmodule

SIMULATION RESULT

RESULT
Thus the output of decoder is verified by synthesizing and simulating the verilog code.
VIVA QUESTIONS
1. What is decoder?

2. For a 2- I/P decoder how many O/P‟s are produced

3. A decoder with „n‟ input produces max. of __ no. of minterms.

4. Draw the 2 to 4 line decoder with only nor gates.

5. Difference b/w de multiplexer and decoder

6. what is an IC number for 3x8decoder..

 EXPERIMENT NO:3
DESIGN OF 8-TO-3 ENCODER (WITH OUT AND WITH PRIORITY)
AIM
To develop the source code for encoder by using VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. XILINX 9.2i
2. FPGA-SPARTAN-3

LOGIC DIAGRAM
ENCODER WITHOUT PRIORITY

VERILOG SOURCE CODE

module encoder(a,b,en);

input[7:0]a;

input en;

output reg[2:0]b;

always@( en,a )
begin

if(en= = 1’b0)

b=3’b000;

else

case(a)

8'b00000001: b=3'b 000;

8'b00000010: b=3'b 001;

8'b00000100: b=3'b 010;

8'b00001000: b=3'b 011;

8'b00010000: b=3'b 100;

8'b00100000: b=3'b 101;

8'b01000000: b=3'b 110;

8'b10000000: b=3'b 111;

default:b=3'bXXX;

endcase

end

endmodule

Test Bench:

module tb_encoder;

reg [7:0]a;

reg en;

wire [2:0]b;

encoder U1(a,b,en);

initial begin

en=1’b0;
a=8’b00000001;

#5

en=1’b1;

a=8’b00000010;

#5

a=8’b00001000;

#10

$stop();

end

endmodule

SIMULATION RESULT
ENCODER WITH PRIORITY

VERILOG SOURCE CODE

module encoderpp(en,a,b);

input [7:0]a;

input en;

output [2:0]b;

reg [2:0]b;

always@(a,en)

begin

if(en= =1'b0)

b<=3'b000;

else

case(1)

a[7]:b=3’b111;

a[6]:b=3’b110;

a[5]:b=3’b101;
a[4]:b=3’b100;

a[3]:b=3’b011;

a[2]:b=3’b010;

a[1]:b=3’b001;

a[0]:b=3’b000;

endcase

end

endmodule

Test Bench:

module tb_encoderpp();

reg [7:0]a;

reg en;

wire [2:0]b;

encoderpp u1 (en,a,b);

initial begin

en=1’b0;

a=8’b00000010;

#5

en=1’b1;

a=8,b00001000;

#10

a=8’b00101101;

#10

a=8’b01001011;

#20
$stop();

end

endmodule

SIMULATION RESULT

RESULT
Thus the output of encoder is verified by synthesizing and simulating the verilog code.

VIVA QUESTIONS
1. What is encoder?

2. Define priority encoder?

3. What is the IC number for encoder and priority encoder?

4. Applications of encoder?
 EXPERIMENT NO : 4

DESIGN OF 8:1 MULTIPLEXER AND 1:8 DEMULTIPLEXER

AIM
To develop the source code for multiplexer and demultiplexer by using verilog and obtain
the simulation, synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. XILINX 9.2i
2. FPGA-SPARTAN-3

LOGIC DIAGRAM

MULTIPLEXER TRUTH TABLE

EN S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Z
0 X X X X X X X X X X X 0
1 0 0 0 0 0 0 0 0 0 0 1 1
1 0 0 1 0 0 0 0 0 0 1 0 1
1 0 1 0 0 0 0 0 0 1 0 0 1
1 0 1 1 0 0 0 0 1 0 0 0 1
1 1 0 0 0 0 0 1 0 0 0 0 1
1 1 0 1 0 0 1 0 0 0 0 0 1
1 1 1 0 0 1 0 0 0 0 0 0 1
1 1 1 1 1 0 0 0 0 0 0 0 1
VERILOG SOURCE CODE
module mux (y,s,en,z);

input [7:0] y;

input [2:0] s;

input en;

output z;

reg z;

always @ (y,s, en)

begin

if(en= =1'b0)

z=1'b0;

else

case(s)

3'b000 : z=y[0];

3'b001 : z=y[1];

3'b010 : z=y[2];

3'b011 : z=y[3];

3'b100 : z=y[4];

3'b101 : z=y[5];

3'b110 : z=y[6];

3'b111 : z=y[7];

endcase

end

endmodule
Test Bench:

module tb_mux;

reg [7:0]y;

reg [2:0]s;

reg en;

wire [2:0]z;

mux u1(y,s,en,z);

initial begin

en=1’b0;

y=8’b10101000;

s=3’b000;

#10

en=1’b1;

y=8’b11010100;

s=3’b001;

#5

s=3’b010;

#5

$stop();

end

endmodule
SIMULATION RESULT

DEMULTIPLEXER

TRUTH TABLE

I S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
VERILOG SOURCE CODE

module demux(a,y,s,en);

output reg [7:0]y;

input [2:0]s;

input en,a;

always@(en,s,a)

begin

y=8’b00000000;

if(en = = 1'b0)

y = 8'b00000000;

else

case(s)

3'b 000 : y [0]=a;

3'b 001 : y [1]=a;

3'b 010 : y [2]=a;

3'b 011 : y [3]=a;

3'b 100 : y [4]=a;

3'b 101 : y [5]=a;

3'b 110 : y [6]=a;

3'b 111 : y [7]=a;

endcase

end

endmodule
Test Bench:

module tb_demux;

reg en,a;

reg [2:0]s;

wire [7:0]y;

demux u1(a,y,s,en);

initial begin

en=1’b0;

a=1’b1;

s=3’b000;

#5

en=1’b1;

a=1’b0;

s=3’b001;

#5

a=1’b1;

s=1’b010;

#10

$stop();

end

endmodule
SIMULATION RESULT

RESULT
Thus the output of Multiplexer and Demultiplexer is verified by synthesizing and
simulating in verilog code.

VIVA QUESTIONS
1. What is a multiplexer?

2. What is a de-multiplexer?

3. What are the applications of multiplexer and de-multiplexer?

4. Derive the Boolean expression for multiplexer an d de-multiplexer.

5. How do you realize a given function using multiplexer

6. What is the difference between multiplexer & de-multiplexer?

7. In 2n to 1 multiplexer how many selection lines are there?

8. How to get higher order multiplexers?

9. Implement an 8:1 mux using 4:1 muxes?

10. what is an IC number for 8x1 multiplexer and 1x8 demultiplexer

 EXPERIMENT NO: 5
DESIGN OF 4-BIT BINARY TO GRAY CONVERTER
AIM
To develop the source code for binary to gray converter by using verilog and obtained the
simulation, synthesis and implement into FPGA.

SOFTWARE & HARDWARE

1. XILINX 9.2i
2. FPGA-SPARTAN-3

CODE CONVERTER (BINARY TO GRAY)

LOGIC DIAGRAM TRUTH TABLE

VERILOG SOURCE CODE

module BtoG(b,g);

input [3:0] b;

output [3:0]g;

assign g[3]=b[3];

assign g[2]=b[2]^b[3];

assign g[1]=b[2]^b[1];
assign g[0]=b[1]^b[0];

endmodule

Test Bench:

module tb_btog;

reg[3:0]b;

wire[3:0]g;

btog gg(b,g);

initial begin

b=4’b0000;

#5 b=4’b0001;

-----

-----

#5 b=4’b1111;

#20

$stop;

end

endmodule

SIMULATION RESULT
RESULT
Thus the output of binary to gray converter is verified by synthesizing and simulating
the verilog code.

VIVA QUESTIONS
1. Realize the Boolean expression for binary to gray and gray to binary converter?

2. What are code converter?

3. What is the necessity of code conversions?

4. What is gray code?

5. What is the IC number for binary to gray converter?

 EXPERIMENT NO:6
DESIGN OF 4 BIT COMPARATOR
AIM
To develop the source code for 4 bit comparator by using verilog and obtained the
simulation, synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. XILINX 9.2i
2. FPGA-SPARTAN-3

LOGIC DIAGRAM
VERILOG SOURCE CODE
module comparator(a,b,equal,greater,lower);

input [3:0]a;

input [3:0]b;

output reg equal,greater,lower;

always @(a , b)

begin

if(a<b)

begin

equal=0;

greater=0;

lower=1;

end

else if(a>b)

begin

equal=0;

greater=1;

lower=0;

end

else

begin

equal=1;

greater=0;

lower=0;

end
end

endmodule

Test Bench:

module tb_comparator;

reg [3:0]a,b;

wire equal,greater,lower;

comparator u1(a,b,equal,grater,lower);

initial begin

a=4’b0000;

b=4’b0000;

#5

a=4’b0010;

b=4’b0001;

#5

$stop();

end

endmodule

SIMULATION RESULT
RESULT
Thus the output of 4 bit comparator is verified by synthesizing and simulating the
VERILOG code.

VIVA QUESTIONS
1.What is Magnitude Comparator?
2. To form a 12 – bit comparator how many 4-bit comparators are connected in cascaded form.

3. The IC 7485 is a package and is a ____ comparator.

4. How many cascaded input are there for a 4-bit comparator.

5 what is an IC number for 4 bit comparator.

 EXPERIMENT NO:7
DESIGN OF FULL ADDER USING THREE MODELLING STYLES
AIM
To develop the source code for full adder using three modeling styles by using verilog
and obtained the simulation, synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. XILINX 9.2i
2. FPGA-SPARTAN-3

LOGIC DIAGRAM

VERILOG SOURCE CODE

Dataflow Modeling:

module fuladdder(a,b,c,sum,carry);

input a,b,c;

output sum,carry;

assign sum=a^b^c;

assign carry=((a&b)|(b&c)|(c&a));

endmodule
Behavioral Modeling:

module FuladderBM(a,b,c,sum,carry);

input a,b,c;

output reg sum,carry;

always @(a or b or c)

begin

sum=a^b^c;

carry=((a&b)|(b&c)|(c&a));

end

endmodule

Structural Modeling:

module fastruct(a,b,c,sum,carry);

input a,b,c;

output sum,carry;

wire t1,t2,t3;

xor(t1,a,b);

xor(sum,t1,c);

and(t2,a,b);

and(t3,t1,c);

or(carry,t2,t3);

endmodule

Test Bench:

module tb_fulladder;

reg a,b,c;

wire sum,carry;
fulladder u1(a,b,c,sum,carry);

initial begin

a=1’b0;

b=1’b0;

c=1’b0;

#5

---

a=1’b1;

b=1’b1;

c=1’b1;

#5

$stop();

end

endmodule

SIMULATION RESULT

RESULT
Thus the outputs of full adder using three modeling styles are verified by synthesizing
and simulating the verilog code.
 EXPERIMENT NO:8
DESIGN OF FLIP FLOPS (SR,JK,D,T)
AIM
To develop the source code for FLIP FLOPS by using VERILOG and obtained the
simulation, synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. XILINX 9.2i
2. FPGA-SPARTAN-3

LOGIC DIAGRAM
SR FLIPFLOP
CLK S R Q QT+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 x
1 1 1 x

VERILOG SOURCE CODE

SR FLIPFLOP

module srff(clk,rst,s,r,q,qb);

input clk,rst,s,r;

output reg q,qb;

always@(posedge clk , rst)

begin

if(rst= =1'b0)
begin

q=q;

qb=qb;

end

else if(s= =1'b0 && r= =1'b0)

begin

q=q;

qb=qb;

end

else if(s= =1'b0 && r= =1'b1)

begin

q=q;

qb= ~q;

end

else if(s==1'b1 && r==1'b0)

begin

q=1'b1;

qb=~q;

end

else if(s= =1'b1 && r= =1'b1)

begin

q=1'bX;qb=~q;

end

end

endmodule
Test Bench:

module tb_srff;

reg s,r,clk,rst;

wire q,qb;

srff u1(clk,rst,s,r,q,qb);

initial begin

clk=1’b0;

forever

#5

clk=~clk;

end

initial begin

rst=1’b0;s=1’b0;r=1’b0;

#5 rst=1’b1;s=1’b0;r=1’b1;

#5 s=1’b0;r=1’b1;

#5

$stop();

end

endmodule

SIMULATION RESULT
JK FLIPFLOP

CLK J K Q QT+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

VERILOG SOURCE CODE

module jkff(clk,rst,j,k,q,qb);

input clk,rst,j,k;

output reg q,qb;

always@(posedge clk ,rst)

begin

if(rst= =1'b0)

begin

q=q;

qb=qb;

end

else if(j= =1'b0 && k= =1'b0)

begin

q=q;

qb=qb;

end

else if(j==1'b0 && k==1'b1)

begin

q=q;

qb=~q;

end

else if(j==1'b1 && k==1'b0)

begin

q=1'b1;

qb=~q;

end

else if(j==1'b1 && k==1'b1)

begin

q=~q;

qb=~qb;

end

end

endmodule

Test Bench:

module tb_jkff;

reg j,k,clk,rst;

wire q,qb;

jkff u1(clk,rst,j,k,q,qb);

initial begin

clk=1’b0;

forever

#5
clk=~clk;

end

initial begin

rst=1’b0;j=1’b0;k=1’b0;

#5 rst=1’b1;j=1’b0;k=1’b1;

#5 j=1’b0;k=1’b1;

#5

$stop();

end

endmodule

SIMULATION RESULT
D FLIPFLOP TRUTH TABLE

CLK D Q QT+1
0 0 0
0 1 0
1 0 1
1 1 1

VERILOG SOURCE CODE

module dff(d,clk,rst,q,qb);

input d,clk,rst;

output reg q,qb;

always@(posedge clk ,rst)

begin

if(rst= =1'b0)

begin

q=1'b0;

qb=~q;

end

else if(d= =1'b0)

begin

q=1'b0;

qb=~q;

end

else

begin

q=1'b1;
qb=~q;

end

end

endmodule

Test Bench:

module tb_dff;

reg d,clk,rst;

wire q,qb;

dff u1(d,clk,rst,q,qb);

initial begin

clk=1’b0;

forever

#5

clk=~clk;

end

initial begin

rst=1’b0;d=1’b0;

#5 rst=1’b1;d=1’b0;

#5 d=1’b0;

#5

$stop();

end

endmodule
SIMULATION RESULT

T FLIPFLOP TRUTH TABLE

CLK T Q QT+1
0 0 0
0 1 1
1 0 1
1 1 0

VERILOG SOURCE CODE

module tff(T,clk,rst,q,qb);

input T,clk,rst;

output reg q,qb;

always@(posedge clk , rst)

begin

if(rst= =1'b0)

begin

q=1'b0;

qb=~q;

end
else if(T= =1'b0)

begin

q=q;

qb=~q;

end

else

begin

q=~q;

qb=~qb;

end

end

endmodule

Test Bench:

module tb_tff;

reg T,clk,rst;

wire q,qb;

tff u1(T,clk,rst,q,qb);

initial begin

clk=1’b0;

forever

#5

clk=~clk;

end

initial begin

rst=1’b0;T=1’b0;
#5 rst=1’b1;T=1’b0;

#5 T=1’b0;

#5

$stop();

end

endmodule

SIMULATION RESULT

RESULT
Thus the outputs of Flip flops are verified by synthesizing and simulating the verilog
code.

VIVA QUESTIONS
1. what is flip-flop?

2. what is disadvantage of SR flip-flop?

3. what is disadvantage of JK flip-flop?

4. To remove race around condition what we use?

5. what is race around condition?

6. what are the characteristic equation for T flip-flop?

7. D flip-flop is used for?

8. what is full form of T flip-flop?

 9. Define a latch?
EXPERIMENT NO : 9
FINITE STATE MACHINE DESIGN
AIM
To develop the source code for FSM by using VERILOG and obtained the simulation,
synthesis, place and route and implement into FPGA.

SOFTWARE & HARDWARE

1. XILINX 9.2i
2. FPGA-SPARTAN-3

LOGIC DIAGRAM

Figure : State Transition Diagram

VERILOG SOURCE CODE

module fsm(x,rst,clk,z);

input x,clk,rst;

output z;

reg [1:0]state;
parameter a=2’b00 , b=2’b01 , c=2’b10 , d=2’b11;

always@(posedge clk )

begin

if(rst= =1’b0)

state=a;

else

case(state)

a:begin

if(x= =0)

state=a;

else

state=b;

end

b:begin

if(x= =0)

state=c;

else

state=b;

end

c:begin

if(x= =0)

state=a;

else

state=d;

end
d:begin

if(x= =0)

state=c;

else

state=b;

end

endcase

end

assign z=(state= =)? 1:0;

endmodule

Test Bench:

Module tb_fsm;

Reg clk,rst,x;

Wire z;

fsm hh(x,rst,clk,z);

Initial begin

Clk=1’b0;

Forever

#5 clk=~clk;

End

Initial begin

X=0;rst=0;

#10 x=1;rst=1;

#10 x=1;

#10 x=0;
#20;

$stop;

endendmodule

SIMULATION RESULT

RESULT
Thus the output of FSM are verified by synthesizing and simulating the verilog code.

VIVA QUESTIONS
1. What is FSM

2. What is the difference between Mealy and Moore FSM?

3. What are various types of state encoding techniques? Explain them.

4. What are Difference between one hot and binary encoding?

5. Design a FSM (Finite State Machine) to detect a sequence 10110?