DVP-M35/S300/S305/S315/ S500D/S 505D/$715 Manual: Operation

DVP-M35/S300/S305/S315/
S500D/S 505D/$715
OPERATION MANUAL
_ CD/DVD PLAYER
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Contents
1. Outline ....................................................................................................................................
6
1-1. Series line-up ...............................................................................................................6
1-2. External appearance diagram ..................................................................................7
1-3,.Internal appearance diagram (top view) ..............................................................8
1-4. Disc drive unit ........................................................................................................... 10
1-5. Block diagram ........................................................................................................... 13
2. SIGNAL PROCESSING BLOCK ................................................................... 15
2-1. DVD RF FRONT END ..........................................................................................15

2-1-1. Attenuation of OP Output Signals ......................................................................... 16
2-1-2. HPF ........................................................................................................................ 16
2-1-3. RF Front End Processing: IC001 SSI33P3720 ...................................................... 16
2-2. CD RF FRONT END ..............................................................................................19
2-3. RF SIGNAL PROCESSING BLOCK ...............................................................2O
2-4. Decrypt Block ...........................................................................................................21
2-5. AV Decoder Block ...................................................................................................21
2-6. OSD Block .................................................................................................................21

L
2-7,. DNR, Video Encoder Blocks ................................................................................23
2-8. Clock Generation Block ......................................................................................... 24
2-9. AC-3 Decoder Block ...............................................................................................25
2-10. Audio L, R 2ch Signal Block .............................................................................26
2-11. Audio 5. lch Signal Block ....................................................................................27
2-12. DVP-S715 AU-205 Board Block Diagram ....................................................28
2-13. System Control Block ...........................................................................................29
2-14. Interface Control Block ........................................................................................29

3. SERVO BLOCK ...........................................................................................................
33
3-1. General Description of Servo Circuits ............................................................... 33

3-1-1. Optical Pickup Control .......................................................................................... 33
3-1-2. Sled Control ........................................................................................................... 33
3-1-3. Spindle Control ...................................................................................................... 33
3-1-4. Tilt Control ............................................................................................................ 33
3-I-5. Disc Loading and Chucking .................................................................................. 33
3-1-6. Disc Judgment ....................................................................................................... 33
3-2. Servo Operation at DVD Play .............................................................................. 34

3-2-2. Sled Control ........................................................................................................... 41
3-2-3. Spindle Control ...................................................................................................... 43
3-2-4. Tilt Control ............................................................................................................ 44
3-3. Servo Operation at CD and Video CD Playing ...............................................46

3-3-2. Sled Control ........................................................................................................... 50
3-3-3. Spindle Control ...................................................................................................... 50
3-3-4. Tilt Control ......................................................................... :.................................. 50
3-4. Disc Loading and Chucking ..................................................................................50

3-4-1. Motor Driver .......................................................................................................... 51
3-4-2. Tray Position Detection ......................................................................................... 51
3-5. Differentiation of Disk Type ................................................................... 52

3-5-1. CD/DVD Differentiation ........................................................................................ 52
3-5-2. SL/DL Differentiation ............................................................................................ 52
3-5-3. Differentiation ............ i........................................................................................... 52
3-6. Block Diagram (Servo) ...........................................................................................53
4. IC PIN DESCRIPTION ..........................................................................................

55
4-1. ARP CXD1865R (IC806 on MB-80 board) ..................................................... 55

4-1-1. Block Diagram .................................................................................... ................... 55
4-1-2. Pin Functions ....................................................................................... '.................. 57
4-2. AV Decoder L64020 (IC203 on MB-78 board) ..............................................62

4-2-1. Block Diagram ....................................................................................................... 62
4-2-2. Pin Assignment ...................................................................................................... 63
4-3. Digital Signal Processor CXD8730R (1C506 on MB;.78 board) ............... 65

4-3:1. Pin Assignment ...................................................................................................... 65
4-3-2. Pin Functions ......................................................................................................... 66
4-4. AC-3 Decoder MB86342 (IC104 on MB-78 board) ......................................70

4-4-1. Block Diagram ....................................................................................................... 70
4-4-2. Pin Functions ......................................................................................................... 71
-4-

4-5. Large Gate Array CXD8728 (IC804 on MB-78 board) ................................ 72
4-5-1. Block Diagram .................................................................................................... 7..72
4-5-2. Pin Functions ........................................................................................................ 73
4-6. Middle Gate Array CXD8746 (IC 101 on MB-78 board) ............................. 78
4-6-1. Block Diagram ....................................................................................................... 78
4-6-2. Pin Functions ......................................................................................................... 79
' 4-7. Small Gate Array CXD8747 (IC807 on MB-78 board) ............................... 81
4-7-1. Block Diagram ....................................................................................................... 81
4-7-2. Pin Assignment ..................................... ............................ :.................................... 82
5. OVERALL BLOCK DIAGRAM ......................................................................

83
5-1. RF, Servo, Audio, Power Block Diagram ......................................................... 83
5-2. Signal Processing Block Diagram ....................................................................... 89

1. Outline
This guidebook describes the DVD-Video.

It also describes the functions not used in the DVP Series.
For the functions used in the DVP Series, refer to Secions 2 to 5, or Service Manual.
1-1. Series line-up

O Basic Dolby digital model
DVP-S500D NTSC U/C specifications (120V)
DVP-S500D NTSC General overseas specifications (110 to 240V)
DVP-S501D NTSC Japan specifications (100V)
DVP-S505D PAL/NTSC Hong Kong specifications (230V)
*AC3 : 5.1 ch OUT (With built-in decoder)
*Output terminal : S terminal, video, audio x2

Color difference output xl
® 280 size model
DVP-M30 NTSC Japan specifications (100V)

DVP-M35 PAL/NTSC China specifications (230V)
DVP-M35 PAL/NTSC Hong Kong specifications (230V)
DVP-M35 PAL/NTSC General overseas specifications (110 to 240V)
DVP-M35 PAL/NTSC Singapore specifications (230V)
*Pixy size
*Output terminal: S terminal, video, audio x2
® Basic model
DVP-S300 NTSC U/C specifications (120V)
DVP-S300 NTSC General overseas specifications (110 to 240V)
DVP-S305 PAL/NTSC China specifications (230V)
DVP-S305 PAL/NTSC Taiwan specifications (ll0V)
DVP-S305 PAL/NTSC General overseas specifications (110 to 240V)
DVP,S305 PAL/NTSC Singapore specifications (230¥)
DVP- $315 PAL/NTSC European specifications (230V)
DVP-S315 PAL/NTSC Great Britain specifications (230V)
DVP-S715 PAL/NTSC European specifications (230V)
DVP-S715 PAL/NTSC Great Britain specifications (230V)
DVP-S715 PAL/NTSC Australia specifications (230V)
-6-

*Output terminal AC3
21P Euro (DVP-S315, $715)

S terminal, video, audio x l
Note: Video-CDs recorded in the PAL format can be played only by general overseas
specifications models.
1-2. External appearance diagram

(_) Basic Dolby digital models
DVP-S'500D
DVP-S501D/S505D
98ram
(_) 280 size models
T
91mm

(_ Basic models
DVP-S300/S305/S315
DVP-S715
1-3. Internal appearance diagram (top view)
(_) Basic Dolby digital models
YS board
(COMPONENT VIDEO)
J
AU board
(AUDIO)
.__.__F3
.........................
I
Power block
(SWITCHING
REGULATOR
HP board
(DVP-S300/S315)
MB board
(HEAD PHONE)
ME board (SIGNAL PROCESS/SERVO)
(DVP-S305)
(MIC)
i
i
LE board
(LED)
Disc drive unit
1 i
' ;---; ' /
/
FR board
FRONT SIDE \
FL board
(IR/POWER SWITCH) (FL DRIVER/FUNCTION SWITCH)

(_) 280 size models
POWER BLOCK _..

j AU-board
MB-board
j HP board
(HEAD PHONE)
FL board
--....,
I o,sco i,vou , , , '1
i i
I I
\ / /
FRONT SIDE
LE board
(_) Basic models
PS board (DVP-S715) Power transformer AU board
(AUDIO POWER) (DVP-S715) ,_ (AUDIO)
ER board
(DVP-S315/S715)
............. .......... _t IIII111
III tI
lIlllll_........ JI 111 _ Iltl""IIll " (EURO AV)
Power
block
(SWITCHING
REGULATOR)
MB board
(SIGNAL PROCESS
/SERVO)
HP board
(HEAD PHO._
Disc drive unit
iii f --J I
' ' /
/ FRONT SIDE
FL board FL board
(IR/POWER SWITCH) (FL DRIVEFVFRUNCTION SWITCH)

1-4. Disc drive unit
1) Configuration of disc drive unit.
[Optical block specifications]
CD system OPT
DVD system OPT
Skew adjustment Tilt motor
i Thread motor
Configuration of thread system

Spindle motor
Tilt sensor
Optical block ass'y
Specification DVD system OPT DC system OPT
Non-deflection,
Non-deflection, limited optical system
Optical system unlimited optical system (laser coupler)
Drive unit 2-shaft 2-shaft
Object lens Glass Plastic
Focus error Stigmatic system Differential 3-division system
Tracking error DPD system TPP system,
Laser beam 650nm 780nm
- 10-

2) Optical route diagram
Las Objec ator
_.... lens
k Mirror _)_._,._
y J
ForCD (__ ' ' -_"_ OEIC

Laser diode
Y
For DVD
-11-

1-5. Block diagram
/
/
I............ OPT COAX
.i : &(_)
256K i -_
SRAM I , i 2CHLP
F AC-3
32M
4M DRAM IMB BOARD1 SDRAM I Lc8D910R51v
H (MBA8C63342)6CH
DSP __l]__ _x3 2C_PFB_F
___l--;__
ITKBOARDI
AU-L,R
MPEG
© SPDIF OUT
DVDFRONTEND
I (SSI33P3720)
OUT ......
--- --
-_
SHSerial"l
_-- B_(OXD8746Q)[
MGA ____.1
I
I_
I I 2CH DAC I T-I
I F_
I_I(oxDa750N)I_
_PF---_
BUFF I r
,..
* D
ARP AVDEC "-_1 __ rTCL_ ..........
(L64020) HEAD
(RFProcesser) PHONE
_. CDRF OSD_ R,G,B,I / ill / ,, --
[3:0] -- IF Serial OSD / , LP.F
(CXD1865)
SHSerial - Bus_ (MB90096) BUFf /
- s_oo ,4
I '11,
(CXA1081Q)
OARDI
I
[ 'i
I
SPDLMOTOR I CCIR601 ___ II _ l[ '- .... .-_------ -------------- -----T ---

SPDLDR ParallelBUS
@ ' Z __SHSeri_ SHSerial !1 ÷ EU BOARD

(LB 1896) 1411
AI IIBUS-Gp'_
BUS-ep2
_ ,
.................... P 21p
ERORR SGAI
4_4_ [ZJ SWBLOCK
SLEDMOTOR SLEDDR
CPRUo
EMXT II CPRuA
EMxT
I
'v'
&
LPF
21p
EURO
EURO
.I EXPi-qTd--
:_
@. ,
I (LA6527)
_E SYSp-COM L GATE
ARRAY
IISHSerial (CDX1854) L----J 75aDR
I
SERVO ARI (SH)
DSP H lG IAY 1 _(CXD8728) l_
I
FOCUSCOIL I (CXD8730R)i
I
I(C×D}728)
I E_o_< ___ >
_ ,
TRACKING
COIL
i
i
FCS!FRKDR
(BA5981) BUS-Gpl
SHSerial
_-- SHSera
BUS-Gp2
IFSerial
BUS
I1<_
BUS-G"3/_
VIDEO
ENCODER
SHSerial (CXD1914)
IR,G,B
I
LPF
"_ EUROONLY RGBOUT
V OUT
©
U
LOADINGMOTOR
I/Fp-COM
/1
CTRL-A1
BUS-Gp2
6dBAMP
75_ DR
__i) Y/OOUZ
_ I- - "" 1 16L
(MB90678)
S-LINK
@
I TILT/LDDR l" "_ S-LINK
TILTMOTOR I
1
(NJM2191)
SIRCS
- _
®, (BA5912)
RESET
I
(ppc393) I
or
1,4.
t 7-
CTRL-A1
i FLO
driver FLO
F_ONT(FL, FR)BOAR_
- 13- - 14 -

2. Signal Processing Block 2-1-1. Attenuation of OP Output Signals
The RF signals (RFP, RFM) output from OP for DVD are attenuated by R066 and
R064 so that they satisfy the input amplitude allowable level of IC006 in the post
Block which perfornls various signal proccssings from the RF frollt cnd to the output of stage.
the audio signal and video signal. (About IVpp D (*'3) for SL (*1) disc. In actual, only the RFP signal is output be-
cause RFM signal is connected to the ground in the OP block.
2-1. DVD RF Front End
2-1-2. ttPF
Low frequency component of the attenuated RF signal is removed by a high pass

TK-47 board
filter (HPF) that cuts off the frequency (about 3.16kHz) determined by the input
0051 impedance of C046, C047, and IC006, then it is entered to the IC001.
_
oo o _ _
,coo,
8SI33P3720
RFIDVD
When delecl H 2-1-3. RF Front End Processing: IC001 SSI33P3720

IC=3.16kHz _ CNO0_ TO MB-78 board ICs0b
CR001
R066 ,0047
(1) ATT block
.ru ._ - t F_ 4) The RF signal entered from IC006 RFP(_) and RFN(_ is entered to the ATT
i 0046 ',V_a..,,,,o0
_ <"_ _- c053
...L..
' SL:3 6 block. In this block, this processing is executed to attenuate the signal below
', DL:5/16 !
_.,.T T signal amplitude level determined according to the specification (about
]_D I P_ VCC
200mVwD, determined depending on AGC input allowable level) in order to
utilize high performance of IC.
SDATA
SDEN
SLCK --
i 17171 ii , After processing, the signal is output from IC006 ATOP_ and ATONe).
ATT: Set to 3/16 for SL disc, or 5/16 for DL (*2) disc.

These are operated by the command register set via serial interface.
(2) AGC block
Figure 2-1. TK-47 Board IC006 SSI33P3720 RF/DVD
ATT output IC006 ATOP(_ and ATONe) are processed below AGC allow-
able level as mentioned above, then they are AC-coupled by C050 and C051,
and entered respectively to AGC block input IC001 AIP_ and AIN(_.
The AGC block controls gain of AGC amplifier so that constant input signal
(1VppD) is supplied to the IC006 DIP@ and DIN_). The AGC compares
about 1.4V about 1.4V full-wave rectified input signal to IC006 DIP(_ and DIN(_) with reference
level, and repeats decay and attack while keeping a balance with the product
of current by time so as to attain the optimum gain.
Decay: When input signal to IC006 DIP(_ and DIN(_) is below I Vppl) ,
C052 (CByp) is discharged with 41aA decay current. In this case,
range 500mV lO0ns range 500mV 20ns AGC amplifier gain gradually increases.
Attack:
When input signal to IC006 DIP_ and DIN(_) is over 1VpeD, C052
Figure 2-2. Figure 2-3. (CuvP) is charged with 0.18mA attack current. In this case, AGC
RF (eye pattern) waveform at DVD RF envelope waveform at DVD disc amplifier gain gradually decreases.
disc TK-47 board CN005(_P
TK-47 board CN005_)P
- 15 - - 16 -

Theinputsignalto IC006DIP_ andDIN_) is a signalprocessed
afterEQ block
mentioned
later.
"1: SingleLayerdisc *2: DualLayerdisc *3: Peakto PeakDifferential

(3) EQblock
TheEQblockis a programmable equalizerfilter differentiatorblock.
TheDVD formatis premised on theEQ andrequireshighfrequencysignalstobe
boosted. Thisblockequalizes
RFsignaltogetoptimumRFsignalbycombiningLPF
and-EQ(boost),asshownin Figure2-4. LPFisdefinedas-3dBbandwidthwithout
boost.If theamountofboostis settoacertainvalue,thegainatcut-offfrequencyis
asfollows:
Gain(atcut-offfrequency)
= -3dB+ Boostamount[dB]
Also,LPFis usedasaprefilterfortheA/D converterprovidedin theinputstageof
RFblockof IC in thepoststage(MB78boardIC770).
10
wl
v ---e.--- LPF+EQ
_z
--D-- LPF
-5
-10
-15
t
0 1 2 3 4 5 6 7 8 9 10
FREQUENCY (MHz)
Figure 2-4. Frequency characteristics (EQ+LPF)
These cut-off frequency and boost amount of LPF are operated by the command
register set via serial interface.
The RF signal processed in this block is output from IC006 FNP_ and FNN(_). This
signal is entered to IC006 DIP_ and DIN(_) and rectified in full wave, then compared
in the AGC block. The RF signal output from IC006 SIG(_ is then transmitted to the
RF signal processing block IC806 in the post stage.
- 17 -

(4) Serial interface
Various values of IC006 are set to internal serial port register via serial interface.
Actually, they are set by three signals from the L G/A IC804. Signals are SDEN_,
SDATA_), and SCLK(_, and its timing chart is shown in Figure 2-5.
SDEN
SDATA
SCLK
( ADDRESS, 8-BIT _ DATA, 8-BIT )
LJ
SDEN
TCLK TTRN
SCLK
SDATA /
ADDR0
(READ)/
ADDR0
SDATA
(WRITE) \
Figure 2-5. Timing chart
- 18-
2-2. CD RF Front End
rTK-47 board
CXA,?.5550
OPTICAL
BLOCK CDRF TK-47 board
_1 cNO01
<
-_ To MB-78 board
IC.806 ARP
Figure 2-6. TK-47 board RF/CD
The RF signal output from the CD OP is input to IC005 (_) and (_), and transmitted to IC806ARP
of the MB-78 board via the amplifier, equalizer.
about 1-1.4Vp-p about 1-1.4Vp-p
range 500mY 500ns range 500mY 20ns
Fi0ure 2-7. Figure 2-8.

RF (eye pattern) waveform at CD disc RF envelope waveform at CD disc
I
TK-47 board CN005(_P TK-47 board CN005(_P
- 19 -

2-3. RF Signal Processing Block
The block is composed of the IC806 ARP (CXD 1865R) and IC810 4Mbit DRAM (I.tPD424260)
of the MB-78 board.
In the case of the DVD, the ARP is input with the AGC and RF equalize-processed DVD-RF
signal at the IC006 analog front end (SSI33P3720) of the TK-47 board. In the case of the CD-
DA and video-CD, it is input with the CD-RF signal from IC005 of the TK-47 board.
In the ARP, first RF signal processing such as asymmetry correction, adaptive equalization, and
sync clock extraction by the RF-PLL are carried out so that the signal becomes binary data
synchronized with the PLL clock. This data is EFMPlus demodulated (DVD)/EFM demodulated
(CD-DA and video-CD) in the demodulator, subjected to frame/sector sync detection, address
detection, and protection, and sent to the buffer memory controller.
In the case of the DVD and video-CD, the ARP is linked to the ECC core, built-in and external
memories, and output controller to carry out error correction, descrambling, EDC detection,
navigation information detection (DVD only), and output data flow control, etc. The data output
in this way is then sent to the decrypt block in the next stage.
J
This is the same for the CDDA. The ARP is linked to the built-in and external memories, and
CDDA signal processing block to carry out error correction, output datll flow control, etc. The
signal is then muted and corrected by the CDDA signal processing block, and then sent to the
IC203AV decoder (L64020).
For all of these disks, RF jitter is calculated by the RF signal processing block, and this
information is used for adaptive control of the servo DSP via the CPU.
ARP DECRYPT
OCRSD0 - 7
DVD-RF
From TK-47 boa_ (
IC806
CXD1865R
IC811
CXD1904G
' To AV decoder IC203
TOS
ERROR
AVALID
DCK
AREQ
CD-RF.(
From TK-47 boa_
_O LRCK (. To AV decoder IC203
CD DATA) _J, _-.-, ,_J, _-._
MDO-15 MAO-8
IC810
4M DRAM
pPD424260
Figure 2-9. MB-78 board RF processor, decrypt
- 20 -
2-4. Decrypt Block
Data sent from ARP is subject to decoding of the digital copy protection for preventing illegal
copy determined by DVD standards at ICS11 (CXD1904), and then sent to the AV decoder in
the post stage.
2-5. AV Decoder Block

Comp0sed of two 16M SDRAMs (IC201,202MB 81117622) and AVDEC (IC203, L64020), it
is used to decode DVD/VCD data (MPEG stream) from the decrypt.
After decoding, the video signal is letter box converted, and output together with the subpicture
and OSD signals.
The audio signal is decoded for the two channels AC3/MPEG/LPCM and output. Separately
AC3/MPEG compressed data is output as IEC958.
The CD data from ARP is bypassed inside and output from the audio output.
2-6. OSD Block

IC207 of the MB-78 board (MB90096) outputs the player menu, and adds it to the video signal
inside the AV decoder IC203 (L64020).
- 21 -

IC203 AV Decoder
(L64020)
YC0-7
DCRSD 0-7 -- To IC251 DNR
TOS AU-197
ERROR 0353
AVALID
DCK
AREQ
iC351 _ C°axial °utptzt ] 0joltal
IC207
GPIF32T I output
MB90096
From IC807 ('CG--'_'O

SGA , _SO
CXD08747 ' L SCLKO OSO IC102 OIR (To LC8905t)
AVDATA
AV LRCK
AVBCK
t To IC101 MGA (2cll signal)
FromIC806ARP --
CDLRCK
CDBCK
CDDATA
SPDIF
AVIO0-15
IC201
IC202
16M SOP,AM
Figure 2-10. AV Decoder, OSD
- 22 -

2-7. DNR, Video Encoder Blocks
The video data from the AV decoder is sent to IC251, DNR (CXD1854), subjected to video
noise reduction, and sent to the IC252 video encoder CXD1914 in the post stage. The video
data is converted to NTSC/PAL video signal (Color difference signal/S-Y, S-C/composite) here.
IC252
IC2510NR VIDEO ENCORDER
CXD1854 CXD 1914
From vr C0-7 R-Y

IC203
AV Decoder
'"
1
Y
For color difference output
B-Y J
YO-7 VIDEOC
VIDEO Y ForS terminal
VIDEOV Compositevideo
Figure 2-11. DNR video encoder
Signals are output externally after passing through the 75 _ driver.
- 23 -

2-8. Clock Generator Block
The IC209 CXD8696PLL IC generates 27 MHz, and using this as the master clock, generates
the system clock for audio decoding.
System Clock 384fs 768fs

CD/VCD 16.9344 MHz 33.8688 MHz
DVD 18.4320 MHz 36.8640 MHz
IC209 IC206 SN74ABT12608

PLL
CXD8696 BUFF
27.0000MHz
)
)
1(;205 SN74ABT12608
BUFF
) 7_Sfs
X210 384fs
27MHz
=
33.8688MHz
Figure 2-12. Clock generator
- 24 -
2-9. AC-3 Decoder Block
M G/A (IC101)
CXO 87460
FromL_A (tC_4) 8s'r

6STC
$062C
SCKG2
From_ 11c8o5)
; SOG2
OR LRCK ( AC-3 AC3__K

DECODER AC;_LRCK DO_LRCK
(IC_04) /
M886342 2
DD_BCK l
AC3_DATA F
AC3_OATA R
AC3.OATA C
I /
3 DD_OATA F 1
AV_ II
256KS_
N341256
Figure 2-13. AC-3 Decoder
The SPDIF_AC3 (Dolby Digital Bit-Stream) audio data output from AVDEC is input to the
AC-3 decoder (IC104) via DIR (IC102) and M G/A (IC101). In the AC-3 decoder (IC104), the
data is processed for three lines, and sent to the AU- 197 board DF/GAC via the M G/A (IC 101).
- 25 -

2-10. Audio L and R 2ch Signal Block
The audio signal data for 2 channels of the MB-78 board AV decoder IC203 (L64020) is passed
through IC101MGA, passed through the digital filter in the AU197 board IC215 (CXD8750),
converted to analog signal in the DAC, and passed through the LDF to become the line out
signal.
IC101 IC215
CXD8746 CXD8750
IC206
IC207
NJM4580
From
IC203 Digitalfilter
MGA KR DATA DAC Secondary LPF Line oul
AV Decoder AVDATA
AVLRCK KR LRCK
AVBCK KR BCK
MB-78 board AU-197"" board
Figure 2-14. 2ch signal block
The line out signal line is also branched out to IC214 to become the _eadphones amplifier
output.
IC214 IC001
NJM4580 NJM4556
R JO01
L
R
-E> .,. -E>
Y _r
AU197 board HP-96 board
Figure 2-15. Headphones amplifier
- 26 -

2-11. Audio 5.1ch Signal Block
The AC3 decoded signal DD-DATA C/R/F output from the MB-78 board IC101 MGA
(CXD8746) is input together with DD BCK and DD LRCK to IC203, IC204, and IC205
(CXD8750) of the AU-197 board, passed through the digital filter, and converted to the analog
signal in DAC.
The front L and R signals are then passed through IC203 of the AU- 197 board, gain-controlled
at IC353 (BU4053B), and noise-eliminated at the secondary LPF IC208, IC211 (NJM4580) to
become the external output of the front L and R.
The sound Land R, and center sub woofer signals are passed through IC204 and IC205 without
being gain-controlled, and noise-eliminated in the secondary LPF IC209, IC212, IC210 and
IC213 (NJM4580) to become the external output.
IC203 IC353 5.1ch OUT

CXD8750 BU4053B IC208, 211
---L
From DD LRCK = FOR L,R _R

MB-78board
IC101MGA DD bATAF _ DF/DAC
DD BCK
GAIN6
IC204
CXD8750
IC209,212
DD LRCK , _ FOR SL, SR

DF/DAC SL
, - SR
DO DATAR
DO BCK
IC205
CXD8750
IC210,213
DD LRCK CENTER I
___
DD DATAC
DF/DAC
SUB WOOFER
_CENTER I:
' SUBWOOFER
I I
DO 8CK I
_J
Figure 2-16. 5.1ch Signal Block
- 27 -

2-12. DVP-S715 AU-205 Board Block Diagram
1/2 _CL_I7 1/2 IC207

L P, F BUFFER
J202
7_
OAC BCK
CLOCK BUFFER
DA,C LRCK
(_) L OUT
CN203 OAC AOATA
0203 0211
FILTER MUTE
SWITCH SW
i (_ R OUT
Q204 0212 IC208 HP, L ;" _ ,CN205
_E01 1/3x3 IC204 DA CONVERTER _i FILTER MUTE

SWITCH SW
1/2 1C206 t/2 IC206
L,P,F BUFFER
kATe
PMUTE I ,
I IF CR202
VIDEO V
i
MUTE LOGIC
0205, 210
1 VIDEO BUFFER
VIOEO_YAuL
CN201 SOG3
AUDIOMUTE
IC_85 Q2_ *W REG
I V_OEO V, J20_
D2LT _) VIDEO
SCKG3
VIDEO Y
POWERCONTROL _ ÷5V
VIDEOIC
[ © S-V,D_O
_ AU*SV
---_ --W _EV REG
_1 .-_ REO
vs Q214
OCCONTROL
REG DRIVE
BUFFER BLB:FER
J_F
©c_
['1--_ AU*E2V _tO
i '
TO_-415 p. FAIL
CRY04 _ _1_
Figure 2-17

2-13. System Control Block
The system controller is composed mainly of the IC805 (HD6437034) SH microcomputer, and
IC807 (CXD8728) large gate array, 1C802 (HM62812) 1M SRAM, ICS803 8M FLASH memory,
and IC807 (CXD8747) small gate array, etc. It serves to control the overall servo system.
2-14. Interface Control Block

The 'interface controller is composed of the IC604 (MBg0T678) I/F microcomputer, IC608
(_PD432568) 256K SRAM, IC601 (SN74HC373), and ICS603 external ROM. It sends various
commands to the SH microcomputer based on the switch information from the FL board and
FR board, receives the current information from the SH microcomputer, and displays
on the FL tube display.
- 29 -

1(3803 Vcc=5v IC802 Vcc=5v IC 506 Vcc=5V IC 806 Vcc=3.3V IC 811 Vcc=5V IC 203 Vcc=3.3V
ROM(Flash)SMbit RAM (1Mbit) Servo DSP ARP DECRIPT AV_DEC
CXD8730 CXD1865
HM628128 CXD1904 L64020
. _k ,LL A
t d, Ai, d
r_ 00 ,,'- ,'-" I--
C3 z _--I._. _ _ _z_
Vcc=5V BusBuffer _cE o,1o "__
_<_1_ (SGA) O'3 (:3 _._ ,,=:
00
SH SA[0:19]
Address
DATA 4 SD[0:15]
dir&G Control I
10805 ;
P
HD 6437034 RD i
System Control
Drive Control
WR
CSO
CSl
T j
I
d
CS6
WAIT
IRQO
IRQ6
IRQ7
IRQ3
IRQ2 I
SOG1] 10604 10207 IC101
TxDO
TxD1 MB90T678
"To Expansion I/FCON OSD FL_ConI
SCK1 MB90096A 11 pPD16311
JPSEL I I/O XI_FBSY
SlO SlSCLKCGGS SISCLKFLCS
1:3 r'_ (Handshake) Ch_n
X X
r,-- tY-
SlO SO
_1 _1 _/_1 Ch m SCLK
t
•--Lo L JI G,Oir Serial -
IFSO= Sl_m FLCS
{9O T FLCS
Address Bus
IWRn Gpl " IFSI_ SO_m
____ INT&WAIT IRDn 10807
co Control Decode Controll_ CN802 0XD8747
SDSPWRn J
SDSPRDn J
AC3 Dec VEnc > Serial Diagnostic
SIC1 Device I ARPCSn Gp2
SIC2 _RxDs DCRCSn
J
MB8-6342
I C_D_9_4Q
/ I Connector
MPX ChipSelectL AVCSn J DBSO..1 Rxl3
;°J
4 ARPINT
INT Control -_ DCRINT DBSI"t Tx[)
Out put
4 ARPWIn 101
Expansion 4 DCRWrn
I/O 10804 WAlT C:nxt_:ll, AVWTn
Servo Block 4 Group2RxOs Expansion
LGA 4 I/O _ DIAGN I
Gro.up.2
I CXD8728 Chip_elect r_ IFSO
T x DOSel -_ DBSO
IFSI
n
AC3
Block i_ R x DOSel • DBSI
LGA
II 1
_CKG3
J SOG3
Serial [-
SCKG4
Gp3,4 / SOG4
ARP Block i_ CONTROLL SCKG4n(DCLK)
J Iv
SOG2PS
=.-
_" 13 SCKG2PS
o _- _ AVCK
SerialDevise i_
fO
Q.
=_J3
,coo6_ _ 03
I/0 T
10102 SSl o_ IC251 (n IC215
EEPROM
Hsync (from 0XD1914) T IC203~205

II DAC
DIR
LC89051V
(SS133P3720)
I_:
DNR
,,z, CXD1854Q
BA9020F
DAC
CXD8750
•
AdvancedHSYNC
(for OSD, DNR,AVDEC)
oxo8o_,2 (::3 t-'t
LU
1.1.1
) k
y. Y
Serial Gp4 Serial Gp3
Fig. 2-18. System Controller Peripheral Device Control Block Diagram
- 31 - -32-

3. SERVO BLOCK 3-2. Servo Operation at DVD Play
3-2-1. Optical Pickup Control

3-1. General Description of Servo Circuits (1) DVD focus servo
The focus error signal output from the optical pickup for DVD (hereinafter referred to
as optical pickup) is entered to the TK-47 board IC006: SSI33P3720A A to D ((_ to
(_)P).
Dedicated optical pickups for DVD and for CD and video CD are provided. The focus and
tracking servo gains are automatically adjusted for every disc loading so that the gains are
The balance amount and offset amount of the focus error signal is set by IC805 (CPU)
constant for every disc to be played.
via IC804 of the MB-78 board using the internal register of IC006.
The focus error signal is generated at TK-47 board IC006, amplified, and output from
3-1-2. Sled Control the FE terminal (_p).
Two pickups for DVD and CD/video CD are placed on the same sled, and the position is The IC006 FOCUS error (DVD FE) signal is input to the MB-78 board via the flexible
controlled with one sled motor. The sled motor is attached with a speed detector utilizing flat cable.
the Hall element, and a sled speed fluctuation due to mechanical load variations is minimized The error signal is switched according to whether the disc type is DVD or CD by the
by applying the speed servo control (feedback control). switch IC452, its signal level is adjusted by IC503 (OP amplifier (_), (_), (_p), and it is
The sled motor used is a DC motor with a brush. input to the servo DSP IC506 (CXD8730R) _p.
The servo system circuit is used for both DVD and CD.
3-1-3. Spindle Control

One 3-phase brushless motor controls all disc rotations. The rotation detection pulses (FG:
Frequency Generator) utilizing the Hall element are used for control.
3-1-4. Tilt Control
The optical pickup is controlled so that the optical axis is perpendicular to the disc; when
DVD is played, it is controlled so that the time axis variation (jitter) of RF signal becomes
minimum.
At the start of DVD play (before RF signal is output), optical sensor detects the tilt angle of
disc and the optical pickup is controlled so that the optical axis is perpendicular to the disc.
The servo system circuit is used for both DVD and CD. At DVD, it always performs tilt
operation, but at CD, it operates only during start-up and stops at the tilt position during
playback.
3-1-5. Disc Loading and Chucking

One DC motor drives the tray in-out motions, and chucking of disc.
3-1-6. Disc Judgment

The presence of a disk is judged from the spindle motor spinning start-up time.
Also, the disc size (12cm or 8cm) is judged from the spindle motor speed-up time and disc
data.
- 33 - - 34 -

MB-78 board
i
r
Optical Block
]
TK-47 board
IC006 SS133P3720A
I
I
i
' tC452 iC503 (1/4,3/4) IC506 IC363
ZIF CNO01
I MC14053 NJM3403 CXD8730R BA5981
CNO05 CN452 r I SERVODSP FCSDRtVE
FE
I
Ln i _-- _
_sso7 ]
,__
'._---_--_
DVD FCS--_ To DVD FOCUS coil
DVDFCS+_
i
I
i s_,,_,<l ,,o,.,cBo,,
' 'I
I ' I__'__ l
IC501 1/2
Figure 3-1. DVD focus servo, drive

The IC506 Servo DSP: CXD8730 on MB-78 board provides the following control in
the focus servo system.
(a) Focus search

The optical pickup lens is moved toward a disc to turn on the focus servo.
The focus servo loop is turned on when the PI (Pull IN) signal (used for FOK:
Focus OK) exceeds the specification (Vc +0.25V) and the FE signal zero-crossing
is detected.
(b) Focus gain adjustment

The gain of digital filter in the IC506 is automatically adjusted so that the focus
servo loop gain becomes optimum.
Consequently, the optimum gain for each disc to be played can be attained, besides
correction of gain variations in focus actuator (coil) and optical pickup sensor
(photodiode for focusing).
(c) Focus bias adjustment

The focus bias is added to the focus servo filter so as to mi_mize the jitter.
Consequently, a variation of optical pickup and disc can be automatically corrected.
(d) Focus jump

Operation carried out when playing back the DVD dual layer disc to perform
focusing jump between layer 0 (PU side layer) and layer 1 (far end layer).
First the servo loop is turned off, the kick voltage is supplied to the focus actuator,
and the focus is jumped to the targeted layer. As the focus approaches the desired
layer, the FE signal appears. The voltage of this signal is monitored, the deceleration
pulse is generated, and the focus servo is turned ON again after focusing.
These operations from the start to end of jumping are all performed inside the
DSP.
- 36 -

,'topped ;topped
CNI_OOmV: : _ i 2ms/div CHI=5_mV: _ + : _$/_v
I_. 10:1 _ (2ms_'_v)

: ! I' i : : : f i _2QOk875
...... ] ....... ] ...... ] ......... i ........ ??......... ] ......... !......... i ........ [ ........
: T i: ;i '* i_}i
'!i .... ............il_
...............
..............
ii..............
...........................
ii...................
!........
;.................................. ......................................................... :......... ! .........
i
: ...................
! : i :
: !
i
Figure 3-2. Example of S-shape Figure 3-3. Example of S-shape

waveform for the DVD disc waveform for the DVD disc
(single layer) MB-78 board (dual layer) MB-78 board

CN303 (_P CN303 (_)P
FOK
................ .ii, DFCTS
PI M_IRR............
[
OSP CORE I BUSY

Tzc] I FON
FE ___ _ I,ou,
FOUT
PWM l _ SLOFS
f
TiOFS
BUSY
Figure 3-4. Focus jump waveform

Figure 3-5. Example of S-shape
waveform for MB-78 board
CXD8730R (Layer) MB-78

board CN303 (_)P
- 3? -
The FE signal input to IC506 (DSP CXD8730R) is low frequency boosted and gain-adjusted at
the internal digital filter, and then output from the DSP as the focus drive signal (F OUT _)P)
by the D/A converter inside the DSP.
The FOUT signal is input to the focus actuator (coil) drive IC (IC363:BA5981).
In IC363, voltage amplification, voltage conversion, and
current amplification are carried out to drive the focus actuator (coil) using the output signals
of IC363 (DVD FCS+, DVD FCS-).
(2) DVD tracking servo
TK-47board MB-78 board

ICG06 IC011 i Ic452 IC503(2/4) IC506 IC363
CNO01 8S133P3720 MC14053 I MC14053 NJM3403 CXD8730 BA5981
DPD TOUT D_I d
To tr_kino actuator
' . ...... F_'*pLc_..__

.. _ I ct;iovo
', OFFwf'mnI_ RFP ', _ (OVO: H_
!(.c__ooL._
!_ .._,y.vp.-.pl I _co:_/
Figure. 3-6 DVD Tracking servo, drive
The tracking error signal output from optical pickup is entered to the IC006:SSI33P3720
A2 to D2 (O to (_)P) on the TK-47 board. The tracking error signal is detected in the
DPD (Differential Phase Detection) method.
The amplification degree and offset value of tracking error signal are set by internal
register in the IC006.
The tracking error signal TE (IC006, _P) is output from IC006, then it is entered to the
switch IC (IC011: MC 14053).
The switch IC shuts off tracking error signal when DVD RF signal (RFP) is below
about 200mVp-p (AC component).

Tracking Error (TE) signal (DPD signal: Differential Phase Detection signal) generated
in the IC006 is entered to the MB-78 board through a flexible fiat cable.
TE (Tracking Error) signal passes through the switch IC, IC452 (MC14053 that switches
CD tracking error andDVD tracking error (DPD) signal), and it"is amplified at IC503
(NJM3403), then entered to the TE (_)P) of IC506 (DSP: CXD8730R).
!
- 38 -

The Servo DSP IC provides the following control in the tracking servo system.
(a) Tracking gain adjustment

The gain of intemal digital filter of IC is automatically adjusted so that the tracking
servo loop gain becomes optimum.
Consequently, the optimum gain for each disc to be played can be attained, besides
correction of gain variations in tracking actuator (coil) and optical pickup sensor
(photodiode for tracking and focusing).
(b) Tracking jump control

At one track jump or N track jump (jumping many tracks) in asearching, generation
of tracking pulses, control of tracking brake, and measurement of tracking jumps
are executed.
The TE (Tracking Error) signal input to IC506 (Servo DSP CXD8730R) is low frequency
boosted, high frequency phase compensated, and gain adjusted by the internal digital
filter, and output from DSP by the DSP internal D/A converter as the tracking drive
signal (T OUT _P).
The T OUT signal is input to the IC (IC363:BA5981) for
driving the tracking actuator (coil).
In IC363, voltage amplification, voltage conversion, and current amplification are carded
out to BTL drive the tracking actuator (coil) using the output signals of IC363 (DVD
TRK + _)P, DVD TRK - (_P).
The tracking zero-cross timing is generated by IC501 (1JPC393) and IC508 (NJM3404).
- 39 -

_.t,opped
CHI=500mV Stopped
DC 10:1 CHlt506mV: 200us/dfv
: : (Sm$t'div)
• i (200_/div)
2 NORM:20_kS/S
MORM:.SMS/$
_" 5m:S_/div r
t
Figure 3-7. Trv (TE at tracking servo Figure 3-8. TE (enlarged Try)
OFF) waveform at DVD waveform at DVD disc,
disc, IC506(_)P IC506(_)P
Figure 3-9. 1TJ (track jump) waveform

at DVD disc, IC506_)P
- 40 -

3-2-2. Sled control
IC302
LBF HPF LA6527N
,_ledDrive
SLOFS ,(
SOUT ,(
' SLDMT _" To sled motor
=_ Tracking block _, SDCNT ,( _J
HYCNT .(
IC506 FromFG-43 board,

CXD8730R IC501, IC502
I
I Feedback speed I
II control by Hall element j
Figure 3-10. DVD Sled control
(1) Sled control during playing

During disc playing, namely, when the focus servo and tracking servo are turned on,
the sled servo controls the sled motor so that an objective lens of optical pickup positions
always in the center of movable range of tracking actuator.
The error signal of the sled servo is obtained by amplifying the low frequency components
of TE by the digital filter in the DSE Consequently, it cannot be observed externally.
Th[ error signal generated internally is output from SOUT ((_)P)) via the digital low
pass filter, and input to the sled driver IC302 (_P).
Thh sled driver carries out sled speed control constantly, and adds the SOUT voltage to
the control loop.
The Servo DSP IC506 CXD8730R carries out the following controls in the sled servo
block.
(a) Sled error signal generation

Carries out tracking error TE processing to generate the sled error signal.
(b) Sled error amplification

Amplifies the sled error signal by the LPF (Low Pass Filter) composed of the
digital filter and amplifier.
(c) Sled error ON/OFF
Tums ON the sled servo during normal playback, and turns it OFF when the
tracking servo is OFF when playback starts, during search, etc.
- 41 -

The sled error signal is passed through the digital filter in IC506 (DSP), and output
from the DSP as the SOUT ((_)P) signal from the D/A converter.
The SOUT signal is input to DVI ((_P) of the sled drive IC (IC302:LA6527N).
The sled drive IC incorporates a speed (motor rotation speed) feed back control using
the Hall element.
There are two speed detection Hall elements (HA, HB). The detection output is obtained
from the sled motor board (FG-43 board) as the differential output of (HA+, HA-)
(HB+, HB-).
The sled drive IC detects the inclination of the Hall element output waveform during
sled motor rotation (differential value near the zero cross) to form the speed feedback.
In the sled drive IC, after the sled error signal is converted to the sled motor rotation
speed signal, the voltage and current are amplified, and the sled (d.c.) motor is driven
by the output signal (SLDMT+ (_)E SLDMT- (_)P).
(2) Sled forced operation control
When driving the sled motor in operations other than playback, _n other words during
direct search, the sled speed target signal is input from IC506 (DSP:CXD8730R) _)P
SDCNT to the sled motor driver IC302 (LA6527N) (_)P. The data to IC506 (Servo
DSP) is sent from the IC805 SH microcomputer.
The IC506 SLOFS (_P is the offset adjustment signal of IC302. It is used to adjust the
voltage supplied between the motor terminals to 0 when the sled motor is stopping.
- 42 -
3-2-3. Spindle Control
This section describes the flow of control signals in the spindle servo during DVD playback.
The CLV control signal is generated from the RF signal obtained from the optical pickup in
' IC806 (CXD1865) to generate the two servo error signals-disc CLV speed error (MDSO (_
P) and CLV phase error (MDPO (_)P).
These two error signals is added by IC301 (NJM3404) and output from OP.
The spindle error output signal SPERR of the OP of IC301 is input to the spindle drive IC
(IC303:LB 1896).
The IC303 is a 3-phase brushless motor drive IC, and it contains a spindle error signal
amplifying circuit, gain switching circuit, and motor forced acceleration and deceleration
control circuit.
Gain switching is done with the SPGC1 signal ((_)P).
Disc size (CD/DVD) SPGC1 level

12 cm H
8 cm L
At the start and stop of disc playing, the forced acceleration and deceleration control is
executed.
Control mode Input signals

SPCTRL0 ((_)P) SPCTRL 1 ((_)P)
Acceleration H L
Deceleration H H
No control L H
MB-78 board t
le806 IC303
CXD1865 IC301 NJM3404 LB1896
ARP
SPEER_ _1 TO spindle
• l motor
MDPO , I-'_"___ H' 12cm _:l _I

' I I,-
,L:Scm
-- -- --
, _1
'-ol
;_1
U_l
Gain switching
From
IC804
LGACXD8728
Figure 3-11. DVD spindle control
- 43 -

3-2-4. Tilt Control
TK-47board MB-78 board

IC006SSI33P3720
0452
2SD2114
1(;361
BA5912
1
i
| | CNO06
cN452
TIERR
T_
l TIMT÷
DRIVER
TILT t
To_ll_m
I TIMT-
I
TIB_ TfE IC8051,10_7034
1I
1C804_8
j L..__ TIOFS
OSP
$H/LGA
Offsetvoffaoe
tC806 CDXE730R
ARP t ,litter
I
J
Figure. 3-12. Tilt control
(1) Tilt servo by tilt sensor

Tilt control using the tilt sensor of the optical pickup is performed at the start of DVD
playback and CD playback.
The tilt sensor output signal of the optical pickup (TK-47 board CN001, (_)P SKEW IN
(TIA), _P SKEW OUT (TIB)) is input to tilt amplifier (_), _)P) of IC006 (SS 13P3720).
After integration and amplification, it is output as the tilt error signal (TIERR _)P).
The servo on/off of the tilt error signal (TIERR) is controlled by the transistor SWQ452
of the MB-78 board.
When the tilt error signal (TIE) level drops within the specified value VCI (+2.5V) +50
mV, the window comparator output TILTIN ((_)P or (_)P) signal of IC455 (comparator
pPC393) becomes the H level, and switch Q452 is controlled to switch to the _[])P
voltage level VC (+2.5V) of IC361.

As a result, the tilt servo goes OFF to form a dead band.
The TIERR signal during ON is input to the tilt drive IC361 (BA5912AFP).
In IC361, voltage amplification, voltage conversion, and current amplification is carried
out, and the tilt motor (DC brush motor) is BTL-driven by the output signal (TIMT+(_)P,
TIMT- (_)P) of IC361.
- 44 -
(2) Tilt offset adjustment minimizing jitter
To optimize RF during DVD playback (excluding search), the jitter (JITTER:time:axis
fluctuation of the RF signal) is measured, offset is added to the tilt servo loop, and the
jitter is minimized.
As jitter is adjusted at shipment, normally this adjustment is not required during playback.
However if the jitter deviates with time, the adjustment value may not be optimum
, according to the disc. In such cases, the jitter is measured prior to playback, and if it is
deviated from the specified value, adjustments are started automatically.
i.
The jitter value is measured by IC806 (CXD1865R) and the measured data is sent to
the system controller IC805 (HD6437034) to determine the offset amount. The offset is
voltage-generated by the PWM output of IC506 (DSP), and input to SSI33P3720 (_P
as the offset voltage (TIOFS).
By performing the above three types of IC control, the jitter is adjusted to optimum.
- 45 -

3-3. Servo Operation at CD and Video CD Playing
(1) CD focus servo
!
CH 1154]OmV: ! lOtrnl/dlv
...................i.............................:.............................::.........i........
...................
ii.............................
t.............................
!.........
!.........
I
................... {............................. ! ............................. : ......... _.........
1
:'i .... T ,, , • . •
!
Figure 3-13. S waveform at CD disc (focus error), IC506_)P
The RF signal (PDI, PD2) output from the CD optical pickup is converted to the focus
error signal (CDFE, (_)P) in IC005 (CD RF amplifier CXA2555Q) of the TK-47 board.
The CD focus error signal (CDFE) is passed through the flexible flat cable and input to
the switch IC452 (MC14053) of the MB-78 board. During CD playback, it is passed
through the switch IC452, BuFF IC503, and input to _)P FE of IC506 (DSP:CXD8730R).
The focus error signal is gain-adjusted, focus bias adjusted as done during DVD playback
in the DSP.
The focus drive signal (FOUT, _P) output from the DSP IC is input to the focus drive
IC (IC363 BA5981FP) as done during DVD playback.
IC363 is a 4ch driver IC, but performs coil driving of each pickup by switching the
level (H/L) of the MUTE terminal ((_), _P) during CD and DVD playback.
Play mode MUTE signal

_)P _P
DVD "H .... L"
CD, Video CD "L .... H"
The IC363 amplifies voltage, transforms voltage, and amplifies current, then BLT drives
the focus coil of CD pickup with its output signals (CD FCS+, CD FCS-).
- 46 -

OpticalBlock TK-47 board MB-78 board
I IC452 IC363 1
i
IC005 CXA2555Q MC14053 BA5981
D
|
ZIF CNO01
CNO05 CN452
C_ FCS* 1
DRIVE To CD focus coil
IC503 (BUFF)
_cs-j
i LI
IC506 (DSP)
route is the sameas
the DVDfocus servo
I
I
| I
I
I
J I
I_
L_.
Figure. 3-14. CD focus servo, drive

(2) CD tracking servo
TK-47 board MB-78 board

IC452 IC503 IC506 le_3
s MC14053 NJM3403 CXD8730 BA5981
IC005
CXA25550
ToCO_up
From tracking
coil
optical
c[
block
Figure 3-15. CD tracking servo
i CH2=lV i i 2muild_
. OC I_I - i (2Wu*/d_]
! :: i i _/,
................... i ......... i ................... t ...... _! ......... ! ................... !.........
,.j
i +.
_(zl : z.1#_
'_i
.........
i.........
i............................................................
i.........
.........:........._..................._.........•.......................................
;........
: ?
Figure 3-16. Try (TE at tracking servo OFF) Figure 3-17. TE (enlarged Try) waveform
waveform at CD disc, at CD disc, IC506(_)P
IC5061_)P
cmn,,_mv: ! Zoo_,/a_v
: i NO_M:SM_Is
........ ÷....... ÷....... _........ _....... _," _.
....... ._....... .;........ F........
o',',i'.o'_ i_,i/_ i i i i
................................................. ÷ ................................................
.............................i........._:
........._.................................................
• . : , :: !
Figure 3-18. 1TJ (track jump) waveform at

CD disc, IC506(_)P
- 48 -

The CDE and CDF signals output from the CD optical pickup are converted to the CD
tracking error signal (CDTE (_)P) at IC005 of (CXA2555Q) the TK-47 board. -
The CDTE signal is input to the switch IC (IC452, MC1405'3) of the MB-78 board.
During CD playback, it is passed through the switch IC (IC452), amplified at IC503,
and input to _)P TE of IC506 (DSP CXD8730R).
Like DVD playback, the tracking error signal is gain-adjusted, tracking bias-adjusted,
and tracking auto level-adjusted in the DSP.
The DSP tracking drive signal (T OUT (_)P) is voltage-amplified, voltage-converted,
and .current-amplified by the IC (IC363 BA5981) for tracking driving, and used to
drive the CD pickup tracking coil.
Track jump control during CD search is carried out by IC506 (DSP CXD8730R) as
done during DVD search.
As a result, when performing 1 track jump or N track jump (many track jumps), tracking
pulses are generated, the tracking zero cross timing is detected, tracking brake is
controlled, and the number of track jumps is measured.
* Tracking auto level adjustment.

This function operates only during CD and V-CD playback.When the TE level (traverse
waveform) is small due to the inconsistency of the disc, this level adjustment is
performed to eliminate the inconsistencies. Consequently, like gain adjustment, the
adjustment is performed each time the disc is replaced (tray is opened), to set the
traverse level to 2.0 Vp-p.
After setting the disc and turning ON the focus servo, the peak-to-peak value of the TE
signal (this TE signal is called the traverse signal) is measured by the IC506
(DSP:CXD8730R).
The|measurement results are read by the IC805 (system control IC) to determine the
gain variable amount. The response (variable amount) is then returned again to IC506
f
(DSP:CXD8730R).
Upon receiving this, IC506 outputs control signal for the tracking auto level adjustment
from (_)P and (_P of the IC506 (DSP:CXD8730R). It is added by IC503 and converted
to the analog voltage (TEATT signal).
The TEATr signal is input to _)P of IC005 (CXA2555) of the
TK-47 board, and gain-controlled inside the IC. The variable width is about _+3.0 dB.
- 49 -

3-3-2. CD Sled Control
CD sled control is exactly the same as the DVD.

However settings in IC506 (DSP:CXD8730R) differ.
3-3-3. CD Spindle Control
As the RF signal is processed inside IC806 (CXD1865), the process from the ARP is the
same as the DVD.
3-3-4. Tilt Control
At CD playing, the tilt control is made using the tilt sensor of optical pickup in a period from
the start of play (start of spindle rotation) to the completion of TOC data reading.
The tilt control in this case is same as tilt servo control by tilt sensor during DVD playing.
The tilt servo is turned off after the completion of TOC data reading.
The tilt servo mode ON/OFF control is done with the tilt servo amplifier in the IC006
(SSI33P3720) on the TK-47 board. (Figure. 3-12)
3-4. Disc Loading and Chucking

!
MB-78board
TK-47board
LOADff_w_TU.TOfkqz
C_l, ! LOM1. •
IIC_)
C_t_2eO
T_Y _t
HO_3r_
S013_ , LOUT- •
t_
I (_lCXlt_
n
C_ CN00S
CKUCK
,,w
FL-88board
)C_01
Figure. 3-19 Loading block
- 50 -

Disc loading, unloading, and chucking operations are performed with one DC motor. Its
block diagram is dhown in Figure 3-19.
3-4-1. Motor Driver

The system controller IC (IC805) controls the open and close of the tray. It monitors the
sensors of the mechanism and
conti:ols the operations of the tray motor via the L G/A IC (IC804).
The tray open/close signal is output by 3-state PWM modulation from IC804.
H (5V) = Open
High Z = Stop
L (Gnd)= Close
The tray speed is controlled by increasing/decreasing the PWM duty ratio.
The TRAY FREE signal is used to control the Mute terminal of the driver directly, turn OFF
the motor drive, and free the operations.
During the stop state, the potential difference between the two terminals of the motor is
controlled to 0V, while during the Tray Free state, the motor is not controlled at all.
3-4-2. Tray Position Detection

Tray position detection is carded out by the chucking sensor PH001 and tray out sensor
S001 on the TK-47 board. These signals are input to the MB-78 board via the flexible flat
cable, and input to L G/A (IC804) CHUCK _)P, and TRAY _P.
The relation between tray position and sensor signals is as shown below:
Mode <TRAY OUT (CN005(_))> <CHUCKING (CN005(_))>

Tray out position H L
Tray opefating L L
Chucking position L H
!
-51 -

3-5. Differentiation of Disc Type
This series can determine three types of discs (CD/DVD-SL/DVD-DL) at one time
when performing focus-search.
3-5-1. CD/DVD Differentiation

The pit shape and track pitch are quite different between CD and DVD. Because of this
difference, TE is not generated even if a large laser spot for CD is shot at a high density
disk such as DVD. This feature is utilized to judge CD or DVD.
Specifically, even if DVD is played in the CD mode (the optical pickup operates at the
CD side), TE is not generated almost all.
On the other hand, by playing CDs in the CD mode, naturally, the 2Vp-p traverse
waveform (approx.) will be measured. This is used for the detection.
3-5-2. SL/DL Differentiation

SL/DL is differentiated by the PI level.
3-5 -3. Differentiation

1) The servo system mode is CD (MB-78 board: IC452 "(_)"P and "(_" are "L")
2) PI mode is DVD (MB-78 board: IC452 (_)P is "H")
3) Both lasers turn ON
4) The spindle turns ON

5) The sled is moved to the external circumference slow.
6) Both focus actuators are moved up and down.

7) The signal is measured.
IC506 DSP (CXD8730R)

• When the p-p value of the CD traverse waveform (24p) is measured, the PI level
of the DVD is measured at the same time.
• IC805 SH (system controller) reads the TE and PI levels measured bythe DSP to
differentiate between CD/DVD-SL/DVD-DL.
• CD/DVD differentiation: TE is generated as a clear traverse waveform,

CD/DVD differentiation: Judged as CD if TE is generated as a clear traverse
waveform.
SL/DL differentiation: The PI level becomes SL>DL.
CD __h_ I Approx. 2Vp-p • _ ' I Approx.

1V
SL
OVO ----.... - ,rox.0.5V
DL
Figure. 3-20. Traverse waveform Figure. 3-21. PI waveform
- 52 -

3-6. Block diagram (Servo)
t
J TK-47 J
,_ :k;AL _LOCK L MR-78 Servo Block
uv_) Rh ITS06
DVDPDIC 9 9_ icoo6 57 MUt,O
lO RFU 64 _F HOLO 4Z CXDI86!,R MDpo
14 14 A ........ 1 37 DVDP_ IA1. 2zM DSP

13 B 2 ssi33P372oA 39 OVDFE DVO FE ID_ <27OOMHz)
R C .... 3
18 OPD
_e D 4 38 PISW <s.i
7 _ Pa
S 5 VR 23 VC Tie
26 • TIERR
TZ¢
27 _08
DFCT
3 OVULO _ VC
41 ssso
4 OVDPO lr 43 COKG3
FE
MIRa i(:Oll
TIOF
FOCHG te
CR/OVO
MC14053 $LEO-
38
4t SLED*
42
HYRET IC363
29 PD2 4 COTE TEACCO DRWER
CX_SS5 CORFOC TEAGCI

t9 19 AL COLCON 8A5981FP
27 27 E tEAl1 OETS
20 2O CD.F F t_OFS
CRRF
23 _23 cp- LC ---- i cx/_2555 _16 VC I I CHUCK

TRAY _1op
26 (3 75v)
25 _CTS
FOCUS
TRACKING
COIL
C_(
C_008 C_3OZ
3O COFCR+
_U- CDFCS-
I_I OFCS+
RVO_CS*
D_,FCS- OVDFCS- OVDFCS-
TR._KtNG
COr_K+ CDTRK+
c¢_x,
CDTRK- COTRK- ' CO_K-
COIL i DVDTRK, RVDTRK÷ DVDmK_
OYOTRK- RVDTRK- D_TRK-
SPINDLE
BOARO S_
121
131
151 WIN2 WIN2 w IN2 W,IN2 1 IC303 OVOLDON

]RL WiN1 WlNt W I_1 WIN1 34 SPINDLEDRiVER CRLDON
17L VIN2 VlN2 VIN2 VIN2 33 TILT/H FON
I 81 Wm VINt ViN1 VINI 32 LB1896
I 9 I UIN2 CIN2 U IN2 UIN2 31 CXDB728Q
]tOL UIN1 UIN1 U IR1 UIN1 _0
J'L s_. SPVH, S_VH÷ U_H._ _NST NUT
It2L RPVH. SPVH- SPVH- SPVH- 28 9 SPCTLO
bUL uout UCOT U OUT -- UOUT 23 s S_CTL1 SPCTLI
WOUT 19 SFGC2 SCKG3 toCN4S2 _
114L vOut VCOT VOUT VOUT 22 seGcl SPGCl
bSL wOUT w OUT WOUT SDEN
SSSD 1 CN501
OPNtCLS 1 kICK
2 NFS
CNOO4 S12VOFF 3 HR
LDMT÷ LDMT+ LDMT* 4 UHD7
LDMT- LDMT- LDMT- 9 TILTDRIVER 13 TRAYFREE 5 SHD6
LOADINGDRIVER S12VOFF 6 SHD5
CN303
7 SHD4
I PI
1-43 CN0O3 ON3_I BASg_2 S SHD3
DGND g SHD2
TIMT. TIMT- TIMT- 5 2
TIMT, TIMT* TIMT_ TIM% 6 TI=E_R F0 SHD!
[_ TIMT_ ll SHDU
TI_ERR
CNU0_ t2 TMS
13 IRST
IC501 HA HA 14 TOI
IC502 HA_ ............. HA* 34 SLEDORIVER lS D*_V
Ti_7- SLVH+ SLVH+ 23 16 GNU
HB* He, _ 30 17 TOO
HB- HB- Ha 29
I_ GNp
__ SLVH SLVH- SL_ SLVH- Lk6527 19 TCK
SLOMT- _DMT HA- 311C302
SLDMT- A* 2O GND
SLOMT+ SLDMT* ULDMT+
SLDMT- 2_ EMU0
22 _MUl
- 53 - - 54 -

4. IC PIN DESCRIPTION
4-1. ARP
CXD1865R (IC806 oil MB-78 board)
4-1-1. Block Diagram
13T-139, 141-143,
145-147, 149:MAO-MA9
113:WFCK 150:XMWR
114:SC0 R 151:XCAS
116:EXCK 153:XRAS
50:DEC1 117:SBSO 154:XOE
51:NORF 119:SOS0 156-159, 161-164,
52:JITPWM 55:FWON 120:SOCK 166-169, 171-174:MDOO-MD15
T 90:SDCK
91:XSHD
IO:RI:-IN1
12:RFIN2 Out,,ut
"-- 92:XSRO
93:XSAK
94:SDEF
.... I ,protec,.on.''
% ontro'
96-99, 101-104:SDO-SDt
lg:AOUT_
106:DATA
107:BCLK
]_ NpM__[ Ope- I __ Built-in _ ECC-core I. _ 108:LRCK
27.y__a plifierl CLVcontrol memory L-II_.I signal / 109:DOUT
110:MUTE
35:VCOIN" 112:MD2
_ _gLesiegrnat
I,°n_ _ Iprocessing[_'--"
124:SCKI c,oc
control CPU I/F
2:PLCKO_
43:MDSO 56:XWR
46:MDS1 57:XRD
48:MDPO 59-62, 64-67:DO-D7
49:MDP1 70-73, 75-78:AO-A7
47:MON 80:XlNT
53:LOCK 81:XCS
83:XWAT
84:XRST
55 - - 56 -

4-1-2. Pin Functions
Pin No. Signal Name Direction Level Function

1 PLCKI I 3.3 PLCK input
2 PLCKO O 3.3 PLCK output
3 VSS P Digital ground
4 i RFD B 3.3 RF2 value data input/output
5 VDD P 3.3 Digital positive power supply
6 v_s1 ADP Digital ground
7 VRB AI ADC reference
8 VRBS AI ADC reference
9 GNDA1 AP Analog ground
10 RFIN1 AI RF input
11 AIN AI RF input
12 RFIN2 AI RF input
13 VCCA1 AP 5 Analog positive power supply
14 VRTS" AI ADC reference
15 VRT AI ADC reference
16 VDD1 ADP 5 Digital positive power supply
17 VSS2 ADP Digital ground
18 VDD2 ADP 3.3 Digital positive power supply
19 AOUT AO DAC output
20 VCCA2 AP 3.3 Analog positive power supply
21 IREF AI DAC reference current
22 VREF AI DAC reference voltage
23 COMP AI DAC compensation pin
24 I_IAS AI DAC bias pin
26 VCCA3 AP 3.3 Analog positive power supply
27 Y AO Ope-amplifier output
28 FR1 AO Feedback resistance switching 1
31 INM AI Ope-amplifier negative input
32 INP AI Ope-amplifier positive input
35 VCOIN AI VCC control input
36 R1 AI VCO external resistor 1
37 R2 AI VCO external resistor 2
38 TEST0 AO VCO test output
39 VCCA4 AP Analog positive power supply
40 VCK B 3.3 VCO oscillation output/test input
- 57 -
42 TESTA I 3.3 Test pin
43 MDSO 0 5 CLV speed error
46 MDS 1 0 5 CLV speed error
47 MON 0 5 Motor on
48 MDP0 0 5 CLV phase error
49 MDP1 0 5 CLV phase error
50 DFCT 0 5 Defect detection output
51 NORF 0 5 NO RF detection output
52 JITPWM O 5 Jitter PWM output
53 LOCK O 5 EFM lock output
54 VDDS P Digital positive power supply
55 FWON I 5 Sync protection on
56 XWR I 3.3 CPU write
57 XRD I 3.3 CPU read l
59 DO B 5 CPU data
60 D1 B 5 CPU data
61 D2 B 5 CPU data
62 D3 B 5 CPU data
64 D4 B 5 CPU data
65 D5 B 5 CPU data
66 D6 B 5 CPU data
67 D7 B 5 CPU data
68 VDDS P 5 Digital positive power supply

69 TEST I 5 Test pin
70 A0 1 5 CPU address
71 A1 I 5 CPU address
74 SCEN(!) I 3,3

80 XINT OD 5 Interruption
81 XCS I 5 Chip select
-58-

83 XWAT OD 5 Wait
84 XRST I 5 Reset

86 TEST0 I 3.3 Test pin
87 SCMD I 3.3 Test pin
88 " ETST I 3.3 Test pin
89 VSS Digital ground
90 SDCK 0 3.3 SD bus clock
91 XSHD 0 3.3 SD bus header
92 XSRQ I 3.3 SD bus REQ
93 XSAK 0 3.3 SD bus ACK
94 SDEF 0 3.3 SD bus error flag
96 SDO o (B) 3.3 SD bus data
97 SD1 O (B) 3.3 SD bus data
99 SD3 o (a) 3.3 SD bus data
101 SD4 o (a) 3.3 SD bus data
102 SD5 o (B) 3.3 SD bus data
103 SD6 0 (B) 3.3 SD bus data
106 DATA O 3.3 CDDA data
107 BCLK O 3.3 CDDA bit clock
108 URCK O 3.3 CDDA LR clock
109 I_OUT O 3.3 Digital out
110 MUTE I 5 Audio mute
112 MD2 I 5 Digital out on
113 WFCK O 5 Frame clock
114 SCOR O 5 Subcode sync
116 EXCK I 5 SBSO reading clock
117 SBSO O 5 SubP to W serial output
119 SQSO O 5 SubQ serial output
120 SQCK I 5 SBSO reading clock
122 MCKI I 5 ECC clock
124 SCKI I 5 System clock
- 59 -
126 MNT0 B 3.3 Monitor bus
135 ESTB O 3.3 Error information strobe
137 MA0 O 3.3 DRAM address
!

141 MA3 O 3.3 DRAM address !
150 XMWR O 3.3 DRAM write enable
151 XCAS O 3.3 DRAM CAS
153 XRAS O 3.3 DRAM RAS
154 xoz O 3.3 DRAM output enable
156 MD00 B 3.3 DRAM data
159 MD03 B 3.3 DRAM data "
- 60 -
i68 MD10 B 3.3 DRAM data
169 MDll B 3.3 DRAM data
174 M-D15 B 3.3 DRAM data
175 PLDIR I 3.3 PLCK direction control
*Function of direction
I [input], O [output], OD [output (open drain)], O(B) [output (bi-direction during test)],
B[input/output (bi-direction)], P [power supply], ADP [power supply (digital for analog cell)],
AP [power supply (analog)].
AI [input (analog)], AO [output (analog)]
- 61 -
4-2. AV Decoder L64020 (MB-78 Board IC203)
c-
O
II
rn
o,1
x
<
a
co
- 62 -

4-2-2. Pin Assignment
Pin No. Signal Name Pin No. Signal Name Pin No.. Signal Name
1 VSS 41 NC 80 NC
2 SBD_7 42 VDD 81 VSS
3 SBD_6 43 A_2 82 PD_5
4 SBD_5 44 A_I 83 PD_6
5 SBD_4 45 A_0 84 PD_7
6 VDD 46 VSS .- 85 VSS
7 SBD_3 47 D_7 86 BLANK
8 SBD_2 48 D_6 87 CREF
9 SBD1 49 D_5 88 EXT_OSD_0
10 SBD_0 5O D_4 89 EXT_OSD_I
11 VSS 51 D_3 90 EXT_OSD_2
12 CH_DATA_0 52 D-2 91 EXT_OSD_3
13 CH_DATA_I 53 D-l 92 NC
14 CH_DATA_2 54 D-0 93 VDD
15 CH_DATA_3 55 VSS 94 ACLK_441
16 CH_DATA,_4 56 SYSCLK 95 ACLK_48
17 CH_DATA_5 57 RESET_N 96 ACLK_32
18 CH_DATA_6 58 DREQ_N 97 VSS
19 CH_DATA_7 59 INTR_N 98 CD_BLK
20 VSS 60 BUSMODE 99 CD_LRCLK
21 TOS_N 61 VDD 100 CD_ALCK
22 NC 62 DTACK_N/ 101 CD_ASDATA
23 NC RDY_N 102 SPDIF_N
24 63 READ/READ_N 103 A_ACLK
ERRO__N
25 VDD 64 DS_N/WRITE_N 104 VDD
26 AVALI__N 65 WAIT_N/WTN 105 BCLK
27 VVALID_N 66 VSS 106 LRCLK
28 DCK 67 AS_N 107 ASDATA
29 VREQ_N 68 CS_N 108 NC
30 AREQ_N 69 VS 109 NC
31 NC 70 HS 110 VSS
32 NC 71 VDD 111 SPDIF_OUT
33 VSS 72 OSD_ACTIVE 112 AUDIO SYNC
34 A8 73 PD_0 113 TM1
35 A7 74 PD_I 114 TM0
36 A_6 75 VSS 115 ZTEST
37 A_5 76 PD_2 116 SCAN_TE
38 A_4 77 PD_3 117 PREQ_N
39 A_3 78 PD_4 118 VDD
40 VDD 79 VDD 119 SBC_15
- 63 -

Pin No. Signal Name
120 SBD14
121 NC
122 SBD_13
123 VSS
124 SBD_12
125 SBD_11
126 SBD_10
127 VDD
128 SBD_9
129 SBD_8
130 SCLK
131 VSS
132 SBA_9
133 SBA_8
134 SBA_7
135 VDD
136 SBA_6
137 SBA_5
138 SBA_4
139 VSS
140 SBA_3
141 SBA_2
142 SBA_I
143 VDD
144 SBA_0
145 SBA_10
146 SBA_ll
147 VSS
148 SCSI_N
149 SCS_N
150 SRAS_N
151 VDD
152 SRAS_N
153 SWEN
154 SDQM
155 VSS
156 PLLVDD
157 NC
158 PLLVSS
159 VDD
160 NC
- 64 -
4-3. Digital Signal Processor CXD8730R (MB-78 Board IC506)
4:3-1. Pin Assignment
G1012 1 7 ] PWMO
G1011 2 (_ 74] PWM1
GI010 3 73 "l PWM2
GI09 4 72 -I HCWHLBS
GI08 s 71 -1 HFS/HMR
DGND 6 70 "1 HR/HRD
G}07 7 69 -1 HX/HINT
GI06 I- 8 68 ] SER/PAR
GIOS/TMC1 [" 9 67 '-] DVCO

' GIO4/TMCO F lo 663 Xl
' GlO3,qNT5 I- 11 65 -L X2/CLKIN

GIO2/INT4 I- 12 64 -1 DGND
GIO1ANT3 E 13 63 3 HOO/HDO
GI_INT2 I- 14 62 -1 HOI/HD1
DGND [ 15 61 HO2/HD2
DVCC E 16 6o HO3/HD3
AIN9 [- 17 59 HO41HD4
AIN8 E _ 5_ HOS/'HD5
AIN7 [ _9 57 HO6/HD6
AIN6 I- 20 56 HO7IHD7
NN5 [- 21 55 DVCC
A|N4 E 22 54 DGND
AIN3 I- 23 53 AGND
AIN2 E 24 52 AVCC
AIN1 [" 25 51 VRBO
/
L_IL.._L_IL_IL_If._IL_Ii_IIIL_/L_.IL__L._L._JL_JL_IL_JL_JL_JL_J__
- 65 -

This section describes signals. The input/output states of signals are differentiated by the input (I), output
(O), and high impedance (Z). Each signal is grouped by function.
Pin ]Signal Name I,I/0 I Type Function

Analog signal pin
29 VRTS O Analog AD upper limit reference voltage output. When Using
3.75V for the upper limit reference voltage, connect
the VRTS output to the VRTA input.
28 VRTA I Analog AD upper limit reference voltage input.
33 VRBS O Analog AD lower limit reference voltage output. When using
1.25V for the lower limit reference voltage, connect
the VRBS output to the VRBA input.
34 VRBA I Analog AD lower limit reference voltage input.
26-27 AIN0-AIN9 I Analog Analog data input signal. Analog signal input to the
8-bit AD converter. The input to the AD converter is
switched automatically by the analog switch.

49 AOUT0 O Analog DAC0 buffer output signal. DAC0 buffer output. The
power down mode can be seleJted.
50 VRT0 I Analog DAC0 buffer upper limit reference voltage input.
51 VRB0 I Analog DAC0 buffer lower limit reference voltage input.
46 AOUT1 O Analog DAC 1 buffer output signal. DAC 1 buffer output. The
power down mode can be selected.
45 VRT1 I Analog DAC 1 buffer upper limit reference voltage input.
44 VRB 1 I Analog DAC 1 buffer lower limit reference voltage input.
42 VRT2 I Analog DAC 1 buffer upper limit reference voltage input.
43 VRB2 I Analog DAC2 buffer upper limit reference voltage input.
37 VRT3 1 Analog DAC2 buffer upper limit reference voltage input.
36 VRB3 I Analog DAC3 buffer lower limit reference voltage input.
PWM pin
75-73 PWM0-PWM2 O CMOS PWM output signal. 8-bit PWM output. The output
pulse width can be set any value.
Host interface pin
68 SER/PAR I TTL Host interface serial/parallel mode selection.
H:Serial, L:Parallel.
70 HR/HWR I TrL Host serial data/host data read strobe signal input. In
(Internal pull-up) the serial mode, the serial data is input. In the parallel
mode, the data read strobe signal is input.
- 66 -

!
Pin Signal Name I/O Type Function
71 HFS/HWR I TTL Frame sync signal/host data write strobe signal input
for data transmission. In the serial mode, the data
transmission frame sync signal is input. In the parallel

mode, the data write strobe signal is input.
69 HX/HINT O/Z CMOS Host serial data/host interrupt signal output. In the
serial mode, the serial data is output. In the parallel
mode, the host interrupt signal is output.
72 HCK/HLBS TTL Clock/host low byte select signal input for host serial
datatransmission. In the serial mode, the serial data
transmission clock is input. In the para!lel mode, the
low byte select signal is input.
63-57 HO0/HD0- I/O TTL General data output/parallel data input/output. In the
HO6/HD6 serial mode, the general data is output. In the parallel
mode, the parallel data is input/output.
56 HIO/HD7 I/O TTL General data/parallel data input/output. In the serial
mode, the general data is input/output. In the parallel
mode, the low byte select signal is input.
General input/output pin
14 GIO0/INT2 lJO TTL General data input/output/INT2 external interrupt
signal input. Selected by the interrupt control register.
13 GIO1/INT3 I/O TTL General data input/output/INT3 external interrupt
signal input. Selected by the interrupt control register.
signal input. Selected by.the interrupt control register.
| signal input. Selected by the interrupt control register.

10 GIO4/TMC0 I/O TIL General data input/output!timer 0 external clock
i
input. Selected by the timer control register.

9 GIO5/TMC 1 I/O TTL General data input/output/timer 1 external clock
input. Selected by the timer control register.
8, 7_ GIO6-GIO15 I/O TTL General data input/output. The input/output is set by
5-1, the GIO control register. The input data is set to the
100-98 general input register. The data of the general output
register is output. When using a GIO from GIO0 to
GIO5 as the interrupt signal or input clock, be careful
not to set the corresponding control bit to the output
when changing the value of the GIO control register
value.
Track counter
88 TTREF TTL Track counter reference pulse signal input.
(Hysteresis)
89 TRIN TTL Track pulse signal input.
(Hysteresis)
- 67 -

Pin I Signa,
Name Ivol Type Function
FG/PG counter
90 FGREF I TTL FG counter reference pulse signal input. The polarity
(Hysteresis) of the input can also be checked by the host output
register (bit 10).
91 FGIN I TTL FG pulse signal input. The polarity of the input can
(Hysteresis) also be checked by the host output register (bit 9).
92 PGREF I TTL PG counter reference pulse signal input.
(Hysteresis)
93 PGIN I TTL PGpulse signal input.
(Hysteresis)
JTAG pin
77 EMU0 IIO/Z TTL Emulator pin 0
(Internal pull-up)
76 EMU1 I/O/Z TTL Emulator pin 1
(Internal pull-up)
84 TRST I TTL JTAG test reset pin
(Internal pull-up)
81 TMS I TTL JTAG test mode select pin
(Internal pull-up)
78 TDO O/Z TTL JTAG test data output pin
80 TDI I TTL JTAG test data input pin
(Internal pull-up)
79 TCK I/O TTL JTAG test clock
(Internal pull-up)
Other signal pins
95 CLKOUT1 O COMS Master clock output signal
94 RS I TTL Reset input
(Internal pull-up)
65 X2/CLKIN I Oscillator Internal oscillator input/clock input
66 Xl O Oscillator Internal oscillator output
31 TESTA O - Reserved pin. Use without connecting.
Power supply pin
16,55. DVcc - +5V supply pin for digital circuit.
67,83
97
6,15, DGNO - Ground pin for digital circuit.

54,64,
82,85-
87,961
- 68 -

Pin Signal Name I/0 Type Function
27, 30, AVcc +5V supply pin for analog circuit.
39, 48,
52
32, 35, AGND Ground for analog circuit.
40, 47,
53
- 69 -
4-4. AC3 Decoder
MB86342 (MB-78 Board IC104)
B-bus
/_-OLIS _'.DUS
-- MCLK1
MCLK2
-- XRST
SGKO
- -- MS
EXTIN
CLKGM •- _ KFSlO
PM
MCORE -- PSTOP
FS1,FS2
-- SYNC
EXLOCK
LRCKI1
-- LRCKI2
BCKI1
ADIF -- BCKI2
- -- SDII,SDI2
LRCKO
_ B_KO
SDOO-SD03
-- HCLK
-HDIN
HISF HDOUT
"HCS
-- BST
GP .... GPO-GP7
MEM
--MOD
-CS
EXMIF ._ WE
AOO-A15
DOO-D19
--ICBRK
EMUIF ICCLK
._ICSO-ICS2
-ICDO,ICD1
LOG
U
- 70 -

Pin No. Signal Name I/O Function
5 MCLKI I Clock input pin

6 MCLK2 I/O Clock input/output pin
1 XRST I Reset signal input
8 SCKO O System clock output pin
12 MS I Master/slave selection pin
L:Master (Crystal oscillation) H:Slave (External clock)
16 S_NC I Sync/async selection pin (L:Sync, H:Async)
2 EXTIN I System clock (384 fs) input pin
13, 14 FS1, FS2 I Sampling frequency switching signal input pin
7 KFSIO I/O Audio clock (384 fs) input!output pin
9 PM I Test pin (normally set to GND.)
10 PSTOP I PLL/crystal oscillator control signal input pin
11 EXLOCK I Lock signal input pin
41 HCLK I Host interface clock input pin
43 HDIN I Host interface serial data input pin
44 HDOUT O Host interface serial data output pin
42 HCS I Host interface chip select input pin
45 BST I Normally fixed at "L".
39-35, 32-30 GP0-GP7 I/O 8-bit general port input/output pin
17 LRCKI1 I/O Sampling clock input/output pin for audio interface serial
data
18 BCKI1 I/O Bit clock input/output pin for audio interface serial data
20 LRCKI2 I Sampling clock input pin for audio interface serial data
21 BCK12 I Bit clock input pin for audio interface serial data
19, 22 SD_I, SDI2 I Serial data input pin for audio interface
23 LRCKO o Sampling clock output pin for audio interface serial data
24 BCKO o Bit clock output pin for audio interface serial data
25-27 SDO1-SDO3 o Serial data output pin for audio interface
46 MOD I Pass mode control signal input pin
47 CS o Chip select output pin for external SRAM interface
48 WE o Write enable output pin for external SRAM interface
67-66,
64-55, A00-A 15 O Serial data output pin for external SRAM interface
52-49
92, 91, 89-85
82-80, D00-D19 I/O Data input/output pin for external SRAM interface
77-68
93 ICCLK o Clock output pin for emulator
94 ICBRK I External brake control signal input pin for emulator
96, 95 ICD0, ICD 1 I/O Data/address input/output pin for emulator
99-97 ICS0-ICS2 o Status output pin for emulator
-71 -

4-5. Large Gate Array CXD8728 (MB-78 Board IC804)

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- 72 -
Pin No. Signal Name RD/WR,SHIF Function "

I VDD VDD
2 DVDLDONn I/O, RD/WR DVD laser light/off signal:ON when "L"
3 CDLDONn I/O, RD/WR CD laser light/off signal:ON when "L"
4 CDfDVD I/O, RD/WR Signal differentiating between CD and DVD:DVD
when "H".
5 OPN/CLS I/O, RD/WR Tray open/close. Open at "H" and Close at "L". Stop
when "Hiz".
6 DRERR I/O, RD DIR LC89051V error signal. Error when "H".
7 NSTn I/O, RD/WR Spindle motor non-control voltage input.
Stop when set to 0V.
8 SPCTL1 I/O, RD/WR Switches the spindle servo operation mode.
Can be set to control, non-control, acceleration.
9 SPCTL0 I/O, RD/WR Switches the operation mode between SPCTL 1 and
2Bit.
Can be set to control, non-control, acceleration.
10 SPGC2 I/O, RD/WR Spindle servo gain control signal.
Switches the gain of the "post stage" amplifier.
11 DETON I/O, RD/WR CD/DVD differentiation sensor ON/OFF SW
(Tout) signal:ON when "H"
(Data output during memory test)
12 ACDDET I/O, RD CD/DVD differentiation signal (sensor output
which is waveform-shaped)
13 TILT/H I/O, RD/WR TILT servo characteristics switching signal
14 BUS_2 I/O, RD Servo DSP busy flag:Busy when "L"
15 ERROR I/O, RD Servo DSP error flag:Error when "L"
i
(TIN) (clk signal input during the memory test)

16 LOCK I/O, RD From ARP
17 FOK I/O, RD From DSP
18 TRAYFREE I/O, RD/WR Releases the tray driver. Open when "L".
19 S 12VOFF I/O, RD/WR Servo 12V power supply OFF. 12V on when "H"
20 VDD VDD
21 GND GND
22 SPGC 1 I/O, RDAVR Spindle servo gain control signal.
Switches the gain of the "first stage" amplifier.
23 TBLR I/O, RD/WR Changer roulette rotation. Rotates when "H".
24 TBLL I/O, RD/WR Changer roulette rotation. Rotates when "H".
25 LDOUTn I/O, RD/WR Changer loading OUT. Loading out when "L".
26 LDINn I/O, RD/WR Changer loading IN. Loading in when "L".
27 ACHUCK I/O, RD Mechanism chucking detection signal.
"H" when chucking.
28 ATRAY I10, RD Tray open signal. "H" when the tray is open.
- 73 -

Pin No. Signal Name RD/WR,SHIF Function
29 TSENS I/O, RD Changer roulette position detection sensor.
No groove when "L". Groove is present when "H".
30 DSENS I/O, RD Changer disc presence detection sensor.
Present when "H" and absent when "L".
31 $3 I/O, RD DISC detection position (rotary sensor) 0 to 7 value
32 $2 I/O, RD DISC detection position (rotary sensor) 0 to 7 value
33 S1 I/O, RD DISC detection position (rotary sensor) 0 to 7 value
34 ACSn I/O, RD/WR AC3_DEC MB86432 chip select
35 ACSI Serial I/F, IN AC3_DEC MB86432 output data
36 VCSn I/O, RD/WR V_Enc CXD1914Q Chip select (XVENCCS)
37 VSI Serial I/F, IN V_Enc CXD1914Q output data
38 KLTn I/O, RD/WR Karaoke DSP CXD2721Q serial data latch
39
40 VDD VDD
41 GND GND
42 GND GND
43 KSI Serial I/F, IN Karaoke DSP CXD2721Q oqtput data
44 IFSI Serial I/F, IN IF CON output data
45 DBSI Serial I/F, IN Debug serial port output data
46 SCKG3 Serial I/F, OUT Serial Group3 Clock
47 SOG3 Serial I/F, OUT Serial group 3 output data
48 SDEN UO, RD/WR SSI (SSI133P3720) chip select
49 DCSn I/O, RD/WR DNR (CXD 1854Q) chip select (XDNRCS)
50 MLTn I/O, RD/WR DAC (CXD8696R) data latch (DACLT)
51 ECSn I/O, RD/WR EEPROM (BA9020F) chi p select (XEERCS)
52 SSSD Serial I/F, IN SSI (SSI133P3720) input/output data
53 EESI Serial I/F, IN EEPROM (BA9020F) output data
54 EWCn I/O, RD/WR EEPROM (BA9020F) Write control (XEEWE)
55 EBSYn I/O, RD EEPROM (BA9020F) BUSY signal (XEERBS)
56 IRDn Peripheral I/F, OUT Peripheral read signal
57 IWRn Peripheral I/F, OUT Peripheral write signal
58 SDSPRDn Peripheral I/F, OUT Servo DSP chip select & read
59 ARPCSn Peripheral I/F, OUT ARP chip select
6O ARPINT Peripheral I/F, IN ARP INT signal input
61 ARPWTn Peripheral I/F, IN ARP WAIT signal input ..
62 DCRCSn Peripheral I/F, OUT DECRYPT chip select
63 DCRINT Peripheral I/F, IN DECRYPT INT signal input
64 DCRWTn Peripheral I/F, IN DECRYPT WAIT signal input
65 AVCSn Peripheral I/F, OUT AV_DEC(L64020) Chip Select
66 AVWTn Peripheral I/F, IN AV_DEC (L64020) WAIT signal input.
Masked by AVCSn.
67 XWAIT'n SHIFT, OUT
" 68 XIRQ3 SHIFT, OUT
- 74 -
69 SIG1 SHIE OUT
70 SIG2 SHIE OUT
71 XmQ7 SHIF, OUT
72 XCS6n SHIE IN
73 XRDn SHIE IN
74 XLWRn SHIE IN
75 HA21 SHIE IN
76 HA20 SHIE IN
77 SDSPWRn Peripheral I/F, OUT Servo DSP chip select & write
78 CPCK SHIE IN CPU clock
79 GND GND
80 GND GND
81 VDD VDD
82 BUSGATE BUSCNT, OUT BUS buffer control. Gate off when "H".
83 HA19 SHIE IN
84 HA7 SHIF, IN
85 HA6 SHIE IN
86 HA5 SHIF, IN
87 HA4 SHIF, IN
88 HA3 SHIF, IN
89 HA2 SHIF, IN
90 HA1 SHIF, IN
91 HA0 SHIF, IN
92 HD7 SHIF, bidir
93 HD6 SHIF, bidir
94 HDI_ SHIF, bidir
95 HD4 SHIF, bidir
!
96 HD3 SHIF, bidir

97 HD2 SHIF, bidir
98 HD1 SHIF, bidir
99 HD0 SHIF, bidir
100 VDD VDD
101 GND GND
102 FWON I/O, RD/WR ARP block, sync protection circuit ON/OFF
(for external control)
103 MD2 I/O, RD/WR ARP block, digital audio output mute.
104 MUTE I/O, RD/WR ARP block, audio output mute.
105 DFCT I/O, RD/WR ARP block, defect detection.
106 NORF I/O, RD/WR ARP block, No-RF detection
107 DBGINTn SHI, IN Serial IC interruption for debugging. Level

108 SOG1 Serial I/F, IN Serial Group 1 (TXD)
109 IFSO Serial I/F, OUT TXD to Serial Group 1 IF
110 DBSO Serial I/F, OUT TxD to Serial Group 1 Diagnostic Connector
- 75 -
111 (DIAGN) H/W, IN
112 (CTS) H/W, OUT
113 SCKG2, (IRQ5) H/W, IN/OUT SH serial channel I SCLK (GROUP2) or IRQ5
output
114 AVCK H/W, o'UT AV Enc CXD1914 serial clock
115 CK27M " 'H/W, IN AV CK Resync 27Mclock
116 GAIN6n I/O, RD/WR AUDIO output gain switching signal 4 (AC-3)
channel L, R (or spare port)
117 D2LTn I/O, RD/wR 2 Channel DAC Latch
118 PDCLK HW/IN 13.5 M CLOCk input
119
120 VDD VDD
121 GND GND
122 GND GND
123 RESETn H/W, IN System reset
124 CTS UO, RD/WR Host status notification. Ready when "L"
125 DIAGN I/O, RD/WR Presence/absence Of connector of diagnostic
connector. Connected when "L".
126 TEB Memory test setting. Normally pull up.
127 HsYNc HW/IN HSYNC input
128 SCKG2PS H/W, OUT Serial Group 2 sync clock (P/S) 1 MHz
129 SOG2PS H/W, OUT Serial Group2 TxD
130 DC/_I3D I/O, RD/WR DCS control
131 TON I/O, RD/WR Test 'tone
132 xIFBSY ' I/0, RD I/F CON BUSY Status

133 XSHINT ....I/O, RD/WR Communication request to I/F CON. Request for
interrupt when "L"
134 SCKG4 Serial I/F, OUT Serial Group 4 Clock
135 SOG4 Serial I/F, OUT Serial group 4 output data
136 DDLT 1n I/O, RD/WR DAC PCM1716 data latch-I (L/R) Grp4
137 DDLT2n ' I/O, RD/WR DAC PCM1716 data latch-2 (SL/SR) Grp4
138 DDLT3n frO, RD/WR DAC PCM17 i6 data latch-3 (C/SW) Grp4
139 DLTn I/O, RD/WR DIR LC89051V data latch Grp4
140 OHSYNC' H/W, OUT Advance HSYNC output
141 TOFC 1 I/O, RD/WR Tracking'Offset Control 1 -
142 TOFC2 I/O, RD/WR Tracking Offset Control 2
143 scKG4n Serial I/F, OUT DIR LC89051V serial clock
144 KADTS'EI_ I/O, RD/WR Selects whether to use the Karaoke DSP
CXD2721Q. When used=H (KD_SEL)

145 KRDY I/0, RD Selects whether to enable or disable Karaoke DSP
CXD2721Q transmission.
When transmission is enabled=H
-76-
146 CLAPBSY I/O, RD When the clap IC MSM6654 is generating sounds,
outputs the "H" level. When the power is turned
ON.
147 OTASUKE I/O, RD Active "L" level when the help IC NJM2072M is
needed.
148 DVD/VTR I/O, RD/WR Video control. Selects the video signal external
input. Selects the external input when "H" is output.
149 AVCNT I/O, RD/WR Video control. AV control signal. EURO AV ON
when "H" is output.
150 EAIV/Y I/O, RD/WR Video control. Composite, YC selection. YC is
selected when "L" is output.
151 E/_IV/RGB I/O, RD/WR Video control. Composite, RGB selection. RGB is
selected when "L" is output.
152 VS1 I/O, RD/WR Video control. S pin control signal.
153 FS I/O, RD/WR Frequency setting:L=_. 1 kHz, H=48 kHz
154 EXCLOCK I/O, RD/WR External frequency lock detection:L=Locked.
H=Not locked.
155 BST I/O, RD/WR Boost strap (when boosting the farm)
Set to the "H" level.
156 CLAPSW1 I/O, RD/WR Phrase input corresponding to the sound generated
by the clap IC MSM6654. (Required)
157 CLAPSW0 I/O, RD/WR Phrase input corresponding to the sound generated
by the clap IC MSM6654. (Required)
158 DOUTCTL I/O, RD/WR Digital out ON/OFF ("H":ON, "L":OFF)
(DO-CTL)
159 GNq GND
160 GND GND
!
- 77 -

4-6. Middle Gate Array CXD8746 (IC101 on MB-78 board)
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- 78 -

!
Pin No. Signal Name I/0 Level From/For Function

1 ARSTI IN 5V
2 XLOCKI IN 5V
3 DVD IN 5V
4 SCK21 IN 5V LGA AC3 serial communication
5 SO21 IN 5V LGA AC3 serial communication

6 ACSI IN 5V LGA AC3 serial communication
m
7 BSTI IN 5V LGA
8
9 FS768 IN 5V 768fs
10
11 MCK27 IN 5V 27M clock
12
13 TON IN 5V Test tone on/off
14 DC3D IN 5V 2ch DAC data switching
15 DATA2 OUT 5V 2Ch DAC Audio signal to 2ch DAC
16 LRCK2 OUT 5V 2Ch DAC Audio signal to 2ch DAC
17 BCK2 OUT 5V 2Ch DAC Audio signal to 2ch DAC
18
19 BCK9 OUT 5V 6Ch DAC Audio signal to 6ch DAC
20 LRCK9 OUT 5V 6Ch DAC Audio signal to 6ch DAC
21 DATF9 OUT 5V 6Ch DAC Audio signal to 6ch DAC
22 DATR9 OUT 5V 6Ch DAC Audio signal to 6ch DAC
23 DATC9 OUT 5V 6Ch DAC Audio signal to 6ch DAC
24
t
25 BSTO OUT 3.3V AC-3
26 ACSO OUT 3.3V AC-3 AC_3 serial communication
27 SO20 OUT 3.3V AC-3 AC_3 serial communication
28 SCK20 OUT 3.3V AC-3 AC_3 serial communication
29 DETON IN 3.3V
30 XLOCKO OUT 3.3V AC-3
31 ARSTO OUT 3.3V AC-3 AC_3 reset signal
32
33 DATC8 IN 3.3V AC-3 Audio (C/S) signal from AC_3
34 DATR8 IN 3.3V AC-3 Audio (RL/RR) signal from AC_3
35 DATF8 IN 3.3V AC-3 Audio (FR/FL) signal from AC_3
36 BCK8 IN 3.3V AC-3 Audio signal from AC_3
37 LRCK8 IN 3.3V AC-3 Audio signal from AC_3
38
39 DATA7 OUT 3.3V AC-3 Audio signal (DIR) to AC_3
40 BCK7 OUT 3.3V AC-3 Audio signal (DIR) to AC_3
41 LRCK7 OUT 3.3V AC-3 Audio signal (DIR) to AC_3
- 79 -

Pin No. Signal Name I/O Level From/For Function
42
43 DATA5 OUT 3.3V AC-3 Audio signal (Karaoke) to AC_3
44 BCK5 OUT 3.3V AC-3 Audio signal (Karaoke) to AC_3
45 LRCK5 OUT 3.3V AC-3 Audio signal (Karaoke) to AC_3
47 FS384 OUT 3,3V AC-3 AC3 384fs
48
49 LRCK3 OUT 5V Karaoke Audio signal to karaoke
50 BCK3 OUT 5V Karaoke Audio signal to karaoke
51 DATA3 OUT 5V Karaoke Audio signal to karaoke
52 DATA4 IN 5V Karaoke Audio signal from karaoke
53
54 DATA1 IN 3.3V AV-Dec Audio signal from AV-Dec
55 LRCK1 IN 3.3V AV-Dec Audio signal from AV-Dec
56 BCK1 IN 3.3V AV-Dec Audio signal from AV-Dec
57
58 DATA6 IN 5V DIR Audio signal from DIR
59 LRCK6 IN 5V DIR
Audio signal fr_rn DIR
60 BCK6 IN 5V DIR Audio signal from DIR
61
62 KDTSEL IN 5V Karaoke/main data switching
63 XRST IN 5V Reset
64
- 80 -
4-7. Small Gate Array CXD8747 (MB-78 Board IC807)
SGA 5V
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- 81 -

4-7-2. Pin Assignment
Pin No. Signal Name I/0 BUFF.TYPE Pin No. Signal Name I/0 BUFF.TYPE
I HA2 l TLCHT 51 VSS
2 HA3 ! TLCHT 52 IA1 O B8
3 HA4 T TLCHT 53 IA0 O B8
4 VSS 54 VSS
5 HA5 T TLCHT 55 DO O B2
6 HA6 I TLCHT 56 SCKO O B2
7 HA7 T TLCHT 57 CSO O B2
8 HA8 I TLCHT 58 VDD
9 VDD 59 XRST O SCHMITT
i0 VSS 60 VSS
II HD0 I/O BD8T 61 CK 0 SCHMITT
12 HD1 I/O BD8T 62 VDD
13 HD2 I/O BD8T 63 HA0 O TLCHT
14 HD3 I/O BD8T 64 HA1 O TLCHT
15 VSS 65
16 HD4 UO BD8T 66
17 HD5 I/O BD8T 67
18 HD6 I/O BD8T 68
19 HD7 I/O BDST 69
20 VSS 70
21 VDD 71
22 VSS 72
23 CSI I TLCHT 73
24 SCKI I SCHMITT 74
25 DI I TLCHT 75
26 VDD 76
27 VSS 77
28 DIR I TLCHT 78
29 OE 1 TLCHT 79
30 NC 8O
31 VDD 81
32 VSS 82
33 ID7 I/O BD8T 83
34 ID6 I/O BD8T 84
35 ID5 I/O BD8T 85
36 ID4 I/O BD8T 86
37 VSS 87
38 ID3 I/O BD8T 88
39 ID2 I/O BD8T 89
40 ID1 I/O BD8T 9O
41 ID0 I/O BD8T 91
42 VSS 92
43 VDD 93
44 IA8 I B8 94
45 IA7 I B8 95
46 IA6 I B8 96
47 IA5 I B8 97
48 IA4 I B8 98
49 IA3 I B8 99
50 IA2 1 B8 100
- 82 -
5 OVERALL BLOCK DIAGRAM
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SONY,

DVP-M35/S300/S305/S315/ S500D/S 505D/$715 Manual: Operation

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DVP-M35/S300/S305/S315/ S500D/S 505D/$715 Manual: Operation

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DVP-M35/S300/S305/S315/

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1-1. Series line-up ...............................................................................................................6

1-2. External appearance diagram ..................................................................................7

1-3,.Internal appearance diagram (top view) ..............................................................8

1-4. Disc drive unit ........................................................................................................... 10

1-5. Block diagram ........................................................................................................... 13

2. SIGNAL PROCESSING BLOCK ................................................................... 15

2-1. DVD RF FRONT END ..........................................................................................15

2-2. CD RF FRONT END ..............................................................................................19

2-3. RF SIGNAL PROCESSING BLOCK ...............................................................2O

2-4. Decrypt Block ...........................................................................................................21

2-5. AV Decoder Block ...................................................................................................21

2-6. OSD Block .................................................................................................................21

2-8. Clock Generation Block ......................................................................................... 24

2-9. AC-3 Decoder Block ...............................................................................................25

2-10. Audio L, R 2ch Signal Block .............................................................................26

2-11. Audio 5. lch Signal Block ....................................................................................27

2-12. DVP-S715 AU-205 Board Block Diagram ....................................................28

2-13. System Control Block ...........................................................................................29

2-14. Interface Control Block ........................................................................................29

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3-1. General Description of Servo Circuits ............................................................... 33

3-2. Servo Operation at DVD Play .............................................................................. 34

3-3. Servo Operation at CD and Video CD Playing ...............................................46

3-4. Disc Loading and Chucking ..................................................................................50

3-5. Differentiation of Disk Type ................................................................... 52

3-6. Block Diagram (Servo) ...........................................................................................53

4. IC PIN DESCRIPTION ..........................................................................................

4-1. ARP CXD1865R (IC806 on MB-80 board) ..................................................... 55

4-2. AV Decoder L64020 (IC203 on MB-78 board) ..............................................62

4-3. Digital Signal Processor CXD8730R (1C506 on MB;.78 board) ............... 65

4-4. AC-3 Decoder MB86342 (IC104 on MB-78 board) ......................................70

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5. OVERALL BLOCK DIAGRAM ......................................................................

5-1. RF, Servo, Audio, Power Block Diagram ......................................................... 83

5-2. Signal Processing Block Diagram ....................................................................... 89

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This guidebook describes the DVD-Video.

1-1. Series line-up

*AC3 : 5.1 ch OUT (With built-in decoder)

*Output terminal : S terminal, video, audio x2

® 280 size model

DVP-M30 NTSC Japan specifications (100V)

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21P Euro (DVP-S315, $715)

1-2. External appearance diagram

(_) 280 size models

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1-3. Internal appearance diagram (top view)

(_) Basic Dolby digital models

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POWER BLOCK _..

(_) Basic models

PS board (DVP-S715) Power transformer AU board

(AUDIO POWER) (DVP-S715) ,_ (AUDIO)

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DVD system OPT

Skew adjustment Tilt motor

Configuration of thread system

Specification DVD system OPT DC system OPT

Drive unit 2-shaft 2-shaft

Object lens Glass Plastic

"1: SingleLayerdisc 2: DualLayerdisc 3: Peakto PeakDifferential