ZXMP S385 CSEP Board Maintenance Manual-Board Overview

ZXMP S385 CSEP Board Maintenance Manual－Board Overview
For internal use only▲
ZXMP S385 CSEP Board Maintenance
Manual
Board Overview
(V2008-05)
Overseas Customer Service Dept. of Transmission & Power
Supply Products
May 2008
All rights reserved 1 in 21

Information Security Policy:
This document belongs exclusively to ZTE CORPORATION, and the readers are
required to keep its confidentiality.
Information security policies for different document types:
 Documents about technical know-how have an infinite length of period for their
confidentiality.
 Documents about deployment guide are for internal use only.
 Documents about maintenance experience are for internal use only.
Release: Overseas Customer Service Dept. of Transmission & Power Supply Products
Document Upgrade Policy:
 Send your feedback about the absence of the necessary product documents to
doc@zte.com.cn, and it will send the request to the Document Release
Administrator in corresponding divisions to have the documents written. When
the documents are done and have passed review, they will be uploaded to
http://tsm.zte.com.cn by the Document Release Administrator along with a notice
of their names published.
 Send your feedback about the errors in the current product documents to
doc@zte.com.cn, and it will send the information to the Document Release
Administrator in corresponding divisions to have the documents upgraded
(revision record is attached). When the documents are done and have passed
review, they will be uploaded to http://tsm.zte.com.cn by the Document Release
Administrator to have the previous documents replaced. For major changes in
technical document, a change notice is published at the same time; for routine
upgrade and changes in technical document, a notice by mail is sent every
quarter.

Revision Record
Release Created/Revised
Version Cause for revision Revision content
time by
V2008-05 May 2008 Shi Xinliang First release None

Contents
Chapter 1 Board Position in the System..........................................................................................................5

1.1 Overview.................................................................................................................................5
1.2 Board Position in System......................................................................................................5
Chapter 2 Board Classification and Names................................................................................................7
Chapter 3 Schematic Diagram and Working Principles............................................................................8

3.1 Software Flow Chart.........................................................................................................................8
3.2 Schematic Diagram and Working Principles..................................................................................8
3.3 Clock Unit Diagram and Working Principles...............................................................................10
Chapter 4 Board Functions.........................................................................................................................12
Chapter 5 Board Panel Indicators and Controls......................................................................................14
Chapter 6 Board Running States...............................................................................................................16
Chapter 7 Board Reset................................................................................................................................19

ZXMP S385 CSEP Board Maintenance Manual—Board Overview
Chapter 1 Board Position in the System

1.1 Overview
CSEP board includes three function modules: service cross-connect module, overhead cross-connect
module and clock module.
Cross-connect unit is the core of the whole system. It means that the cross-connect unit is not only
the core of service cross-connect but also the HW bus. Cross-connect unit is the convergence center of
system service and HW bus. Cross-connect unit provides the following functions:
1. Dispatches the services in various optical directions according to the configuration information
from the NMS and the alarm information in various optical directions on the HW bus;
2. Implements overhead cross-connect, path protection switching, APS bridging and switchover;
and
3. Detects and reports alarms.
The cross-connect capability of CSEP board is 180 Gbit/s, in which 140 Gbit/s is divided to slots of
service boards and each slot has a maximum capacity of 10 Gbit/s. The rest 40 Gbit/s cross-connect
capability is used for lower-order cross-connect board. CSEP board at the maximum supports a TCS board
with a cross-connect capability of 256*256 VC4s.
1.2 Board Position in System

Slots 8 and 9 of ZXMP S385 are available for the CSEP board.
Figure1.1 CSEP board position in ZXMP S385 system
All signal lines of CSEP are connected to the sockets at the backplane of the board. Connections
between CSEP board and the other service buses in the system are illustrated in the figure below:

Figure1.2 Relationship between CSEP board and other boards

Chapter 2 Board Classification and Names

CSEP board includes two parts: higher-order cross-connect unit and lower-order cross-connect unit.
Each CSEP board allows a cross-connect capacity of 72*72 STM-16. Lower-order cross-connect module
is classified into several types by capacity: 32*32 VC4s, 64*64 VC4s, 126*128 VC4s and 256*256 VC4s.
The cross-connect capacity of the TCS module must be correctly configured on NMS. Or else there
would be a board type mismatch alarm on NMS, CSEP board cannot run normally, and furthermore all the
service will be interrupted.
(FPGA and software of OL16F board should be upgraded to Version 2.00 when CSEP+TCS64Z is
used in ZXMP S385.)

Chapter 3 Schematic Diagram and

Working Principles
3.1 Software Flow Chart
CSEP board is first booted via the boot program and then loads the main program. After the program
is successfully loaded, the application program runs. The board downloads FPGA program, performs
initialization and begins chip self-test and board address detection. Both the red indicator and the green
indicator quickly flash and the yellow indicator is off. This process continues till the board waits for and
receives the key configuration data. The main program flow chart is given as follows:
Figure 3.1 CSEP software chart
3.2 Schematic Diagram and Working Principles

Figure 3.2 Functional blocks of the CSEP board
Cross-connect unit of CSEP includes higher-order cross-connect module and HW cross-connect

module, in which higher-order cross-connect is done by the higher-order cross-connect chip PMC5377.
The chip can provide 72 groups of service cross-connect at the rate of 2.5 Gbit/s. HW bus cross-connect is
done by the ZX2074 chip, enabling a cross-connect capacity of 4096*4096 64 kbit/s.
1. High-speed aggregate line signal flow: High-speed 2.5 Gbit/s aggregate line service buses
connected to the backplane and the extended slots of the lower-order cross-connect board  Service
cross-connect processing chip  Backplane and extended slots of the lower-order cross-connect board 
High-speed aggregate line service processing boards.
2. Low-speed HW signal flow: 16 low-speed HW service buses connected to the backplane  HW

service cross-connect processing chip  Backplane Service boards.
After the CPU is powered on and initialized, it communicates with NCP via HDLC communication
interface to get property configuration and other configuration information, and then initializes the cross-
connect matrix. As can be seen from the above functional block diagram, the signals from the aggregate
line boards and signals from the TCS board enter the STM-4 frame higher-order cross-connect matrix. The
data for lower-order cross-connect processing are sent to TCS board for processing and the other data are
sent back after cross-connect processing to the aggregate lines. The APS protocol processor executes
protection switching according to the alarms of the optical interface boards and K1 and K2 bytes. For the
subnet connection protection involving hybrid service in multiple directions, the CPU of CSEP board
implements protection switching according to the alarms detected by the CSEP board itself. For path
protection of the lower-order cross-connect module, the protection will be completed by interface board if
2 Mbit/s, 34 Mbit/s and 45 Mbit/s services are added/dropped at this point or completed by CSE P board if
these services are not added/dropped at this point.

3.3 Clock Unit Diagram and Working Principles
Figure 3.3 Clock unit diagram
Clock unit can make the local OCXO synchronize with line reference clock or external reference
clock by using second order DPLL which is based on micro processor. It makes the whole network
synchronized by selecting the highest priority reference clock according to SSM algorithm. In the standby
state, clock unit trace the clock of main clock unit and it can make the master and slave clock switch
between each other with no phase difference. Clock unit generates system frame head, HW bus clock and
frame head. At the same time it provides system clock, system frame head, HW bus clock and HW bus
frame head to each board of system.
Note 1: In figure 2.3 there are compatible design on both SCI and CSEP boards for 2.048 MHz VCXO.
Note 2: MCU function can be divided into two parts. The first one is MPC852T enabling communication
with the outside, control and alarm monitoring. The second part is 8051 finishing the phase locked loop
control function.

Chapter 4 Board Functions

CSEP board includes cross-connect unit and clock unit, and it provides the following functions for ZXMP
S385:
1. Implements service inter-connection form multiple directions and implements service cross-
connect and overhead cross-connect.
2. Provides 72*72 STM-16/STM-48 services cross-connect capacity.
3. Provides 4096*4096 64 Kbit/s overhead cross-connect capacity.
4. The backplane supports adaptive rates 2.5 Gbit/s and 622 Mbit/s and it gives four buses to each
slot.
5. Supports line side loop-back of the cross-connect board (for optical board, it would be AU level
straight through, no matter line side loop-back or terminal side loop-back in NMS).
6. For idle channels, the board sends AU-AIS signal for the AU protected as SNC (I) or SNC (I) +SD
if there is no incoming timeslot. It sends HP-UNEQ for AU protected as SNC (N) if there is no
incoming timeslot.
7. Provides the clock and frame head of system to SDH equipment.
8. Provides HW bus clock and frame head to each unit of SDH equipment.
9. The board has four work modes through the phase locked circuit control indicator by software: a.
fast start mode; b. lock mode; c. hold mode; d. free running mode.
10. Provides four external 2.048 MHz timing reference and 28 lines of 8 KHz timing reference. The
board allows switching protection of reference clock source according to alarm information of
various clock sources and the SSM message.
11. Synchronizes the whole network through SSM.
12. CSEP board can either work in the dual-board hot backup mode or work independently for the
reliability of system synchronization and timing. In the hot backup mode, two CSEP board
output system clock and frame head to backplane at the same time. Master or slave state of the
two boards is decided by completed switch mechanism. Moreover, other boards of the system
select the master CSEP board as the state information of the two CSEP boards.
13. CSEP board can switch to another one less than 50ms.
14. Clock unit includes CSEP and SCI, and 2.048 Mbit/s (75 ohm/120 ohm) or 2 MHz input/output
interface is provided by SCIB or SCIH.
15. SCI board provides POWER2, POWER2_ALM, ALARM_SHOW, ALARM_IN&UC, BITS, F1

interfaces. All signals are connected to the backplane by hardware connection lines.
16. FPGA and main software can be upgraded remotely.

Notes: Any kind of reset of CSEP board would have an influence to services transmitting over this
CSEP board.

Chapter 5 Board Panel Indicators and

Controls
Figure 4.1 Panel indicators and buttons
1. Indicators
2. Reset button (RST)
3. Micro switches
Green indicator lights show the running state of the CSEP board. In initialization stage of the board,
the yellow indicator light denotes initialization failure of application program and FPGA, while the red
indicator light denotes initialization failure of RAM, flash and other hardware. When the board is running,
the yellow and red indicators denote board alarms and switching state.
Table 4.1 Indicator state description

Indicator name Indicator color Description
NOM Green Flashes regularly when the board works

normally.
ALM1 Yellow Constantly on when minor alarm takes place and

turns off when the alarm disappears.
ALM2 Red Constantly on when major alarm takes place and

turns off when the alarm disappears.
CK_MS Green Constantly on when the board is in active state.
CKS1 Green Clock running state indicator
CKS2 Green Clock running state indicator
Table 4-2 describes the operation of clock running state indicators.
Table 4.2 Clock running state description
CKS1 CKS2 Clock running state
ON ON Lock mode
ON OFF Hold mode
OFF ON Fast start mode
OFF OFF Free running mode
Note: There are two micro switches on the front panel of CSEP board. The micro switches should be
tightened after the installation of CSEP board or else an alarm will take place.

Chapter 6 Board Running States

CSEP board experiences the following process from power-on to normal operation.
Figure 5.1 Board operation flow
1. Board power-on
After being powered on, the green, yellow and red indicators on the board panel turn on for one
second and then turn off all together to show all indicators work normally.

2. RAM self-test
The board enters the RAM self-test process. All the green, yellow and red indicators on the board
panel flash regularly at 1.5 Hz, indicating that the board is in the memory self-test state. If the
memory self-testing fails, the red indicator will regularly flash at 1.5 Hz while the yellow indicator
and the green indicator will be off. Then the software will not clear the watchdog but wait for the
board to be reset. If the board reset is implemented by invoking the BSP reset function, the board
will flash 10 times (10 times on and 10 times off) and then invoke the reset function
3. Application program loading
After the RAM completes self-test, the board starts to load the application program (the board will
load the program from its own storage area if it has any available program or get the program from
the NCP if the board needs to be upgraded). Both the green indicator and the red indicators will
regularly flash at 1.5 Hz while the yellow indicator will be off. If the board cannot find any
available program or FPGA file for loading, the yellow indicator will flash regularly at 1.5 Hz
while the red indicator and the green indicator will be off. The software will not clear the watchdog
but wait for the board to be reset. If errors occur during Flash erasure in the loading process, the
red indicator will flash regularly at 1.5 Hz while the yellow indicator and the green indicator will
be off. The software will not clear the watchdog but wait for the board to be reset.
4. FPGA program loading
After the program is successfully loaded, the application program runs. The board downloads the
FPGA program, performs initialization and begins chip self-test and board address detection. Both
the red indicator and the green indicator regularly flash at 1.5 Hz and the yellow indicator is off.
If the board fails to download the FPGA, the yellow indicator will regularly flash at 1.5 Hz while
the green indicator and the red indicator will be off. Then the software will not clear the watchdog
but wait for the board to be reset. If the board reset is implemented by invoking the BSP reset
function, the board will flash 10 times (10 times on and 10 times off) and then invoke the reset
function.
If the chip self-testing fails, the red indicator will regularly flash at 1.5 Hz while the green
indicator and the yellow indicator will be off. Then the software will not clear the watchdog but
wait for the board to be reset. If the board reset is implemented by invoking the BSP reset function,
the board will flash 10 times (10 times on and 10 times off) and then invoke the reset function.
If the board address detection fails, the green indicator will be off while both the red indicator and
the yellow indicator will regularly flash at 1.5 Hz. Then the software will not clear the watchdog
but wait for the board to be reset. If the board reset is implemented by invoking the BSP reset
function, the board will flash 10 times (10 times on and 10 times off) and then invoke the reset
function.
5. Key configuration
The board enters the state of waiting for the key configuration after it is initialized. The green
indicator will turn on while the yellow indicator and the red indicator will be both off. If the

board does not receive any configuration information within 10 seconds, it will report an alarm. If
the board receives the property configuration command, the yellow indicator will be on. If the
board fails to receive the complete information within 30 seconds, it will repeat the above
process. After the board receives the complete key configuration command, the yellow indicator
will be off.
6. Board preheat
After receiving the complete key configuration command, the board enters the preheating stage
that will last two minutes. At this time, the board detects alarm information but will not report
any alarm, will not turn on the alarm indicators and will not perform switchover. It will wait for
the other boards to enter the normal working state. The green indicator will regularly flash at 1.5
Hz, the yellow and red indicators will be off and the other indicators (such as the optical
receiving/transmitting indicator of the optical board) will normally operate without alarms. Then
the board processes the NM commands.
7. Normal operation of the board
When the board finishes the preheating state, it enters the normal running stage. The green
indicator will regularly flash at 0.5 Hz and the board starts to detect alarms. If it has not yet
received the indicator control configuration rules from the NMS, the board will generate alarms
according to the default state.

Chapter 7 Board Reset

CSEP board supports the following three reset modes:
1. Reset via the RST button
The reset is independent of the S interface communication or the normal running of the board
software. When the RST button is pressed, the MAX706 chip outputs a reset signal (RST) to the
CPU to reset the whole CPU. After the reset, the board is able to normally self-test and run and can
enter the normal working state within four minutes. If two cross-connect boards are in position and
the NMS does not set forced selection of a cross-connect board, resetting a cross-connect board will
switch the service buses and overhead buses of the service boards to the other cross-connect board. If
we reset the cross-connect board forcibly selected by the NMS, the services will not switch over but
will be interrupted during the reset. The services will not be recovered till the cross-connect board
forcibly selected resumes normal running.
2. Hard reset via the NMS
The reset is independent of the S interface communication or the normal running of the board
software but is implemented by the hardware connections from the NCP to the boards. After the
reset, the board is able to normally self-test and run and can enter the normal working state within
four minutes. If two cross-connect boards are in position and the NMS does not set forced selection
of a cross-connect board, resetting a cross-connect board will switch the service buses and overhead
buses of the service boards to the other cross-connect board. If we reset a cross-connect board
forcibly selected by the NMS, the services will not switch over but will be interrupted during the
reset. The services will not be recovered till the cross-connect board forcibly selected resumes normal
running.
3. Soft reset via the NMS
Soft reset can be divided into CPU, IC and CPU+IC three levels. The CSEP board is the same with
other boards in terms of whether downloading FPGA. Actually FPGA is not downloaded when CPU
and IC are reset; however FPGA is downloaded when CPU+IC is downloaded.
This reset mode is implemented via the S interface command. Upon receipt of the S interface command,
the software stops the software watchdog and makes the software restart. After the reset, the board is able
to normally self-test and run and can enter the normal working state within four minutes. I f two cross-
connect boards are in position and the NMS does not set forced selection of clock board, service buses,
overhead buses and clock buses of service boards will be switched to the standby cross-connect board. If
the NMS has set forced selection of clock board, the services will not switch over but will be interrupted
during the reset.
Exercise

Choice Questions
1. CSEP board includes ( ), ( ) and ( ) function modules.
Answer: service cross-connect function module, overhead cross-connect function module, clock function
module.
2. The clock module of the CSEP board can provide ( ) clock directions for ZXMP S385.
Answer: 28
3. Higher-order cross-connect capacity of CSEP board is ( ), it supports ( ) TCS at most.
Answer: 180 Gbit/s 256*256 VC4s
4. When CSEP board is used in ZXMP S385 system, the back board bus of the system supports two kinds
of rate ( ) and ( ), and ( ) buses for each slot.
Answer: 2.5 Gbit/s 622 Mbit/s 4
5. Two CSEP boards run in the ( ) protection mode.
Answer: 1+1
6. CSEP board provides ( ) channels of external clock input.
A. 2
B. 4
C. 6
D. 8
Answer: B
7. For ZXMP S385, CSEP board can be install indicator on slot ( )
A. 6
B. 7
C.8
D.9
Answer: CD
8. Please select the process the CSEP board experiences from power on until normal operation?
（1）Board power on
(2) RAM self-testing
(3) Load application program
(4) Download FPGA program
(5) Key configuration

(6) Preheating stage
(7) Normal operation
Essay Questions
1. List main functions of CSEP board. (At least 5)
(1) Implements service inter-connection form multiple directions and implements service cross-
connect and overhead cross-connect.
(2) Provides 72*72 STM-16/STM-48 service cross-connect capacity.
(3) Provides 4096*4096 64 Kbit/s overhead cross-connect capacity.
(4) The backplane supports adaptive rates 2.5 Gbit/s and 622 Mbit/s and it gives four buses to each
slot.
(5) Supports line side loop-back of the cross-connect board (for optical board, it would be AU level
straight through, no matter line side loop-back or terminal side loop-back in NMS).
(6) For idle channels, the board sends AU-AIS signal for the AU protected as SNC (I) or SNC (I)
+SD if there is no incoming timeslot. It sends HP-UNEQ for AU protected as SNC (N) if there is no
incoming timeslot.
(7) Provides the clock and frame head of system to SDH equipment.
(8) Provides HW bus clock and frame head to each unit of SDH equipment.
(9) The board has four work modes through the phase locked circuit control indicator by software: a.
fast start mode; b. lock mode; c. hold mode; d. free running mode.
(10) Provides four external 2.048 MHz timing reference and 28 lines of 8 KHz timing reference. The
board allows switching protection of reference clock source according to alarm information of various
clock sources and the SSM message.
(11) Synchronizes the whole network through SSM.
(12) CSEP board can either work in the dual-board hot backup mode or work independently for the
reliability of system synchronization and timing. In the hot backup mode, two CSEP boards output
system clock and frame head to backplane at the same time. Master or slave state of the two boards is
decided by completed switch mechanism. Moreover, other boards of the system select the master
CSEP board as the state information of the two CSEP boards.
(13) CSEP board can switch to another one in less than 50ms.
(14) Clock unit includes CSEP and SCI, and 2.048 Mbit/s (75 ohm/120 ohm) or 2 MHz input/output
interface is provided by SCIB or SCIH.
(15) SCI board provides POWER2, POWER2_ALM, ALARM_SHOW, ALARM_IN&UC, BITS, F1

interfaces. All signals are connected to the backplane by hardware connection lines.
(16) FPGA and main software can be upgraded remotely.
2. Please list all reset modes of the CSEP board and tell the differences between them.

CSEP board supports the following three reset modes: Reset via the RST button, hard reset via the NMS
and soft reset via the NMS.
(1) RST reset is independent of the S interface communication or the normal running of the board
software. The board outputs reset signal to CPU by switching on/off the RST button to reset the whole
CPU.
(2) The hard reset is independent of the S interface communication or the normal running of the board
software but is implemented by the hardware connections from the NCP to the boards.
(3) Soft reset can be divided into CPU, IC and CPU+IC three levels. For downloading FPGA or not it is
the same to the other boards. Actually reset CPU, IC would not download FPGA, however reset CPU+IC
the board would download FPGA. This reset mode is implemented via the S interface command. Upon
receipt of the S interface command, the software stops the software watchdog and makes the software
restart.
After any kind of reset, the board is able to normally self-test and run and can enter the normal working
state within four minutes. If there are two cross-connect boards and no forcibly clock selection has been
down by NMS, reset board would raise switch events. Service boards buses, overhead buses, clock buses
would select slave cross-connect board. For the forcibly selected board reset, during the reset time master
one would not switch and service will shut down until CSEP board runs normally.

ZXMP S385 CSEP Board Maintenance Manual-Board Overview

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

ZXMP S385 CSEP Board Maintenance Manual-Board Overview

Uploaded by

Copyright:

Available Formats

ZXMP S385 CSEP Board Maintenance Manual－Board Overview

For internal use only▲