Assessment 1

Reg No: 21BIT0519

Name: Soham L Patil
Slot: L15+L16
Course: BITE202P (Digital Logic and Microprocessors)
 Question 1:

• Aim:

To verify the truth table of basic logic gates

• Truth table:

X Y AND OR NOT(X) NOR NAND XOR XNOR

0 0 0 0 1 1 1 0 1
0 1 0 1 1 0 1 1 0
1 0 0 1 0 0 1 1 0
1 1 1 1 0 0 0 0 1
• Logic Gates:
a) AND

b) OR
c) NOT

d) NOR

e) NAND
f) XOR

g) XNOR
• Schematic:

• Result:
The logical circuits are simulated using MULTISIM and the truth table is verified
 Question 2

• Aim:
To verify the equations given in the question.
• Truth Table:
a) XY+YZ+Y’Z=XY+Z

X Y Z XY+YZ+Y’Z XY+Z
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 1 1
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

b) XY+YZ+YZ’=Y

X Y Z XY+YZ+YZ’ Y
0 0 0 0 0
0 0 1 0 0
0 1 0 1 1
0 1 1 1 1
1 0 0 0 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 1
 c) XY+X’Z+YZ=XY+X’Z

X Y Z XY+X’Z+YZ XY+X’Z
0 0 0 0 0
0 0 1 1 1
0 1 0 0 • 0
0 1 1 1 1
1 0 0 0 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 1

d) PQ+Q’R+WPRQ=PQ+Q’R

P Q R W PQ+Q’R+WPRQ PQ+Q’R
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 1 1
0 0 1 1 1 1
0 1 0 0 0 0
0 1 0 1 0 0
0 1 1 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 0 1 0 0
1 0 1 0 1 1
1 0 1 1 1 1
1 1 0 0 1 1
1 1 0 1 1 1
1 1 1 0 1 1
1 1 1 1 1 1

• Circuits:
a)
b) XY+YZ+YZ’=Y

c) XY+X’Z+YZ=XY+X’Z

d) PQ+Q’R+WPRQ=PQ+Q’R
 Question 3

• Aim:
To implement NAND and NOR gates( Universal Gates) in a logic circuit
• Simplification:

• K-Map:
• Table:

A B C D F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1
• Digital Circuits:
• Schematic:

• Result:
The NAND and NOR gate can be used as universal gates and the truth table of the expression
is verified.
 Question 4

Half Adder

• Aim:
To design a half adder circuit in multisim and verify its truth table.
• Truth table:

X Y S Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
• K-Map:

• Digital Circuit:
• Schematic:

• Result:
The circuit for the half adder is simulated using multisim and the truth is verified.

Half Subtractor

• Aim:
To design a half subtractor circuit in multisim and verify its truth table.
• Truth Table:

X Y
0 0
0 1
1 0
1 1
D Bout
0 0
1 1
1 0
0 0
• K-Map:

• Digital Circuit:

• Schematic:
 Full Adder

• Aim:
To design a circuit for a full adder in multisim and verify it with the truth table.
• Truth Table:

X Y Cin
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
• K-Map:
S Cout
0 0 0
1 1 0
0 1 0
1 0 1
0 1 0
1 0 1
0 0 1
1 1 1

• Digital circuit:
• Schematic:

Full Subtractor
• Aim:
To design a full subtractor in multisim and verify it using the truth table
• Truth Table:

X Y Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
• K-Map:
• Digital Circuit:

• Schematic:
 Question 5

• Aim:
To implement full adders to perform a 4-bit addition and subtraction using a circuit in
multisim.
• Calculation:
• Schematic:
 Question 6

• Aim:
To implement the given function using 8x1 Multiplier and verify the truth table.
• Truth Table:

A B C D F
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
• K-Map:
• Schematic:

• Result:
An 8x1 Multiplier can be used to implement Boolean function
 Question 7

• Aim:
To design a BCD to Excess-3 code converter
• Truth table:

A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X
• K-Map:
• Digital logic:

• Schematics:

• Result:
The circuit for a BCD to Excess-3 converter is designed and verified using multisim.
 Question 8

• Aim:
To design a seven segment decoder with input ABCD that converts decimal digit in BCD to an
appropriate code for the selection of segments in an indicator.
• Truth Table:

A B C D a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 0 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 0 0 1 1
1 0 1 0 x x x x x x x
1 0 1 1 x x x x x x x
1 1 0 0 x x x x x x x
1 1 0 1 x x x x x x x
1 1 1 0 x x x x x x x
1 1 1 1 x x x x x x x
• Schematic:

• Result:
A digital circuit for a BCD to 7 segment is designed in multisim and verified.
 Question 9

• Aim:
To design a 3-bit magnitude comparator in multisim and verify it with its truth table.
• Logic and Circuit:
• Schematics:

• Result:
3-bit magnitude comparator is designed in multisim and verified using examples.
 Question 10

• Aim:
To find the expression and design a digital circuit for the given condition.
• Truth Table:

C S D B W
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
• K-Map:
• Digital Logic:

• Schematics:

• Result:
The circuit and digital logic for the given problem is created using multisim.