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April 2009
FSFM260N / FSFM300N
Green-Mode Fairchild Power Switch (FPS™)
Features Description
! Internal Avalanche-Rugged SenseFET The FSFM260/300 is an integrated Pulse Width
! Advanced Burst-Mode Operation Consumes Under Modulator (PWM) and SenseFET specifically designed
1W at 240VAC and 0.5W Load for high-performance offline Switch Mode Power
! Precision Fixed Operating Frequency: 67kHz
Supplies (SMPS) with minimal external components.
! Internal Startup Circuit This device is an integrated high-voltage power-
! Over-Voltage Protection (OVP) switching regulator that combines an avalanche-rugged
SenseFET with a current-mode PWM control block. The
! Overload Protection (OLP)
PWM controller includes an integrated fixed-frequency
! Internal Thermal Shutdown Function (TSD) oscillator, under-voltage lockout, leading-edge blanking
! Abnormal Over-Current Protection (AOCP) (LEB), optimized gate driver, internal soft-start,
! Auto-Restart Mode temperature-compensated precise-current sources for a
! Under-Voltage Lockout (UVLO) with Hysteresis loop compensation, and self-protection circuitry.
! Low Operating Current: 2.5mA Compared with discrete MOSFET and PWM controller
solutions, it can reduce total cost, component count, size,
! Built-in Soft-Start: 15ms
and weight while simultaneously increasing efficiency,
productivity, and system reliability. This device is a basic
platform for cost-effective designs of flyback converters.
Applications
! Power Supply for LCD TV and Monitor, VCR, SVR,
STB, DVD, and DVD Recorder
! Adapter
Related Resources
Visit: http://www.fairchildsemi.com/apnotes/ for:
! AN-4134: Design Guidelines for Offline Forward
Converters Using Fairchild Power Switch (FPS™)
! AN-4137: Design Guidelines for Offline Flyback
Converters Using Fairchild Power Switch (FPS™)
! AN-4140: Transformer Design Consideration for
Offline Flyback Converters Using Fairchild Power
Switch (FPS™)
! AN-4141: Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback Applications
! AN-4145: Electromagnetic Compatibility for Power
Converters
! AN-4147: Design Guidelines for RCD Snubber of
Flyback Converters
! AN-4148: Audible Noise Reduction Techniques for
Fairchild Power Switch (FPS™) Applications
Notes:
1. The junction temperature can limit the maximum output power.
2. 230VAC or 100/115VAC with doubler.
3. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient temperature.
4. Maximum practical continuous power in an open-frame design at 50°C ambient.
5. Eco status for both the FSFM2600N and FSFM300NS is RoHS.
VO
AC
IN
VSTR
Drain
ILIM
PWM
GND
FB V CC
FSFM260 Rev. 00
VCC
OSC Vref
VBURL/VBURH VCC good
VCC VCC 8V/12V
Idelay IFB
FB 2.5R Normal
PWM
S Q
3
Burst Soft- LEB
R Gate
Start R Q
250ns driver
ILIM
4
VSD
VCC 1
S Q VOCP
VOVP LPF GND
R Q
TSD
VCC good
FSFM260 Rev.00
GND Drain
FB Drain
ILIM VSTR
FSFM260 Rev.1.0.0
Pin Definitions
Pin # Name Description
1 GND Ground. This pin is the control ground and the SenseFET source.
Power Supply. This pin is the positive supply input, providing internal operating current for
2 VCC
both startup and steady-state operation.
Feedback. This pin is internally connected to the inverting input of the PWM comparator. The
collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should
3 FB
be placed between this pin and GND. If the voltage of this pin reaches 6V, the overload pro-
tection triggers, which shuts down the FPS.
Peak Current Limit. Adjusts the peak current limit of the Sense FET. The feedback 0.9mA
4 ILIM current source is diverted to the parallel combination of an internal 2.8kΩ resistor and any ex-
ternal resistor to GND on this pin to determine the peak current limit.
Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link. At
startup, the internal high-voltage current source supplies internal bias and charges the exter-
5 VSTR
nal capacitor connected to the VCC pin. Once VCC reaches 12V, the internal current source is
disabled. It is not recommended to connect VSTR and drain together.
6,7,8 Drain SenseFET Drain. High-voltage power SenseFET drain connection.
Thermal Impedance
TA = 25°C unless otherwise specified.
(10) °
θJC Junction-to-Case Thermal Resistance 8-DIP 20 C/W
ΨJT Junction-to-Top Thermal Resistance(11) 35 °C/W
Notes:
9. Free standing with no heat-sink under natural convection.
10. Infinite cooling condition - refer to the SEMI G30-88.
11. Measured on the package top surface.
Notes:
12. Pulse test: pulse width ≤ 300µs, duty ≤ 2%.
13. Guaranteed by design; not tested in production.
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [°C] Temperature [°C]
Figure 4. Operating Supply Current (IOP) vs. TA Figure 5. UVLO Start Threshold Voltage
(VSTART) vs. TA
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [°C] Temperature [°C]
Figure 6. UVLO Stop Threshold Voltage Figure 7. Startup Charging Current (ICH) vs. TA
(VSTOP) vs. TA
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [°C] Temperature [°C]
Figure 8. Switching Frequency (fOSC) vs. TA Figure 9. Maximum Duty Cycle (DMAX) vs. TA
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [°C] Temperature [°C]
Figure 10. Over-Voltage Protection (VOVP) vs. TA Figure 11. Feedback Source Current (IFB) vs. TA
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [°C] Temperature [°C]
Figure 12. Shutdown Delay Current (IDELAY) vs. TA Figure 13. Burst-Mode HIGH Threshold Voltage
(VBURH) vs. TA
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [°C] Temperature [°C]
Figure 14. Burst-Mode LOW Threshold Voltage Figure 15. Peak Current Limit (ILIMIT) vs. TA
(VBURL) vs. TA
VO Vfb SenseFET
3 OSC
FOD817A
D1 D2
VDC CB 2.5R
+ Gate
Vfb* R driver
CVcc KA431 -
OLP Rsense
VSD
VCC Vstr
2 5 FSFM260 Rev: 00
Istart
Figure 17. Pulse Width Modulation (PWM) Circuit
2.2 Leading-Edge Blanking (LEB): At the instant the
Vref
internal SenseFET is turned on, a high-current spike
8V/12V VCC good
occurs through the SenseFET, caused by primary-side
Internal capacitance and secondary-side rectifier reverse
Bias recovery. Excessive voltage across the RSENSE resistor
FSFM260 Rev: 00
would lead to incorrect feedback operation in the current-
mode PWM control. To counter this effect, the FSFM260/
Figure 16. Internal Startup Circuit 300 employs a leading edge blanking (LEB) circuit. This
circuit inhibits the PWM comparator for a short time
2. Feedback Control: FSFM260/300 employs current- (tLEB) after the SenseFET is turned on.
mode control, as shown in Figure 17. An opto-coupler
(such as the FOD817A) and shunt regulator (such as the 2.3 Constant Power Limit Circuit: Due to the circuit
KA431) are typically used to implement the feedback delay of FPS, the pulse-by-pulse limit current increases
network. Comparing the feedback voltage with the a little bit when the input voltage increases. This means
voltage across the RSENSE resistor makes it possible to unwanted excessive power is delivered to the secondary
control the switching duty cycle. When the reference pin side. To compensate, the auxiliary power compensation
voltage of the shunt regulator exceeds the internal network in Figure 18 can be used. RLIM can adjust pulse-
reference voltage of 2.5V, the optocoupler LED current by-pulse current by absorbing internal current source
increases, pulling down the feedback voltage and (IFB: typical value is 0.9mA) depending on the ratio
reducing the duty cycle. This typically occurs when the between resistors. With the suggested compensation
input voltage is increased or the output load is circuit, additional current from IFB is absorbed more
decreased. proportionally to the input voltage (VDC) and achieves
2.1 Pulse-by-Pulse Current Limit: Because current- constant power in wide input range. Choose RLIM for
mode control is employed, the peak current through the proper current to the application, then check the pulse-
SenseFET is determined by the inverting input of the by-pulse current difference between minimum and
PWM comparator (VFB*), as shown in Figure 17. When maximum input voltage. To eliminate the difference (to
the current through the opto-transistor is zero and the gain constant power), Ry can be calculated by:
current limit pin (#4) is left floating, the feedback current
Na
source (IFB) of 0.9mA flows only through the internal Ilim_spec ×Vdc ×
Np
resistor (R+2.5R=2.8k). In this case, the cathode voltage Ry ≅ (3)
of diode D2 and the peak drain current have maximum Ifb × ΔIlim_comp
t
2.5V
Normal Fault Normal
FSFM260 Rev: 00 operation situation operation
T12= Cfb*(6.0-2.5)/Idelay
Figure 19. Auto Restart Operation
T1 T2 t
Vds
OSC
2.5R S Q
Gate
LEB R Q
driver
R time
Switching Switching
disabled disabled
FSFM260 Rev: 00 T1 T2 T3 T4
Features
! Average efficiency of 25%, 50%, 75%, and 100% load conditions is higher than 80% at universal input
! Low standby mode power consumption (<1W at 230VAC input and 0.5W load)
! Enhanced system reliability through various protection functions
! Internal soft-start (15ms)
1. Schematic
L201
T1 5 H
EER3016
14V, 1.4A
10
1
C201 C202
R103 C104 1000 F 1000 F
R102 51k 3.3nF 25V 25V
2 6
75k 1W 630V
D101
C103 1N4007
100 F 3
2 400V
BD101
2KBP06M FSFM300N
5
1 3 VSTR 6,7,8
Drain
4 R105 C106 C107 L202
D202
ILIM 100 100nF 47 F 5 H
MBRF1060
0.5W 50V
3 FB VCC 5V, 2A
4 2 4 7
GND D102 C204
C105 C203
C102 1 UF 4004 1000 F
33nF 2200 F
150nF 10V
100V 10V
275VAC 6
5
ZD101
1N4745A
C301
4.7nF
LF101 Y2
R108
30mH
N.C
R201
1k
R101 R204
1M 8k
1W R202
R203 C205
1.2k 47nF
18k
IC301
FOD817C
IC201
RT1 C101 KA431
NTC 150nF F1 R205
5D-9 275VAC FUSE 8k
250V
2A
1
EER3016 Top
10
N14V
Np/2 2 1
9 GND
Np/2 2 Na 4 5
N5V 7 6
3 8 N5V 8 6
Np/2 N5V
8
7 N14V 10
Na 4 N5V
2
Np/2
3
5 6
Bottom
3. Winding Specification
4. Electrical Characteristics
9.83
9.00
6.67
6.096
8.255
7.61
0.33 MIN
(0.56) 3.60
3.00 0.356
2.54 0.20
0.56
0.355
9.957
1.65 7.87
1.27
7.62
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.