Schematic - Aap21 La-C921p Rev 1.0 A00

For DELL Confidential
A B C D E
1 1
Compal Confidential
ia l
n t
2
AAP11/AAP21
id e 2
Schematic Document
n f
SKL-H paltform with Nvidia N16E-GS/GT/GX
C o
3 L
Rev: 1.0(A00) PVT
L
2015/07/21 3
@ : Nopop Component
E
EMI@ /@EMI@ : EMI pop/unpop part
D
ESD@ /@ESD@ : ESD pop/unpop part
DIS@ : Discrete Part
N16EGS@:N16E-GS(2G)
N16EGT@:N16E-GT(3G)
r
RF@ /@RF@ : RF pop/unpop part
o
N16EGX@:N16E-GX(4G)
2G@:2G VRAM
4
AOAC@ : Intel AOAC
DS3/NODS3: deepS3
TBT@: ThunderBolt
F
CONN@ : Connector Component 3G@:3G VRAM
4G@:4G VRAM
DAX
DAZ18F00100
PCB
PCB 18F LA-B752P REV0 M/B 8

R1@
DAX
DAZ18F00101
PCB
PCB 18F LA-B752P REV0 M/B 8

R3@
4
PD@: Power Delivery Security Classification Compal Secret Data Compal Electronics, Inc.
12L
Issued Date 2015/01/30 Deciphered Date 2016/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C912P
Date: Wednesday, July 22, 2015 Sheet 1 of 78
A B C D E

A B C D E
SKL+NV Block Diagram

eDP panel eDP 1.3
Page25
1
FFS 1
DP 1.2 (DDI1) KXCNL-1010

ThunderBolt DP 1.2 (DDI2)
Intel
Alpine Ridge-SP SKYLAKE-H
PCI-E x4(port1~4)
l
CIO/USB3.1 Memory Bus Dual Channel
USB3.1 Page58~59
BGA CPU 1.2V DDR4 1866/2133MHz DDR4-SODIMM x2
TypeC Page14~15
1440 Pins
ia
Page60
PCI-E(GEN3)x8
TPS65982 50W,65,85W dGPU port0~port7
t
USB PD Page60
I2C/USB2 nVIDIA
4pcs GDDR5 128bit
6pcs GDDR5 192bit
n
Page27
HDMI 8pcs GDDR5 256bit
HDMI 2.0 Page7~13
connector
e
Page46~55
DMI x 4
id
PCI-E(GEN3)x4
2 port8~port11 SATA3.0 port1 2
HDD connector
f
Page36
Caldera USB3.0 port5 USB2.0 port4
n
connector AlienFX / ELC , C8051F383 Page37
USB2.0 port3
Page41
o
USB2.0 port6
Touch screen Page25
Page30 PCI-E port5 USB2.0 port7

RJ45 LAN(Gigabit)
C
Digital camera(with digital MIC)
connector Killer E2400
Page30
Intel
SKYLAKE-PCH USB3.0 port1
USB2.0 port1 USB connector 1 , Right side Page34
3 in 1 Page31 Card reader PCI-E port7
BGA
L
Card slot RTS5227Page31
837 Pins
NGFF (M.2) PCI-E port 9~12
L
SSD 1 Page29 SATA3.0 port 0,1 USB3.0 port3 USB connector 3 , Left side
USB2.0 port2
3
USB power share Page35 3
E
NGFF (M.2) PCI-E port 15~16
USB3.0 port4
SSD 2 Page29 SATA3.0 port 2,3
USB2.0 port9 USB connector 4 , Lift side Page35
D
HP/MIC Global headset
combo JACK Page32
r
Audio codec
HD Audio Creative HP/MIC Retaskable
combo JACK
o
Sound Core3D-EX Page32
PCI-E port6
NGFF (M.2)
WLAN+BT USB2.0 port6 Page32 TI TPA3111 Sub-woofer
4
DC in
Battery
3V/5V
System
1.2V
1.00V
2.5V
CPU
Vcore
dGPU
Core
Charger
dGPU
1.35V
F SPI ROM
128MbitPage19
SPI
Int. KBD
LPC Bus
ENE KB9022
Page16~22
Touch pad
PS2/SMBus
TI TPA3131D2
Speaker
Page32
Daughter Board
17" only
ENE KC3810 Page43

Page43
Security Classification Compal Secret Data Compal Electronics, Inc.
Block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
A B C D E

A B C D E
Compal Confidential
1 1
M/B
FFC LS-9335P
POWER BUTTON/B
FFC
ia l Camera
t
Touch Pad on/off SW
eDP Panel
Coaxial/Wire Combo
n
Led x 2
2 LS-9336P
FFC
id e Daughter/B
Sub-woofer Amplifier
USB3.0
USB3.0
2
f
INDICATOR/B
Headphone combo JACK
Led-HDD
n
Led-Wireless
Wire-Set Headphone combo JACK
Led-CapsLock Lid
C o
L
KSI/KSO Backlight Wire
E Keyboard
L LOGO /B
Led x 2
3
r D Wire
Hot Bar Hot Bar
Wire
Hot Bar
Wire
o
Alien Slits-R Light/B Alien head badge/B Alien Slits-L Light/B
F
Led x 2 Led x 2 Led x 2
4 4

Block Diagram
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D E

A
USB3.0
Board ID Table for AD channel
Vcc 3.3V +/- 1% Port1 Right side1
Ra 100K +/- 1%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Port2 Right side2
0 0 0.000V 0.000V 0.300V 0x00 - 0x0B
1 12K +/- 1% 0.347V 0.354V 0.360V 0x0C - 0x1C Port3 Left side 1
2 15K +/- 1% 0.423V 0.430V 0.438V 0x1D - 0x26
3 20K +/- 1% 0.541V 0.550V 0.559V 0x27 - 0x30 Port4
4 27K +/- 1% 0.691V 0.702V 0.713V 0x31 - 0x3B NVIDIA
5 33K +/- 1% 0.807V 0.819V 0.831V 0x3C - 0x46 Graphic Port5 Caldera
l
6 43K +/- 1% 0.978V 0.992V 1.006V 0x47 - 0x54
7 56K +/- 1% 1.169V 1.185V 1.200V 0x55 - 0x64 Port6 Left side 2
ia
8 75K +/- 1% 1.398V 1.414V 1.430V 0x65 - 0x76
9 100K +/- 1% 1.634V 1.650V 1.667V 0x77 - 0x87 USB2.0
t
10 130K +/- 1% 1.849V 1.865V 1.881V 0x88 - 0x96
11 160K +/- 1% 2.015V 2.031V 2.046V 0x97 - 0xA3 Port0 Right side1
n
12 200K +/- 1% 2.185V 2.200V 2.215V 0xA4 - 0xAD
13 240K +/- 1% 2.316V 2.329V 2.343V 0xAE - 0xB7 Port1 Left side 1 (PowerShare)
e
14 270K +/- 1% 2.395V 2.408V 2.421V 0xB8 - 0xC0 AMD
15 330K +/- 1% 2.521V 2.533V 2.544V 0xC1 - 0xC9 Graphic Port2 Caldera
id
16 430K +/- 1% 2.667V 2.677V 2.687V 0xCA - 0xD3
17 560K +/- 1% 2.791V 2.800V 2.808V 0xD4 - 0xDC Port3 ELC
18 750K +/- 1% 2.905V 2.912V 2.919V 0xDD - 0xE6
f
19 NC 3.000V 3.300V 3.300V 0xE7 - 0xFF Port4 BT
Port5 Touch screen
Board ID TABLE
ID PCB Revision
o n BDW Port6
Port7 / 8
Camera
Right side 2 Left side 2
C
1 1
NV AMD PCI EXPRESS

0 10 EVT
1 11 DVT-1 Lane 1
L
2 12 DVT-1.1 TBT connector change to SMD type.
3 13 DVT-2 Lane 2
4 14 DVT-3
L
5 15 Pilot build Lane 3 10/100/1000 LAN
E
Lane 4 M.2 Card WLAN
CLOCK SIGNAL Lane 5 PCIE 4x MUX
r D CLKOUT_PCIE0
CLKOUT_PCIE1
Lane 6
SATA
o
CLKOUT_PCIE2 10/100/1000 LAN SATA0 HDD
F
CLKOUT_PCIE3 M.2 Card WLAN SATA1 NGFF SSD
CLKOUT_PCIE4 dGPU (N16) SATA2 NGFF SSD
CLKOUT_PCIE5 DGPU (Caldera) SATA3

Symbol Note :
: means Digital Ground
: means Analog Ground

Notes list
A

5 4 3 2 1
1K
D
SMBUS Address [0x9a] D
+3VS
1K
AW44 PCH_SMBCLK 253 DIMMA SMBUS Address [A0]
l
BB43 PCH_SMBDATA 254
499
ia
253 DIMMB SMBUS Address [A4]
+3V_PCH
499 254
Skylake AY44
BB39
SML0CLK
SML0DATA
1K
n t
e
1K
+3V_PCH
4 FFS SMBUS Address [1Dh]
id
N-MOS 6
AW42 SML1CLK EC_SMB_CK2
N-MOS
C AW45 SML1CLK EC_SMB_DA2 C
f
5 JTP SMBUS Address [TBD]
6
2.2K
2.2K
+3VS
o 10K
n U2407
Thermal Sensor SMBUS Address [0X9A]
C
+3VS
79 EC_SMB_CK2 10K
80 EC_SMB_DA2 0 ohm
0 ohm
TBTA_I2C_SCL1 B5 UT4 SMBUS Address [0X7]
TBTA_I2C_SDA1 A5 TBT
L
1.8K
+3.3V_GFX_AON
L
1.8K
KBC N-MOS UV1
B
KB9022QD N-MOS
VGA_SMB_CK2 BF3 GPU SMBUS Address [0x9E] B
E
2.2K
VGA_SMB_DA2 BE3
2.2K
+3VALW
77
78
EC_SMB_CK1
EC_SMB_DA1
r D 0 ohm
0 ohm
SCL
SDA
11
10
PU701
POWER
Charger
SMBUS Address [0x12]
o
100 ohm
CPU,C 3 PD1 4 BAT_ALERT 3 PBATT1 SMBUS Address [0x16]
100 ohm
DDR,D 1 6 BATT_PRS 5
F
GPU,DP,HDMI,EDP,V
LAN,L
AUDIO,A
NGFF,N
USB,U
A
CALDERA,M A
HDD,S
ELC,E
FAN,F
TP,T
KBC,K
Security Classification
2015/01/30
Compal Secret Data
2016/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
DC,O THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMBus block diagram
5 4 3 2 1

5 4 3 2 1
+1V_PCH JTAG
RH492 1 2 XDP_PLTRST#
2.2K_0402_5%
+3V_PCH
D D
RH493 1 2 PCH_SYS_PWROK_XDP
2.2K_0402_5%
ia l
t
+VCCSTG
n
RH494 1 2 51_0402_5% XDP_TMS
XDP_TMS <9,18>
RH495 1 2 51_0402_5% XDP_TDI
XDP_TDI <9,18> Connect CPU & PCH
e
RH496 1 @ 2 51_0402_5% XDP_TDO
XDP_TDO <9,18>
id
RH95 1 2 51_0402_5% PCH_JTAG_TCK
PCH_JTAG_TCK <18>
RH498 1 @ 2 51_0402_5% XDP_TCK
XDP_TCK <9,18> Connect CPU & PCH
C C
f
RH497 1 2 51_0402_5% CPU_XDP_TRST#
CPU_XDP_TRST# <9,22>
<18> PCH_ITP_PMODE
<17> PCH_SPI_SI_R
RH479
RH489
1
1
@ 2 0_0402_5%
2 1K_0402_5%
XDP_PLTRST#
o n
C
PCH_SYS_PWROK_XDP +3VS
+3V_PCH_DSW
AAM00 is XDP@
1
1
L
RH5
1K_0402_5%
RH2
2
1K_0402_5%
2
L
RH6 1 @ 2 0_0402_5% RH8 1 @ 2 0_0402_5%
PBTN_OUT# <18,43> SYS_RESET# <18>
0.1U_0402_10V
0.1U_0402_10V
1
1
+VCCIO
CH174
CH175
E
2
2
1
B B
AAM00 is XDP@
RH483
@ 150_0402_5%
2
1 2 AAM00 is XDP@
D
CFG0
RH488 @ 1K_0402_5% CFG0 <9>
o r
A
F A

XDP CONN
5 4 3 2 1

5 4 3 2 1
?O
SKYLAKE_HAL
CPU1C
BGA1440
E25 B25 PEG_GTX_HRX_P[0..7] <46>

D25 PEG_RXP[0] PEG_TXP[0] A25 PEG_GTX_HRX_N[0..7] <46>
PEG_RXN[0] PEG_TXN[0]
PEG_HTX_C_GRX_P[0..7] <46>
N16P GPU
E24 B24
F24 PEG_RXP[1] PEG_TXP[1] C24 PEG_HTX_C_GRX_N[0..7] <46>
E23 B23 PEG_GTX_HRX_P[8..11] <41>
D23 PEG_RXP[2] PEG_TXP[2] A23 PEG_GTX_HRX_N[8..11] <41>
PEG_HTX_C_GRX_P[8..11] <41>
Caldera
E22 B22
F22 PEG_RXP[3] PEG_TXP[3] C22 PEG_HTX_C_GRX_N[8..11] <41>
PEG_GTX_HRX_P11 E21 B21 PEG_HTX_GRX_P11 CC24 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_P11
D PEG_GTX_HRX_N11 D21 PEG_RXP[4] PEG_TXP[4] A21 PEG_HTX_GRX_N11 CC12 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N11 D
PEG_GTX_HRX_N10 F20 PEG_RXP[5] PEG_TXP[5] C20 PEG_HTX_GRX_N10 CC11 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N10
PEG_GTX_HRX_N9 D19 PEG_RXP[6] PEG_TXP[6] A19 PEG_HTX_GRX_N9 CC10 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N9
l
PEG_GTX_HRX_N8 F18 PEG_RXP[7] PEG_TXP[7] C18 PEG_HTX_GRX_N8 CC9 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N8
PEG_GTX_HRX_P7 D17 A17 PEG_HTX_GRX_P7 CC20 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_P7
PEG_RXP[8] PEG_TXP[8]
ia
PEG_GTX_HRX_N7 E17 B17 PEG_HTX_GRX_N7 CC8 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N7
PEG_GTX_HRX_P6 F16 C16 PEG_HTX_GRX_P6 CC19 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_P6
PEG_GTX_HRX_N6 PEG_RXP[9] PEG_TXP[9] B16 PEG_HTX_GRX_N6 PEG_HTX_C_GRX_N6
PEG Lane Reversed

E16 CC7 1 2 0.22U_0402_16V7K
t
PEG_GTX_HRX_N5 E15 PEG_RXP[10] PEG_TXP[10] B15 PEG_HTX_GRX_N5 CC6 1 2 0.22U_0402_16V7K PEG_HTX_C_GRX_N5
n
e
id
+VCCIO PEG_RXN[15] PEG_TXN[15]
1 2 PEG_COMP PEG_COMP G2
C RC2 24.9_0402_1% PEG_RCOMP C
f
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils. <19> DMI_CRX_PTX_P0
DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0
DMI_CTX_PRX_P0 <19>
DMI_CRX_PTX_N0 E8 DMI_RXP[0] DMI_TXP[0] A8 DMI_CTX_PRX_N0
n
<19> DMI_CRX_PTX_N0 DMI_RXN[0] DMI_TXN[0] DMI_CTX_PRX_N0 <19>
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
<19> DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 DMI_RXP[1] DMI_TXP[1] DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 <19>
F6 B6 DMI_CTX_PRX_N1 <19>
<19> DMI_CRX_PTX_N1 DMI_RXN[1] DMI_TXN[1]
DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2
o
E5 A5 DMI_CTX_PRX_N2 <19>
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
J9 B4 DMI_CTX_PRX_N3 <19>
C
3 OF 14
SKL-H_BGA1440
REV = 1 ?
@
<58> CPU_DP1_P0
CPU_DP1_P0
CPU_DP1_N0
K36
CPU1D
DDI1_TXP[0]
?O
SKYLAKE_HAL
BGA1440
L L
EDP_TXP[0]
D29 CPU_EDP_TX0P
CPU_EDP_TX0N CPU_EDP_TX0P <25>
E
K37 E29
B <58> CPU_DP1_N0 CPU_DP1_P1 J35 DDI1_TXN[0] EDP_TXN[0] F28 CPU_EDP_TX1P CPU_EDP_TX0N <25> B
<58> CPU_DP1_P1 CPU_DP1_N1 J34 DDI1_TXP[1] EDP_TXP[1] E28 CPU_EDP_TX1N CPU_EDP_TX1P <25>
<58> CPU_DP1_N1 CPU_DP1_P2 H37 DDI1_TXN[1] EDP_TXN[1] B29 CPU_EDP_TX2N CPU_EDP_TX1N <25>
<58> CPU_DP1_P2 CPU_DP1_N2 H36 DDI1_TXP[2] EDP_TXN[2] A29 CPU_EDP_TX2P CPU_EDP_TX2N <25>
<58> CPU_DP1_N2 CPU_DP1_P3 J37 DDI1_TXN[2] EDP_TXP[2] B28 CPU_EDP_TX3N CPU_EDP_TX2P <25>
TBT <58> CPU_DP1_P3 CPU_DP1_N3 DDI1_TXP[3] EDP_TXN[3] CPU_EDP_TX3P CPU_EDP_TX3N <25>
J38 C28
<58> CPU_DP1_N3 DDI1_TXN[3] EDP_TXP[3] CPU_EDP_TX3P <25>
D
CPU_DP1_AUXP D27 C26 CPU_EDP_AUX
<58> CPU_DP1_AUXP CPU_DP1_AUXN E27 DDI1_AUXP EDP_AUXP B26 CPU_EDP_AUX# CPU_EDP_AUX <25>
<58> CPU_DP1_AUXN DDI1_AUXN EDP_AUXN CPU_EDP_AUX# <25>
CPU_DP2_P0 H34
<58> CPU_DP2_P0 CPU_DP2_N0 H33 DDI2_TXP[0] +VCCIO
<58> CPU_DP2_N0 CPU_DP2_P1 DDI2_TXN[0]
r
F37 A33
<58> CPU_DP2_P1 CPU_DP2_N1 DDI2_TXP[1] EDP_DISP_UTIL PAD~D @ T3
G38
<58> CPU_DP2_N1 CPU_DP2_P2 F34 DDI2_TXN[1]
<58> CPU_DP2_P2 CPU_DP2_N2 F35 DDI2_TXP[2] D37 EDP_COMP RH30 1 2 24.9_0402_1%
<58> CPU_DP2_N2 CPU_DP2_P3 E37 DDI2_TXN[2] EDP_RCOMP
mDP/TBT
o
<58> CPU_DP2_P3 CPU_DP2_N3 E36 DDI2_TXP[3] EDP_COMP
<58> CPU_DP2_N3 DDI2_TXN[3] CAD Note:Trace width=20 mils ,Spacing=25mil,
CPU_DP2_AUXP F26 Max length=100 mils.
<58> CPU_DP2_AUXP CPU_DP2_AUXN E26 DDI2_AUXP
<58> CPU_DP2_AUXN DDI2_AUXN
C34
F
D34 DDI3_TXP[0]
B36 DDI3_TXN[0]
B34 DDI3_TXP[1]
F33 DDI3_TXN[1]
E33 DDI3_TXP[2]
C33 DDI3_TXN[2]
B33 DDI3_TXP[3]
DDI3_TXN[3] G27 AUD_AZACPU_SCLK
A27 PROC_AUDIO_CLK G25 AUD_AZACPU_SDO AUD_AZACPU_SCLK <18>
B27 DDI3_AUXP PROC_AUDIO_SDI G29 AUD_AZACPU_SDI AUD_AZACPU_SDO <18>
DDI3_AUXN PROC_AUDIO_SDO
4 OF 14
SKL-H_BGA1440
?
A REV = 1 A
AUD_AZACPU_SDI 1 2 AUD_AZACPU_SDI_R
@ AUD_AZACPU_SDI_R <18>
RC66 20_0402_5%

PROCESSOR(1/7) DMI,FDI,PEG
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
5 4 3 2 1

5 4 3 2 1
Interleave CPU1A
?O
SKYLAKE_HAL
CPU1B
?O
SKYLAKE_HAL
BGA1440 BGA1440
DDR_A_D0 BR6 AG1 DDR_B_D0 BT11 AM9
DDR_A_D1 DDR0_DQ[0] DDR0_CKP[0] M_CLK_DDR0 <14> DDR_B_D1 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKP[0] M_CLK_DDR2 <15>
BT6 AG2 BR11 AN9
DDR_A_D2 DDR0_DQ[1] DDR0_CKN[0] M_CLK_DDR#0 <14> DDR_B_D2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[0] M_CLK_DDR#2 <15>
BP3 AK1 BT8 AM8
<14> DDR_A_D[0..63] DDR_A_D3 DDR0_DQ[2] DDR0_CKN[1] M_CLK_DDR#1 <14> DDR_B_D3 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKN[1] M_CLK_DDR#3 <15>
BR3 AK2 BR8 AM7
<14> DDR_A_MA[0..13] DDR_A_D4 DDR0_DQ[3] DDR0_CKP[1] M_CLK_DDR1 <14> DDR_B_D4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] M_CLK_DDR3 <15>
BN5 AL3 BP11 AM11
<14> DDR_A_DQS#[0..7] DDR_A_D5 DDR0_DQ[4] DDR0_CLKP[2] DDR_B_D5 DDR1_DQ[4]/DDR0_DQ[20] DDR1_CLKP[2]
BP6 AK3 BN11 AM10
<14> DDR_A_DQS[0..7] DDR_A_D6 DDR0_DQ[5] DDR0_CLKN[2] DDR_B_D6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CLKN[2]
BP2 AL2 BP8 AJ10
DDR_A_D7 BN3 DDR0_DQ[6] DDR0_CLKP[3] AL1 DDR_B_D7 BN8 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CLKP[3] AJ11
DDR_A_D8 BL4 DDR0_DQ[7] DDR0_CLKN[3] DDR_B_D8 BL12 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CLKN[3]
DDR_A_D9 BL5 DDR0_DQ[8] AT1 DDR_B_D9 BL11 DDR1_DQ[8]/DDR0_DQ[24] AT8
D DDR_A_D10 DDR0_DQ[9] DDR0_CKE[0] DDR_CKE0_DIMMA <14> DDR_B_D10 DDR1_DQ[9]/DDR0_DQ[25] DDR1_CKE[0] DDR_CKE2_DIMMB <15> D
BL2 AT2 BL8 AT10
DDR_A_D11 DDR0_DQ[10] DDR0_CKE[1] DDR_CKE1_DIMMA <14> DDR_B_D11 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CKE[1] DDR_CKE3_DIMMB <15>
BM1 AT3 BJ8 AT7
<15> DDR_B_D[0..63] DDR_A_D12 DDR0_DQ[11] DDR0_CKE[2] DDR_B_D12 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CKE[2]
BK4 AT5 BJ11 AT11
<15> DDR_B_MA[0..13] DDR_A_D13 DDR0_DQ[12] DDR0_CKE[3] DDR_B_D13 DDR1_DQ[12]/DDR0_DQ[28] DDR1_CKE[3]
BK5 BJ10
<15> DDR_B_DQS#[0..7] DDR_A_D14 DDR0_DQ[13] DDR_B_D14 DDR1_DQ[13]/DDR0_DQ[29]
BK1 AD5 BL7 AF11
<15> DDR_B_DQS[0..7] DDR_A_D15 DDR0_DQ[14] DDR0_CS#[0] DDR_CS0_DIMMA# <14> DDR_B_D15 DDR1_DQ[14]/DDR0_DQ[30] DDR1_CS#[0] DDR_CS2_DIMMB# <15>
BK2 AE2 BJ7 AE7
DDR_A_D16 DDR0_DQ[15] DDR0_CS#[1] DDR_CS1_DIMMA# <14> DDR_B_D16 DDR1_DQ[15]/DDR0_DQ[31] DDR1_CS#[1] DDR_CS3_DIMMB# <15>
BG4 AD2 BG11 AF10
DDR_A_D17 BG5 DDR0_DQ[16]/DDR0_DQ[32] DDR0_CS#[2] AE5 DDR_B_D17 BG10 DDR1_DQ[16]/DDR0_DQ[48] DDR1_CS#[2] AE10
l
DDR_A_D18 BF4 DDR0_DQ[17]/DDR0_DQ[33] DDR0_CS#[3] DDR_B_D18 BG8 DDR1_DQ[17]/DDR0_DQ[49] DDR1_CS#[3]
DDR_A_D19 BF5 DDR0_DQ[18]/DDR0_DQ[34] AD3 DDR_B_D19 BF8 DDR1_DQ[18]/DDR0_DQ[50] AF7
DDR_A_D20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_ODT[0] M_ODT0 <14> DDR_B_D20 DDR1_DQ[19]/DDR0_DQ[51] DDR1_ODT[0] M_ODT2 <15>
BG2 AE4 BF11 AE8
DDR_A_D21 DDR0_DQ[20]/DDR0_DQ[36] DDR0_ODT[1] M_ODT1 <14> DDR_B_D21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_ODT[1] M_ODT3 <15>
BG1 AE1 BF10 AE9
DDR0_DQ[21]/DDR0_DQ[37] DDR0_ODT[2] DDR1_DQ[21]/DDR0_DQ[53] DDR1_ODT[2]
ia
DDR_A_D22 BF1 AD4 DDR_B_D22 BG7 AE11
DDR_A_D23 BF2 DDR0_DQ[22]/DDR0_DQ[38] DDR0_ODT[3] DDR_B_D23 BF7 DDR1_DQ[22]/DDR0_DQ[54] DDR1_ODT[3]
DDR_A_D24 BD2 DDR0_DQ[23]/DDR0_DQ[39] AH5 DDR_B_D24 BB11 DDR1_DQ[23]/DDR0_DQ[55] AH10
DDR_A_D25 DDR0_DQ[24]/DDR0_DQ[40] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_BS0 <14> DDR_B_D25 DDR1_DQ[24]/DDR0_DQ[56] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_RAS# <15>
BD1 AH1 BC11 AH11
DDR_A_D26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_BS1 <14> DDR_B_D26 DDR1_DQ[25]/DDR0_DQ[57] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_WE# <15>
BC4 AU1 BB8 AF8
DDR_A_D27 DDR0_DQ[26]/DDR0_DQ[42] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_BG0 <14> DDR_B_D27 DDR1_DQ[26]/DDR0_DQ[58] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_CAS# <15>
BC5 BC8
t
DDR_A_D28 BD5 DDR0_DQ[27]/DDR0_DQ[43] AH4 DDR_B_D28 BC10 DDR1_DQ[27]/DDR0_DQ[59] AH8
DDR_A_D29 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_RAS# <14> DDR_B_D29 DDR1_DQ[28]/DDR0_DQ[60] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_BS0 <15>
BD4 AG4 BB10 AH9
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_WE# <14> DDR_B_D30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_BS1 <15>
BC1 AD1 BC7 AR9
DDR_A_D31 DDR0_DQ[30]/DDR0_DQ[46] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_CAS# <14> DDR_B_D31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_BG0 <15>
BC2 BB7
DDR_A_D32 AB1 DDR0_DQ[31]/DDR0_DQ[47] AH3 DDR_A_MA0 DDR_B_D32 AA11 DDR1_DQ[31]/DDR0_DQ[63] AJ9 DDR_B_MA0
n
DDR_A_D33 AB2 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] AP4 DDR_A_MA1 DDR_B_D33 AA10 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] AK6 DDR_B_MA1
DDR_A_D34 AA4 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AN4 DDR_A_MA2 DDR_B_D34 AC11 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] AK5 DDR_B_MA2
DDR_A_D35 AA5 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AP5 DDR_A_MA3 DDR_B_D35 AC10 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] AL5 DDR_B_MA3
DDR_A_D36 AB5 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] AP2 DDR_A_MA4 DDR_B_D36 AA7 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[3] AL6 DDR_B_MA4
e
DDR_A_D37 AB4 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] AP1 DDR_A_MA5 DDR_B_D37 AA8 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[4] AM6 DDR_B_MA5
DDR_A_D38 AA2 DDR0_DQ[37]/DDR1_DQ[5] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] AP3 DDR_A_MA6 DDR_B_D38 AC8 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AN7 DDR_B_MA6
DDR_A_D39 AA1 DDR0_DQ[38]/DDR1_DQ[6] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AN1 DDR_A_MA7 DDR_B_D39 AC7 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] AN10 DDR_B_MA7
DDR_A_D40 V5 DDR0_DQ[39]/DDR1_DQ[7] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AN3 DDR_A_MA8 DDR_B_D40 W8 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AN8 DDR_B_MA8
DDR_A_D41 V2 DDR0_DQ[40]/DDR1_DQ[8] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AT4 DDR_A_MA9 DDR_B_D41 W7 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AR11 DDR_B_MA9
id
DDR_A_D42 U1 DDR0_DQ[41]/DDR1_DQ[9] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] AH2 DDR_A_MA10 DDR_B_D42 V10 DDR1_DQ[41]/DDR1_DQ[25] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] AH7 DDR_B_MA10
DDR_A_D43 U2 DDR0_DQ[42]/DDR1_DQ[10] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] AN2 DDR_A_MA11 DDR_B_D43 V11 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AN11 DDR_B_MA11
DDR_A_D44 V1 DDR0_DQ[43]/DDR1_DQ[11] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] AU4 DDR_A_MA12 DDR_B_D44 W11 DDR1_DQ[43]/DDR1_DQ[27] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AR10 DDR_B_MA12
DDR_A_D45 V4 DDR0_DQ[44]/DDR1_DQ[12] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] AE3 DDR_A_MA13 DDR_B_D45 W10 DDR1_DQ[44]/DDR1_DQ[28] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AF9 DDR_B_MA13
DDR_A_D46 U5 DDR0_DQ[45]/DDR1_DQ[13] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU2 DDR_B_D46 V7 DDR1_DQ[45]/DDR1_DQ[29] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AR7
DDR_A_D47 DDR0_DQ[46]/DDR1_DQ[14] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_BG1 <14> DDR_B_D47 DDR1_DQ[46]/DDR1_DQ[30] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_BG1 <15>
C U4 AU3 V8 AT9 C
f
DDR_A_D48 DDR0_DQ[47]/DDR1_DQ[15] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR_A_ACT# <14> DDR_B_D48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_ACT# <15>
R2 R11
DDR_A_D49 P5 DDR0_DQ[48]/DDR1_DQ[32] AG3 DDR_B_D49 P11 DDR1_DQ[48] AJ7
DDR_A_D50 DDR0_DQ[49]/DDR1_DQ[33] DDR0_PAR DDR_A_PAR <14> DDR_B_D50 DDR1_DQ[49] DDR1_PAR DDR_B_PAR <15>
R4 AU5 P7 AR8
DDR_A_D51 DDR0_DQ[50]/DDR1_DQ[34] DDR0_ALERT# DDR_A_ALERT# <14> DDR_B_D51 DDR1_DQ[50] DDR1_ALERT# DDR_B_ALERT# <15>
P4 R8
DDR_A_D52 R5 DDR0_DQ[51]/DDR1_DQ[35] DDR_B_D52 R10 DDR1_DQ[51]
n
DDR_A_D53 P2 DDR0_DQ[52]/DDR1_DQ[36] BR5 DDR_A_DQS#0 DDR_B_D53 P10 DDR1_DQ[52] BP9 DDR_B_DQS#0
DDR_A_D54 R1 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[0] BL3 DDR_A_DQS#1 DDR_B_D54 R7 DDR1_DQ[53] DDR1_DQSN[0]/DDR0_DQSN[2] BL9 DDR_B_DQS#1
DDR_A_D55 P1 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSN[1] BG3 DDR_A_DQS#2 DDR_B_D55 P8 DDR1_DQ[54] DDR1_DQSN[1]/DDR0_DQSN[3] BG9 DDR_B_DQS#2
DDR_A_D56 M4 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[2]/DDR0_DQSN[4] BD3 DDR_A_DQS#3 DDR_B_D56 L11 DDR1_DQ[55] DDR1_DQSN[2]/DDR0_DQSN[6] BC9 DDR_B_DQS#3
DDR_A_D57 M1 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSN[3]/DDR0_DQSN[5] AB3 DDR_A_DQS4 DDR_B_D57 M11 DDR1_DQ[56] DDR1_DQSN[3]/DDR0_DQSN[7] AC9 DDR_B_DQS#4
o
DDR_A_D58 L4 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSP[4]/DDR1_DQSP[0] V3 DDR_A_DQS5 DDR_B_D58 L7 DDR1_DQ[57] DDR1_DQSN[4]/DDR1_DQSN[2] W9 DDR_B_DQS#5
DDR_A_D59 L2 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] R3 DDR_A_DQS6 DDR_B_D59 M8 DDR1_DQ[58] DDR1_DQSN[5]/DDR1_DQSN[3] R9 DDR_B_DQS#6
DDR_A_D60 M5 DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQSP[6]/DDR1_DQSP[4] M3 DDR_A_DQS7 DDR_B_D60 L10 DDR1_DQ[59] DDR1_DQSN[6] M9 DDR_B_DQS#7
DDR_A_D61 M2 DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D61 M10 DDR1_DQ[60] DDR1_DQSN[7]
DDR_A_D62 L5 DDR0_DQ[61]/DDR1_DQ[45] BP5 DDR_A_DQS0 DDR_B_D62 M7 DDR1_DQ[61] BR9 DDR_B_DQS0
DDR_A_D63 L1 DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQSP[0] BK3 DDR_A_DQS1 DDR_B_D63 L8 DDR1_DQ[62] DDR1_DQSP[0]/DDR0_DQSP[2] BJ9 DDR_B_DQS1
C
DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSP[1] BF3 DDR_A_DQS2 DDR1_DQ[63] DDR1_DQSP[1]/DDR0_DQSP[3] BF9 DDR_B_DQS2
BA2 DDR0_DQSP[2]/DDR0_DQSP[4] BC3 DDR_A_DQS3 AW11 DDR1_DQSP[2]/DDR0_DQSP[6] BB9 DDR_B_DQS3
BA1 DDR0_ECC[0] DDR0_DQSP[3]/DDR0_DQSP[5] AA3 DDR_A_DQS#4 AY11 DDR1_ECC[0] DDR1_DQSP[3]/DDR0_DQSP[7] AA9 DDR_B_DQS4
AY4 DDR0_ECC[1] DDR0_DQSN[4]/DDR1_DQSN[0] U3 DDR_A_DQS#5 AY8 DDR1_ECC[1] DDR1_DQSP[4]/DDR1_DQSP[2] V9 DDR_B_DQS5
AY5 DDR0_ECC[2] DDR0_DQSN[5]/DDR1_DQSN[1] P3 DDR_A_DQS#6 AW8 DDR1_ECC[2] DDR1_DQSP[5]/DDR1_DQSP[3] P9 DDR_B_DQS6
BA5 DDR0_ECC[3] DDR0_DQSN[6]/DDR1_DQSN[4] L3 DDR_A_DQS#7 AY10 DDR1_ECC[3] DDR1_DQSP[6] L9 DDR_B_DQS7
BA4 DDR0_ECC[4] DDR0_DQSN[7]/DDR1_DQSN[5] AW10 DDR1_ECC[4] DDR1_DQSP[7]
AY1 DDR0_ECC[5] AY3 AY7 DDR1_ECC[5] AW9
AY2 DDR0_ECC[6] DDR0_DQSP[8] BA3 AW7 DDR1_ECC[6] DDR1_DQSP[8] AY9
L
DDR0_ECC[7] DDR0_DQSN[8] DDR1_ECC[7] DDR1_DQSN[8]
DDR CHANNEL B
DDR CHANNEL A 2 121_0402_1% DDR_RCOMP0 G1
L
RH148 1 BN13
DDR_RCOMP[0] DDR_VREF_CA +V_DDR_REFA_R
RH149 1 2 75_0402_1% DDR_RCOMP1 H1 BP13
RH150 1 2 100_0402_1% DDR_RCOMP2 J2 DDR_RCOMP[1] DDR0_VREF_DQ BR13
DDR_RCOMP[2] DDR1_VREF_DQ +V_DDR_REFB_R
1 OF 14 2 OF 14
SKL-H_BGA1440 SKL-H_BGA1440
REV = 1 ? REV = 1 ?
E
B @ @ B
r D
A
F o A
Security Classification Compal Secret Data

PROCESSOR(2/7) DDRIII
5 4 3 2 1

5 4 3 2 1
CFG Straps for Processor

+VCCST
Stall reset sequence after PCU PLL lock until de-asserted 1 2 H_THERMTRIP#_R
?O
SKYLAKE_HAL
RH163 1K_0402_5% CPU1E
XDP_PREQ# BGA1440
1 = (Default) Normal Operation; No stall. 1 @ 2 B31 BN25 CFG0
CFG0 * RH156 51_0402_5%
H_VCCST_PWRGD
<17> PCH_CPU_BCLK_P
<17> PCH_CPU_BCLK_N
A32 BCLKP
BCLKN
CFG[0]
CFG[1]
CFG[2]
BN27
BN26
CFG1
CFG2
CFG0 <6>
T56
T72
PAD~D
PAD~D
@
@
1 2 D35 BN28 CFG3 T91 PAD~D @
D <17> PCH_CPU_PCIBCLK_P PCI_BCLKP CFG[3] D
0 = Stall. RH164 1K_0402_5% C36 BR20 CFG4 T92 PAD~D @
<17> PCH_CPU_PCIBCLK_N PCI_BCLKN CFG[4] BM20 CFG5 T93 PAD~D @
1 2 VR_SVID_DATA E31 CFG[5] BT20 CFG6 T94 PAD~D @
<17> CPU_24MHZ_P CLK24P CFG[6]
RH151 100_0402_1% D31 BP20 CFG7 T95 PAD~D @
<17> CPU_24MHZ_N CLK24N CFG[7]
CFG0 1 @ 2 BR23 CFG8 T96 PAD~D @
RH183 1K_0402_5% 1 2 VR_SVID_ALERT# CFG[8] BR22 CFG9 T101 PAD~D @
RH152 56.2_0402_1% CFG[9] BT23 CFG10 T102 PAD~D @
CFG[10] BT22 CFG11 T103 PAD~D @
l
CFG[11] BM19 CFG12 T104 PAD~D @
CFG[12] BR19 CFG13 T105 PAD~D @
CFG[13] BP19 CFG14 T106 PAD~D @
VR_SVID_ALERT# RH153 1 2 220_0402_5% VR_SVID_ALERT#_R BH31 CFG[14] BT19 CFG15 T107 PAD~D @
<71> VR_SVID_ALERT# VIDALERT# CFG[15]
ia
VR_SVID_CLK BH32
<71> VR_SVID_CLK VR_SVID_DATA VIDSCK
<71> VR_SVID_DATA BH29 BN23 CFG17 T108 PAD~D @
H_PROCHOT# RH158 1 2 499_0402_1% H_PROCHOT#_R BR30 VIDSOUT CFG[17] BP23 CFG16 T109 PAD~D @
+VCCSTG <43,61,62> H_PROCHOT# PROCHOT# CFG[16]
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS BP22 CFG19 T110 PAD~D @
DDR_VTT_PG_CTRL BT13 CFG[19] BN22 CFG18 T111 PAD~D @
DDR_VTT_CNTL CFG[18]
t
BR27 XDP_BPM#0
1: Normal Operation; Lane # definition matches BPM#[0] XDP_BPM#1
T112 PAD~D @
CFG2 BT27 T113 PAD~D @
socket pin map definition 1 2 H_PROCHOT# BPM#[1] BM31
RH165 1K_0402_5% H_VCCST_PWRGD 1 2 VCCST_PWRGD_CPU H13 BPM#[2] BT30
<43,45> H_VCCST_PWRGD VCCST_PWRGD BPM#[3]
n
0:Lane Reversed RH154 60.4_0402_1%
* <18> H_CPUPWRGD
<16> PLTRST_CPU#
PLTRST_CPU#
H_PM_SYNC_R
BT31
BP35 PROCPWRGD
RESET# PROC_TDO
BT28 XDP_TDO
XDP_TDI XDP_TDO <6,18>
BM34 BL32
<16> H_PM_SYNC_R H_PM_DOWN H_PM_DOWN_R PM_SYNC PROC_TDI XDP_TMS XDP_TDI <6,18>
CFG2 1 2 RH155 1 2 20_0402_5% BP31 BP28
e
<16> H_PM_DOWN H_PECI_R PM_DOWN PROC_TMS XDP_TCK XDP_TMS <6,18>
RH184 1K_0402_5% RH190 1 @ 2 0_0402_5% BT34 BR28
<16,43> H_PECI H_THERMTRIP#_R PECI PROC_TCK XDP_TCK <6,18>
J31
<16> H_THERMTRIP#_R THERMTRIP# CPU_XDP_TRST#
BP30
PROC_TRST# XDP_PREQ# CPU_XDP_TRST# <6,22>
RH519 1 @ 2 0_0402_5%~D BR33 BL30
<16> PROC_DETECT# SKTOCC# PROC_PREQ# XDP_PRDY# XDP_PREQ# <22>
BN1 BP27
id
PROC_SELECT# PROC_PRDY# XDP_PRDY# <22>
@ PAD~D T54 BM30
CATERR# BT25 CFG_RCOMP
CFG_RCOMP
Display Port Presence Strap +1.2V_DDR
1
C UC1 C
f
5 1 RH59
VCC NC 5 OF 14
1 : Disabled; No Physical Display Port DDR_VTT_PG_CTRL SKL-H_BGA1440 49.9_0402_1%
CFG4 1 2 ?
attached to Embedded Display Port @ 4 A REV = 1
2
CH197 Y 3
n
GND @
0 : Enabled; An external Display Port device is 0.1U_0402_10V7K
* connected to the Embedded Display Port
2 74AUP1G07GW_TSSOP5
o
4/13 UC1 SA00005U600 is X1 code.
CFG4 1 2 +3VS
RH185 1K_0402_5%
Change PN SA00005U600 to SA00007WE00.
C
RH525
220K_0402_5%~D
2
<64> SM_PG_CTRL
PCIE Port Bifurcation Straps
?O
SKYLAKE_HAL
L
11: (Default) x16 - Device 1 functions 1 and 2 disabled CPU1K
BGA1440
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
@ PAD~D T39 D1 BM33 T66 PAD~D @
disabled @ PAD~D T40 E1 RSVD_TP RSVD_TP BL33 T67 PAD~D @
E3 RSVD_TP RSVD_TP
01: Reserved - (Device 1 function 1 disabled ; function @ PAD~D T41
RSVD_TP
L
@ PAD~D T42 E2 BJ14 T68 PAD~D @
2 enabled) RSVD_TP RSVD_TP BJ13 T69 PAD~D @
BR1 RSVD_TP
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled @ PAD~D T43
* @ PAD~D T44 BT2 RSVD_TP
RSVD_TP RSVD
RSVD
BK28
BJ28
T70
T71
PAD~D
PAD~D
@
@
@ PAD~D T45 BN35
RSVD
E
CFG5 1 2 BJ18
B
RH186 1K_0402_5% @ PAD~D T46 J24 VSS B
@ PAD~D T47 H24 RSVD BJ16 T73 PAD~D @

CFG6 1 2 @ PAD~D T48 BN33 RSVD RSVD_TP BK16 T74 PAD~D @
RH187 1K_0402_5% @ PAD~D T49 BL34 RSVD RSVD_TP
RSVD
@ PAD~D T50 N29 BK24 T75 PAD~D @
R14 RSVD RSVD_TP BJ24
D
@ PAD~D T51 T76 PAD~D @
@ PAD~D T52 AE29 RSVD RSVD_TP
@ PAD~D T53 AA14 RSVD BK21 T77 PAD~D @
RSVD RSVD BJ21 T78 PAD~D @
A36 RSVD
PEG DEFER TRAINING RSVD
A37 BT17 T79 PAD~D @
RSVD RSVD
r
BR17 T80 PAD~D @
PCH_TRIGGER RH167 1 2 30_0402_5% PCH_TRIGGER_R H23 RSVD
1: (Default) PEG Train immediately following xxRESETB
CFG7 * de assertion
<22> PCH_TRIGGER
<22> CPU_TRIGGER
CPU_TRIGGER RH192 1 2 30_0402_5% CPU_TRIGGER_R J23 PROC_TRIGIN
PROC_TRIGOUT VSS
BK18
@ PAD~D T57 F30 BJ34 T81 PAD~D @
o
E30 RSVD RSVD_TP BJ33
0: PEG Wait for BIOS for training @ PAD~D T58
RSVD RSVD_TP
T82 PAD~D @
@ PAD~D T59 B30

@ PAD~D T60 C30 RSVD
CFG7 1 @ 2 RSVD G13 T83 PAD~D @
G3 RSVD AJ8
F
RH188 1K_0402_5% @ PAD~D T61 T84 PAD~D @
@ PAD~D T62 J3 RSVD RSVD BL31
RSVD RSVD
B2 T85 PAD~D @
NCTF B38 T86 PAD~D @
NCTF BP1 T87 PAD~D @
@ PAD~D T63 BR35 NCTF BR2 T88 PAD~D @
@ PAD~D T64 BR31 RSVD NCTF C1 T89 PAD~D @
@ PAD~D T65 BH30 RSVD NCTF C38 T90 PAD~D @
RSVD NCTF
11 OF 14
SKL-H_BGA1440
REV = 1 ?
@
A A

PROCESSOR(3/7) RSVD,CFG
5 4 3 2 1

5 4 3 2 1
+VCC_CORE +VCC_CORE
?
SKYLAKE_HALO
CPU1J
D D
? BGA1440
BJ17
CPU1GSKYLAKE_HALO BJ19 VCCOPC
BJ20 VCCOPC
BGA1440 BK17 VCCOPC
AA13 V32 BK19 VCCOPC
AA31 VCC VCC V33 BK20 VCCOPC
l
AA32 VCC VCC V34 BL16 VCCOPC
ia
AA37 VCC VCC W13 BL21 VCCOPC
AA38 VCC VCC W14 BM17 VCCOPC
AB29 VCC VCC W29 BN17 VCCOPC
AB30 VCC VCC W30 VCCOPC
t
AB31 VCC VCC W31 BJ23
AB32 VCC VCC W32 BJ26 RSVD
AB35 VCC VCC W35 BJ27 RSVD
AB36 VCC VCC W36 BK23 RSVD
n
AC13 VCC VCC Y29 BL23 RSVD
e
AC33 VCC VCC Y35 BM24 RSVD
id
AC34 VCC VCC Y36 RSVD
AC35 VCC VCC L14
AC36 VCC VCC P29 BL15
AD13 VCC VCC P30 BM16 VCCOPC_SENSE
AD14 VCC VCC P31 VSSOPC_SENSE
C
AD31 VCC VCC P32 BL22 C
f
AD32 VCC VCC P33 BM22 RSVD
AD33 VCC VCC P34 RSVD
AD34 VCC VCC P35
AD35 VCC VCC P36 BP15
VCC VCC VCCEOPIO
n
AD36 R13 BR15
AD37 VCC VCC R31 BT15 VCCEOPIO
AD38 VCC VCC R32 VCCEOPIO
AE13 VCC VCC R33 BP16
AE14 VCC VCC R34 BR16 RSVD
o
AE30 VCC VCC R35 BT16 RSVD
AE31 VCC VCC R36 RSVD
AE32 VCC VCC R37
AE35 VCC VCC R38 BN15
AE36 VCC VCC T29 BM15 VCCEOPIO_SENSE
AE37 VCC VCC T30 VSSEOPIO_SENSE
C
AE38 VCC VCC T31 BP17
AF35 VCC VCC T32 BN16 RSVD
AF36 VCC VCC T35 RSVD
AF37 VCC VCC T36
AF38 VCC VCC T37 BM14
K13 VCC VCC T38 BL14 VCC_OPC_1P8
K14 VCC VCC U29 VCC_OPC_1P8
L13 VCC VCC U30 BJ35
L
N13 VCC VCC U31 BJ36 RSVD
N14 VCC VCC U32 RSVD
N30 VCC VCC U33
N31 VCC VCC U34 +VCC_CORE AT13
N32 VCC VCC U35 AW13 ZVM#
L
N35 VCC VCC U36 MSM#
N36 VCC VCC V13 AU13
VCC VCC ZVM2#
1
N37 V14 AY13

N38 VCC VCC V31 RH197 MSM2#
P13 VCC VCC P14 RH166 1 @ 2 49.9_0402_1% BT29
VCC VCC 100_0402_1% OPC_RCOMP
RH57 1 @ 2 49.9_0402_1% BR25
E
B B
RH58 1 @ 2 49.9_0402_1% BP25 OPCE_RCOMP
2
OPCE_RCOMP2
AG37 RH198 1 @ 2 0_0402_5%
VCC_SENSE VCCSENSE <71>
AG38 RH465 1 @ 2 0_0402_5%
VSSSENSE <71>
VSS_SENSE 10 OF 14
SKL-H_BGA1440
REV = 1 ?
1
D
RH466 @
7 OF 14
SKL-H_BGA1440 100_0402_1%
REV = 1 ?
2
o r
A
F A

PROCESSOR(4/7) PWR,BYPASS
5 4 3 2 1

5 4 3 2 1
+VCCIO +VCCSTG +VCCST
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
D D
1 1 1 1 1 1 1 1 1
CH102
CH103
CH104
CH105
CH106
CH107
CH108
CH109
CH110
+VCCSA +1.2V_DDR
2 2 2 2 2 2 2 2 2
l
?
SKYLAKE_HALO
CPU1I
BGA1440
J30 AA6
K29 VCCSA VDDQ AE12
ia
K30 VCCSA VDDQ AF5
K31 VCCSA VDDQ AF6 +1.2V_DDR
K32 VCCSA VDDQ AG5
K33 VCCSA VDDQ AG9
K34 VCCSA VDDQ AJ12
t
K35 VCCSA VDDQ AL11
L31 VCCSA VDDQ AP6
VCCSA VDDQ
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
L32 AP7 1 1 1 1
L35 VCCSA VDDQ AR12
VCCSA VDDQ
CH129
CH130
CH131
CH132
L36 AR6
n
L37 VCCSA VDDQ AT12 +1.2V_DDR
L38 VCCSA VDDQ AW6 2 2 2 2
M29 VCCSA VDDQ AY6
M30 VCCSA VDDQ J5
e
M31 VCCSA VDDQ J6
VCCSA VDDQ
1
M32 K12
M33 VCCSA VDDQ K6 RH473
M34 VCCSA VDDQ L12 @ 0_0402_5%
id
M35 VCCSA VDDQ L6
C +VCCIO M36 VCCSA VDDQ R6 C
2
VCCSA VDDQ T6 +1.2V_VCCPLL_OC +1.2V_DDR
VDDQ W6
AG12 VDDQ RH530 1 @ 2 0_0402_5%
G15 VCCIO Y12
f
G17 VCCIO VDDQC
VCCIO VCCPLL_OC is allowed to be turned off +1.2V_DDR
G19 BH13
G21 VCCIO VCCPLL_OC G11
during S3 and DS3 if it is not powered directly from VDDQ
H15 VCCIO VCCPLL_OC +VCCST
VCCIO
n
H16
H17 VCCIO H30
VCCIO VCCST +VCCSTG
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
H19
VCCIO
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
H20 H29
H21 VCCIO VCCSTG
o
VCCIO 1 1 1 1 1 1 1 1 1 1 1
CH118
CH121
CH124
CH120
CH119
CH122
CH123
CH125
CH126
CH127
CH128
H26 G30
H27 VCCIO VCCSTG +VCCST
J15 VCCIO H28
J16 VCCIO VCCPLL J28 2 2 2 2 2 2 2 2 2 2 2
J17 VCCIO VCCPLL
J19 VCCIO RH201 1 2 100_0402_1%
C
VCCIO +VCCSA
J20 M38 RH202 1 @ 2 0_0402_5%
VCCIO VCCSA_SENSE VCCSA_SENSE <71>
J21 M37 RH470 1 @ 2 0_0402_5%
VCCIO VSSSA_SENSE VSSSA_SENSE <71>
J26 RH469 1 2 100_0402_1%
J27 VCCIO H14
VCCIO VCCIO_SENSE J14
VSSIO_SENSE
VCCIO_SENSE <74>
L
VSSIO_SENSE <74>
B B
9 OF 14
L
SKL-H_BGA1440
REV = 1 ?
@
D E
o r
A
F Security Classification
Issued Date 2015/01/30
Compal Secret Data
Deciphered Date
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2016/12/31 Title
Size Document Number

Custom
PROCESSOR(5/7) PWR
Rev
0.1
A

5 4 3 2 1

5 4 3 2 1
+VCCGT
+VCCGT +VCCGT
?
?
SKYLAKE_HALO SKYLAKE_HALO
CPU1H CPU1N
BGA1440
D BG34 BGA1440 D
VCCGT AV29 AJ29
BG35 VCCGT VCCGT
VCCGT AV30 AJ30
BG36 VCCGT VCCGT AF29
VCCGT AV31 AJ31 VCCGTX
BH33 VCCGT VCCGT AF30
BH38 VCCGT VCCGT AG13
l
VCCGT AW14 AK31 VCCGTX
BJ37 VCCGT VCCGT AG14
BJ38 VCCGT VCCGT AG31
BL36 VCCGT VCCGT AG32
BL37 VCCGT VCCGT AG33
ia
BM36 VCCGT VCCGT AG34
BM37 VCCGT VCCGT AG35
BN36 VCCGT VCCGT AG36
BN37 VCCGT VCCGT AH13
VCCGT AW38 AL13 VCCGTX
BN38 VCCGT VCCGT AH14
t
VCCGT AY29 AL29 VCCGTX
BP37 VCCGT VCCGT AH29
BP38 VCCGT VCCGT AH30
BR37 VCCGT VCCGT AH31
BT37 VCCGT VCCGT AH32
BE38 AJ13
n
VCCGT AY36 AL36 VCCGT
BF13 VCCGT VCCGTX AJ14
BF14 VCCGT VCCGTX
BF29 VCCGT
VCCGT BA13 AM13 VCCGT
BF30 VCCGT
e
BF31 VCCGT
BF32 VCCGT
BF35 VCCGT
BF36 VCCGT
id
BF37 VCCGT
C BF38 VCCGT C
BG29 VCCGT
BG30 VCCGT
BG31 VCCGT
VCCGT BB13 AN13 VCCGT
BG32 VCCGT
f
BG33 VCCGT
BC36 VCCGT
BC37 VCCGT
BC38 VCCGT
VCCGT
n
BD13 VCCGT VCCGT
VCCGT BB35 AN35
BD14 VCCGT VCCGT
VCCGT BB36 AN36
BD29 VCCGT VCCGT
VCCGT BB37 AN37
BD30 VCCGT VCCGT
VCCGT BB38 AN38
BD31 VCCGT VCCGT
o
VCCGT BC29 AP13
BD32 VCCGT VCCGT
VCCGT BC30 AP14
BD33 VCCGT VCCGT +VCCGT
VCCGT BC31 AP29
BD34 VCCGT VCCGT
VCCGT BC32 AP30
BD35 VCCGT VCCGT
VCCGT BC35 AP31
BD36 VCCGT VCCGT
VCCGT BE33 AP32
BE31 VCCGT VCCGT
C
VCCGT BE34 AP35
BE32 VCCGT VCCGT
VCCGT BE35 AP36
BE37 VCCGT VCCGT
VCCGT BE36 AP37
1
VCCGT AP38 VCCGT
VCCGT RH203
AR29
8 OF 14 AR30 VCCGT 100_0402_1%
SKL-H_BGA1440 AR31 VCCGT
AR32 VCCGT
2
?
L
REV = 1 AR33 VCCGT AH38 RH204 1 @ 2 0_0402_5%
VCCGT VCCGT_SENSE VCCGT_SENSE <71>
@ AR34 AH35
AR35 VCCGT VSSGTX_SENSE AH37 RH471 1 @ 2 0_0402_5%
VCCGT VSSGT_SENSE VSSGT_SENSE <71>
AR36 AH36
AT14 VCCGT VCCGTX_SENSE
B VCCGT B
AT31
L
AT32 VCCGT
AT33 VCCGT
1
AT34 VCCGT
VCCGT RH472
AT35
AT36 VCCGT 100_0402_1%
E
AT37 VCCGT
AT38 VCCGT
2
AU14 VCCGT
AU29 VCCGT
AU30 VCCGT
AU31 VCCGT
AU32 VCCGT
D
AU35 VCCGT
AU36 VCCGT
AU37 VCCGT
VCCGT 14 OF 14
AU38
VCCGT
r
SKL-H_BGA1440
?
REV = 1
@
F o Security Classification
Compal Secret Data
Deciphered Date
Compal Electronics,TitleInc.
2016/12/31 Title
A
PROCESSOR(6/7) PM,XDP,CLK
5 4 3 2 1

5 4 3 2 1
? ?
SKYLAKE_HALO SKYLAKE_HALO
CPU1F CPU1L
BGA1440 CPU1M
SKYLAKE_HALO
BGA1440
Y38 K1 BGA1440
VSS VSS C17 C25
Y37 J36 VSS VSS BB4 AK30
VSS VSS C13 C23 VSS VSS
VSS VSS C9 C21 VSS VSS
VSS VSS BT32 C19 VSS VSS
D Y11 J25 VSS VSS BB1 AJ38 D
Y10 J22 VSS VSS BA38 AJ37
VSS VSS BT14 BM29 VSS VSS
W34 J4 VSS VSS BA10 AJ3
W33 H35 VSS VSS BA9 AJ2
l
W12 H32 VSS VSS BA8 AJ1
W5 H25 VSS VSS BA7 AH34
VSS VSS BR36 BM8 VSS VSS
W4 H22 VSS VSS BA6 AH33
VSS VSS BR34 BM7 VSS ? VSS
W3 H18 VSS VSS B9 AH12
ia
W2 H12 VSS VSS AY34 AH6
W1 H11 VSS VSS AY33 AG30
VSS VSS BR24 BL38 VSS VSS
V30 G28 VSS VSS AY14 AG29
V29 G26 VSS VSS AY12 AG11
V12 G24 AW30 AG10
t
BR14 VSS VSS BL6
V6 VSS VSS G23 AW29 VSS VSS AG8
BR12 VSS VSS BK25
U38 VSS VSS G22 AW12 VSS VSS AG7
BR7 VSS VSS BK22
U37 VSS VSS G20 AW5 VSS VSS AG6
BP34 VSS VSS BK13
U6 VSS VSS G18 AW4 VSS VSS AF14
VSS VSS
n
VSS VSS BP33 BK6 VSS VSS
T34 G16 VSS VSS AW3 AF13
VSS VSS BP29 BJ30 VSS VSS
T13 G10 AV38 AF3
e
BP21 VSS VSS BJ12
T12 VSS VSS G9 AV37 VSS VSS AF2
BP18 VSS VSS BH11
T11 VSS VSS G8 AU34 VSS VSS AF1
BP14 VSS VSS BH10
T10 VSS VSS G6 AU33 VSS VSS AE34
BP12 VSS VSS BH7
T9 VSS VSS G5 AU12 VSS VSS AE33
VSS VSS
id
VSS VSS BP7 BH6 VSS VSS
T8 G4 VSS VSS AU11 AE6
VSS VSS BN34 BH3 VSS VSS
T7 F36 VSS VSS AU10 AD30
VSS VSS BN31 BH2 VSS VSS
VSS VSS BN30 BG37 VSS VSS
C VSS VSS BN29 BG14 VSS VSS C
BN24 BG6
f
T2 VSS VSS F25 AU6 VSS VSS AD10
BN21 VSS VSS BF34
T1 VSS VSS F23 AT30 VSS VSS AD9
BN20 VSS VSS BF6
R30 VSS VSS F21 AT29 VSS VSS AD8
BN19 VSS VSS BE30
R29 VSS VSS F19 AT6 VSS VSS AD7
BN18 VSS VSS BE5
VSS VSS VSS VSS
n
R12 F17 VSS VSS AR38 AD6
VSS VSS BN14 BE4 VSS VSS
P38 F15 VSS VSS AR37 AC38
o
VSS VSS BN4 BD38 VSS VSS
N34 F8 VSS VSS AR4 AC5
VSS VSS BN2 BD37 VSS VSS
VSS VSS BM38 BD12 VSS VSS
N10 F2 VSS VSS AP34 AC1
BM27 BD8
C
N9 VSS VSS E38 AP33 VSS VSS AB34
BM26 VSS VSS BD7
BM23 VSS VSS BD6
BM21 VSS VSS BC33
N6 VSS VSS E9 AP10 VSS VSS AA30
BM13 VSS VSS BC14
N5 VSS VSS E4 AP9 VSS VSS AA29
BM12 VSS VSS BC13
N4 VSS VSS D33 AP8 VSS VSS AA12
BM9 VSS VSS BC6
N3 VSS VSS D30 AN30 VSS VSS A30
BM6 VSS VSS BB30
VSS VSS VSS VSS
L
N2 D28 VSS VSS AN29 A28
VSS VSS BM2 BB29 VSS VSS
N1 D26 VSS VSS AN12 A26
VSS VSS BL29 BB6 VSS VSS
M14 D24 VSS VSS AN6 A24
VSS VSS BK29 BB5 VSS VSS
M13 D22 VSS VSS AN5 A22
VSS VSS BK15 VSS VSS
M12 D20 VSS AM38 A20
VSS VSS BK14 VSS VSS
M6 D18 AM37 A18
L
BJ32 VSS
L34 VSS VSS D16 AM12 VSS VSS A16
BJ31 VSS
BJ25 VSS
BJ22 VSS
BH14 VSS
B K38 VSS VSS D9 C2 AM2 VSS VSS A9 B
VSS
E
VSS VSS BH12 NCTFVSS VSS VSS
K11 D6 VSS BT36 AM1 A6
VSS VSS BH9 NCTFVSS VSS VSS
K10 D3 VSS BT35 AL34
VSS VSS BH8 NCTFVSS VSS
K9 C37 VSS BT4 AL33
VSS VSS BH5 NCTFVSS VSS
K8 C31 VSS BT3 AL14 B37
VSS VSS BH4 NCTFVSS VSS NCTFVSS
K7 C29 VSS BR38 AL12 B3
VSS VSS BH1 NCTFVSS VSS NCTFVSS
K5 C27 VSS AL10 A34
D
VSS VSS BG38 VSS NCTFVSS
K4 VSS AL9 A4
VSS BG13 VSS NCTFVSS
K3 D38 VSS AL8 A3
VSS NCTFVSS BG12 VSS NCTFVSS
K2 VSS AL7
VSS BF33 VSS
VSS AL4
BF12 VSS
VSS
r
6 OF 14 BE29
SKL-H_BGA1440 BE6 VSS
? VSS
BD9 13 OF 14
REV = 1 VSS
BC34 SKL-H_BGA1440
@ VSS ?
BC12
o
VSS REV = 1
BB12
VSS @
12 OF 14
SKL-H_BGA1440
?
F
REV = 1
@
A A

PROCESSOR(7/7) VSS
5 4 3 2 1

5 4 3 2 1
<8>
<8>
DDR_A_D[0..63]
DDR_A_MA[0..13] +1.2V_DDR JDIMM1
JP?
5.2H
<8> DDR_A_DQS#[0..7] +1.2V_DDR
<8> DDR_A_DQS[0..7]
1 2
DDR_A_D1 3 VSS1 VSS2 4 DDR_A_D0
Layout Note: Layout Note: DQ5 DQ4
5 6
Place near JDIMM1.257,259 Place near JDIMM1.258 DDR_A_D5 7 VSS3 VSS4 8 DDR_A_D4
9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS5 VSS6 12
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_A_D6
DDR_A_D3 17 VSS8 DQ6 18
+2.5V_MEM +0.6VS 19 DQ7 VSS9 20 DDR_A_D2
DDR_A_D7 21 VSS10 DQ2 22
Layout Note: DQ3 VSS11 DDR_A_D12
23 24
Place near JDIMM1.255 DDR_A_D9 25 VSS12 DQ12 26
DQ13 VSS13 DDR_A_D13
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
D 27 28 D
DDR_A_D8 VSS14 DQ8
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V
29 30
1U_0402_6.3V DQ9 VSS15 DDR_A_DQS#1
1U_0402_6.3V
1 1 1 1 31 32
VSS16 DQS1_c DDR_A_DQS1
CD12
CD13
CD14
CD15
1 1 1 1 33 34
DM1_n/DBI_n DQS1_t
CD3
CD4
35 36
DDR_A_D15 VSS17 VSS18 DDR_A_D14
CD9
CD10
37 38
2 2 2 2 +3VS 39 DQ15 DQ14 40
2 2 2 2 DDR_A_D10 41 VSS19 VSS20 42 DDR_A_D11
43 DQ10 DQ11 44
l
45 46
47 DQ21 DQ20 48
0.1U_0402_16V7K~D
2.2U_0603_6.3V6K~D
49 50
51 DQ17 DQ16 52
1 1 DDR_A_DQS#2 VSS25 VSS26
CD16
CD17
53 54
ia
2 2 DDR_A_D19 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_A_D22
DDR_A_D18 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_A_D28
t
DDR_A_D24 67 VSS32 DQ28 68
Layout Note: DQ29 VSS33 DDR_A_D25
69 70
Place near JDIMM1 DDR_A_D29 71 VSS34 DQ24 72
DQ25 VSS35
n
73 74 DDR_A_DQS#3
75 VSS36 DQS3_c 76 DDR_A_DQS3
+1.2V_DDR 77 DM3_n/DBI3_n DQS3_t 78
81 DQ30 DQ31 82
e
DQ26 DQ27
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
85 86
87 VSS41 VSS42 88
1 1 1 1 1 1 1 1 CB5/NC CB4/NC
CD1
CD2
CD75
CD74
CD77
CD76
CD79
CD78
89 90
91 VSS43 VSS44 92
CB1/NC CB0/NC
id
93 94
2 2 2 2 2 2 2 2 95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
C 103 CB2/NC VSS49 104 C
105 VSS50 CB7/NC 106
f
107 CB3/NC VSS51 108 DDR4_DRAMRST#
DDR_CKE0_DIMMA 109 VSS52 RESET_n 110 DDR_CKE1_DIMMA
<8> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <8>
111 112
+1.2V_DDR DDR_A_BG1 113 VDD1 VDD2 114
<8> DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT# DDR_A_ACT# <8>
<8> DDR_A_BG0 115 116 DDR_A_ALERT# <8>
n
117 BG0 ALERT_n 118
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
A9 A7
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
123 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
1 DDR_A_MA6 A8 A5 DDR_A_MA4
o
1 1 1 1 1 1 1 1 127 128
+ CD11 129 A6 A4 130
DDR_A_MA3 VDD7 VDD8 DDR_A_MA2
CD5
CD6
CD7
CD8
CD70
CD71
CD72
CD73
220U_D7_2VM_R6M 131 132

DDR_A_MA1 133 A3 A2 134
A1 EVENT_n/NF
All VREF traces should
2 2 2 2 2 2 2 2 2 135 136
M_CLK_DDR0 VDD9 VDD10 M_CLK_DDR1
have 10 mil trace width
137 138
<8> M_CLK_DDR0 M_CLK_DDR#0 CK0_t CK1_t/NF M_CLK_DDR#1 M_CLK_DDR1 <8>
139 140
<8> M_CLK_DDR#0 CK0_c CK1_c/NF M_CLK_DDR#1 <8>
C
141 142
DDR_A_PAR 143 VDD11 VDD12 144 DDR_A_MA0
<8> DDR_A_PAR DDR_A_BS1 PARITY A0 DDR_A_MA10
145 146
<8> DDR_A_BS1 BA1 A10/AP
147 148
DDR_CS0_DIMMA# 149 VDD13 VDD14 150 DDR_A_BS0
<8> DDR_CS0_DIMMA# DDR_A_WE# CS0_n BA0 DDR_A_RAS# DDR_A_BS0 <8>
151 152
<8> DDR_A_WE# WE_n/A14 RAS_n/A16 DDR_A_RAS# <8>
153 154
M_ODT0 155 VDD15 VDD16 156 DDR_A_CAS#
<8> M_ODT0 DDR_CS1_DIMMA# ODT0 CAS_n/A15 DDR_A_MA13 DDR_A_CAS# <8>
157 158
<8> DDR_CS1_DIMMA# CS1_n A13
159 160
L
M_ODT1 161 VDD17 VDD18 162
<8> M_ODT1 ODT1 C0/CS2_n/NC +V_DDR_REFA
163 164
165 VDD19 VREFCA 166 DIMM_CHA_SA2
167 C1, CS3_n,NC SA2 168
0.1U_0402_16V7K~D
169 170
171 DQ37 DQ36 172 1
L
CD18
173 174
175 DQ33 DQ32 176
+1.2V_DDR DDR_A_DQS#4 177 VSS57 VSS58 178
+1.2V_DDR 2
B +3VS +3VS +3VS DDR_A_D38 183 VSS60 DQ39 184 B
185 DQ38 VSS61 186 DDR_A_D34
E
DDR_A_D39 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D40
DDR_A_D44 VSS64 DQ45
1
191 192
1
RD35 193 DQ44 VSS65 194 DDR_A_D45

RD1 RD2 RD3 470_0402_1% DDR_A_D41 195 VSS66 DQ41 196
@ @ @ 197 DQ40 VSS67 198 DDR_A_DQS#5
0_0402_5% 0_0402_5% 0_0402_5% VSS68 DQS5_c DDR_A_DQS5
199 200
+1.2V_DDR
2
D
201 DM5_n/DBI5_n DQS5_t 202
2

DIMM_CHA_SA0 DIMM_CHA_SA1 DIMM_CHA_SA2 DDR4_DRAMRST# 1 @ 2 205 DQ46 DQ47 206
<15> DDR4_DRAMRST# H_DRAMRST# <18> DDR_A_D42 VSS71 VSS72 DDR_A_D46
RD31 0_0402_5% 207 208
DQ42 DQ43
0.1U_0402_16V7K~D
209 210
1

1 DQ52 DQ53
r
CD69
RD28 RD29 RD30 213 214

0_0402_5% 0_0402_5% 0_0402_5% DQ49 DQ48
217 218
2 DDR_A_DQS#6 219 VSS77 VSS78 220
+1.2V_DDR
2

o
DDR_A_D53 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_A_D49
DDR_A_D55 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_A_D61
DDR_A_D56 233 VSS84 DQ60 234
235 DQ61 VSS85 236 DDR_A_D57
F
DDR_A_D60 237 VSS86 DQ57 238
+V_DDR_REFA_R +1.2V_DDR 239 DQ56 VSS87 240 DDR_A_DQS#7
241 VSS88 DQS7_c 242 DDR_A_DQS7
1

RH206 247 DQ62 DQ63 248
1K_0402_1%~D DDR_A_D62 249 VSS91 VSS92 250 DDR_A_D63
20mil 251 DQ58 DQ59 252
PCH_SMBCLK 253 VSS93 VSS94 254 PCH_SMBDATA
<15,18,36,38> PCH_SMBCLK PCH_SMBDATA <15,18,36,38>
2
255 SCL SDA 256 DIMM_CHA_SA0

+V_DDR_REFA +3VS VDDSPD SA0
RH484 1 2 2_0402_1% 257 258
+2.5V_MEM VPP1 VTT DIMM_CHA_SA1 +0.6VS
259 260
261 VPP2 SA1 262
1
1
A GND1 GND2 A
CH101 RH209
0.022U_0402_25V7K 1K_0402_1%~D
2
1
BELLW_SD-80886-1021 CONN@
2
RH211
24.9_0402_1%
2

DDRIII DIMMA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
5 4 3 2 1

5 4 3 2 1
+1.2V_DDR JDIMM2
JP?
9.2H
<8> DDR_B_D[0..63] +1.2V_DDR
<8> DDR_B_MA[0..13]
1 2
<8> DDR_B_DQS#[0..7] DDR_B_D0 VSS1 VSS2 DDR_B_D5
<8> DDR_B_DQS[0..7] 3 4
5 DQ5 DQ4 6
Layout Note: Layout Note: DDR_B_D4 VSS3 VSS4 DDR_B_D1
7 8
Place near JDIMM2.258 Place near JDIMM2.257,259 9 DQ1 DQ0 10
DDR_B_DQS#0 11 VSS5 VSS6 12
DDR_B_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_B_D2
DDR_B_D6 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDR_B_D7
+0.6VS +2.5V_MEM 23 DQ3 VSS11 24 DDR_B_D8
DDR_B_D10 25 VSS12 DQ12 26
D 27 DQ13 VSS13 28 DDR_B_D9 D
31 DQ9 VSS15 32 DDR_B_DQS#1
VSS16 DQS1_c DDR_B_DQS1
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
Layout Note: 33 34
35 DM1_n/DBI_n DQS1_t 36
1 1 1 1 1 1 1 1 Place near JDIMM2.255 DDR_B_D12 VSS17 VSS18 DDR_B_D15
CD32
CD30
CD31
37 38
DQ15 DQ14
CD90
CD89
CD88
CD27
CD28
39 40
DDR_B_D13 41 VSS19 VSS20 42 DDR_B_D11
2 2 2 2 2 2 2 2 43 DQ10 DQ11 44
DDR_B_D16 VSS21 VSS22 DDR_B_D22
l
45 46
47 DQ21 DQ20 48
+3VS 51 DQ17 DQ16 52
ia
DDR_B_D19 59 VSS28 DQ22 60
DQ23 VSS29 DDR_B_D20
0.1U_0402_16V7K~D
2.2U_0603_6.3V6K~D
61 62
DDR_B_D23 63 VSS30 DQ18 64
1 1 DQ19 VSS31 DDR_B_D27
CD34
CD35
65 66
t
DDR_B_D25 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_B_D30
2 2 DDR_B_D28 71 VSS34 DQ24 72
DQ25 VSS35
Layout Note:
n
73 74 DDR_B_DQS#3
Place near JDIMM2 75 VSS36 DQS3_c 76 DDR_B_DQS3
81 DQ30 DQ31 82
e
85 DQ26 DQ27 86
87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
91 VSS43 VSS44 92
CB1/NC CB0/NC
id
+1.2V_DDR 93 94
95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
VSS48 CB6/NC
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
101 102
C 103 CB2/NC VSS49 104 C
1 1 1 1 1 1 1 1 VSS50 CB7/NC
CD19
CD20
CD21
CD22
CD83
CD81
CD80
CD82
105 106
f
107 CB3/NC VSS51 108 DDR4_DRAMRST#
DDR_CKE2_DIMMB VSS52 RESET_n DDR_CKE3_DIMMB DDR4_DRAMRST# <14>
109 110
2 2 2 2 2 2 2 2 <8> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <8>
111 112
DDR_B_BG1 113 VDD1 VDD2 114
<8> DDR_B_BG1 DDR_B_BG0 BG1 ACT_n DDR_B_ALERT# DDR_B_ACT# <8>
<8> DDR_B_BG0 115 116 DDR_B_ALERT# <8>
n
117 BG0 ALERT_n 118
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7
123 A9 A7 124
+1.2V_DDR DDR_B_MA6 A8 A5 DDR_B_MA4
o
127 128
129 A6 A4 130
DDR_B_MA1 133 A3 A2 134
A1 EVENT_n/NF
All VREF traces should
135 136 have 10 mil trace width
M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
137 138
<8> M_CLK_DDR2 M_CLK_DDR#2 CK0_t CK1_t/NF M_CLK_DDR#3 M_CLK_DDR3 <8>
1 139 140
<8> M_CLK_DDR#2 CK0_c CK1_c/NF M_CLK_DDR#3 <8>
C
1 1 1 1 1 1 1 1 141 142
+ CD33 DDR_B_PAR 143 VDD11 VDD12 144 DDR_B_MA0
<8> DDR_B_PAR DDR_B_BS1 PARITY A0 DDR_B_MA10
CD23
CD24
CD25
CD26
CD87
CD85
CD84
CD86
220U_D7_2VM_R6M 145 146

<8> DDR_B_BS1 BA1 A10/AP
147 148
2 2 2 2 2 2 2 2 2 DDR_CS2_DIMMB# 149 VDD13 VDD14 150 DDR_B_BS0
<8> DDR_CS2_DIMMB# DDR_B_WE# CS0_n BA0 DDR_B_RAS# DDR_B_BS0 <8>
151 152
<8> DDR_B_WE# WE_n/A14 RAS_n/A16 DDR_B_RAS# <8>
153 154
M_ODT2 155 VDD15 VDD16 156 DDR_B_CAS#
<8> M_ODT2 DDR_CS3_DIMMB# ODT0 CAS_n/A15 DDR_B_MA13 DDR_B_CAS# <8>
157 158
<8> DDR_CS3_DIMMB# CS1_n A13
159 160
L
M_ODT3 161 VDD17 VDD18 162
<8> M_ODT3 ODT1 C0/CS2_n/NC +V_DDR_REFB
163 164
165 VDD19 VREFCA 166 DIMM_CHB_SA2
167 C1, CS3_n,NC SA2 168
0.1U_0402_16V7K~D
169 170
171 DQ37 DQ36 172 1
L
CD29
173 174
175 DQ33 DQ32 176
+1.2V_DDR 2
B DDR_B_D33 183 VSS60 DQ39 184 B
185 DQ38 VSS61 186 DDR_B_D37
E
DDR_B_D32 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_B_D44
DDR_B_D40 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_B_D45
DDR_B_D41 195 VSS66 DQ41 196
+3VS +3VS +3VS 197 DQ40 VSS67 198 DDR_B_DQS#5
199 VSS68 DQS5_c 200 DDR_B_DQS5
+1.2V_DDR
D
205 DQ46 DQ47 206
VSS71 VSS72
1
DDR_B_D43 207 208 DDR_B_D46

RD4 RD5 RD6 209 DQ42 DQ43 210
@ @ DDR_B_D52 211 VSS73 VSS74 212 DDR_B_D54
0_0402_5% 0_0402_5% 0_0402_5% DQ52 DQ53
r
213 214
2
217 DQ49 DQ48 218

DIMM_CHB_SA0 DIMM_CHB_SA1 DIMM_CHB_SA2 DDR_B_DQS#6 219 VSS77 VSS78 220
+1.2V_DDR
o
1
DDR_B_D50 225 VSS80 DQ54 226

RD38 RD39 RD40 227 DQ55 VSS81 228 DDR_B_D49
@ DDR_B_D55 229 VSS82 DQ50 230
0_0402_5% 0_0402_5% 0_0402_5% DQ51 VSS83 DDR_B_D59
231 232
DDR_B_D61 233 VSS84 DQ60 234
2
235 DQ61 VSS85 236 DDR_B_D57
F
DDR_B_D62 237 VSS86 DQ57 238
239 DQ56 VSS87 240 DDR_B_DQS#7
241 VSS88 DQS7_c 242 DDR_B_DQS7
+V_DDR_REFB_R DDR_B_D56 245 VSS89 VSS90 246 DDR_B_D63
+1.2V_DDR 247 DQ62 DQ63 248
251 DQ58 DQ59 252
1
PCH_SMBCLK 253 VSS93 VSS94 254 PCH_SMBDATA

<14,18,36,38> PCH_SMBCLK SCL SDA DIMM_CHB_SA0 PCH_SMBDATA <14,18,36,38>
RH207 255 256
+3VS VDDSPD SA0
1K_0402_1%~D 257 258
+2.5V_MEM VPP1 VTT DIMM_CHB_SA1 +0.6VS
259 260
20mil 261 VPP2 SA1 262
2
A GND1 GND2 A
RH485 1 2 2_0402_1% +V_DDR_REFB
1
1 BELLW_SD-80886-1021
RH210 CONN@
CH100 1K_0402_1%~D
0.022U_0402_25V7K
2
2
1
RH212
24.9_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
2
DDRIII DIMMB
5 4 3 2 1

5 4 3 2 1
SKY-S-PCH_BGA837
UH1C
AV2 PCIE_PRX_DTX_N9
CL_CLK G31 PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 <29>
AV3 PCIE9_RXN/SATA0A_RXN
CL_DATA CLINK H31 PCIE_PTX_DRX_N9 PCIE_PRX_DTX_P9 <29>
AW2 PCIE9_RXP/SATA0A_RXP
CL_RST# C31 PCIE_PTX_DRX_P9 PCIE_PTX_DRX_N9 <29>
PCIE9_TXN/SATA0A_TXN B31
R44 PCIE_PTX_DRX_P9 <29>
PCIE9_TXP/SATA0A_TXP M.2 SSD
R43 GPP_G8/FAN_PWM_0
U39 GPP_G9/FAN_PWM_1 G29 PCIE_PRX_DTX_N10 Slot#1
N42 GPP_G10/FAN_PWM_2 PCIE10_RXN/SATA1A_RXN E29 PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 <29>
GPP_G11/FAN_PWM_3 PCIE10_RXP/SATA1A_RXP C32 PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 <29>
FAN PCIE10_TXN/SATA1A_TXN B32 PCIE_PTX_DRX_P10 PCIE_PTX_DRX_N10 <29>
D U43 PCIE10_TXP/SATA1A_TXP PCIE_PTX_DRX_P10 <29> D
U42 GPP_G0/FAN_TACH_0
GPP_G1/FAN_TACH_1 F41 PCIE_PRX_DTX_N15
U41 PCIE15_RXN/SATA2_RXN PCIE_PRX_DTX_P15 PCIE_PRX_DTX_N15 <29>
GPP_G2/FAN_TACH_2 E41
M44 PCIE15_RXP/SATA2_RXP PCIE_PTX_DRX_N15 PCIE_PRX_DTX_P15 <29>
GPP_G3/FAN_TACH_3 B39
U36 PCIE15_TXN/SATA2_TXN PCIE_PTX_DRX_P15 PCIE_PTX_DRX_N15 <29>
GPP_G4/FAN_TACH_4 A39
P44 PCIE15_TXP/SATA2_TXP PCIE_PTX_DRX_P15 <29>
T45 GPP_G5/FAN_TACH_5
GPP_G6/FAN_TACH_6 D43 PCIE_PRX_DTX_N16 M.2 SSD
Slot#2
T44
PCIe/SATA
PCIE16_RXN/SATA3_RXN E42 PCIE_PRX_DTX_P16 PCIE_PRX_DTX_N16 <29>
GPP_G7/FAN_TACH_7
l
PCIE16_RXP/SATA3_RXP A41 PCIE_PTX_DRX_N16 PCIE_PRX_DTX_P16 <29>
M.2 SSD PCIE_PTX_DRX_P11 B33 PCIE16_TXN/SATA3_TXN A40 PCIE_PTX_DRX_P16 PCIE_PTX_DRX_N16 <29>
<29> PCIE_PTX_DRX_P11 PCIE_PTX_DRX_N11 PCIE11_TXP
Slot#1 <29> PCIE_PTX_DRX_N11 PCIE_PRX_DTX_P11
C33
PCIE11_TXN
PCIE16_TXP/SATA3_TXP PCIE_PTX_DRX_P16 <29>
K31
<29> PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11 PCIE11_RXP H42
L31 PCIE17_RXN/SATA4_RXN
ia
<29> PCIE_PRX_DTX_N11 PCIE11_RXN H40 Default
PCIE17_RXP/SATA4_RXP E45
AB33 PCIE17_TXN/SATA4_TXN
GPP_F10/SCLOCK F45
AB35 PCIE17_TXP/SATA4_TXP
AA44 GPP_F11/SLOAD SATAGP0 1 M2_SLOT1_PEDET 0=SATA 1=NoHDD
GPP_F13/SDATAOUT0 K37
AA45 PCIE18_RXN/SATA5_RXN
GPP_F12/SDATAOUT1 G37
t
B38 PCIE18_RXP/SATA5_RXP G45
<36> SATA_PTX_DRX_N1 C38 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN G44
SATAGP1 1 HDD_DET# 0=SATA 1=PCIE
<36> SATA_PTX_DRX_P1 D39 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP
SATA HDD +3VS
<36> SATA_PRX_DTX_N1 E37 PCIE14_RXN/SATA1B_RXN AD44 PCH_SATALED#
<36> SATA_PRX_DTX_P1 PCIE14_RXP/SATA1B_RXP GPP_E8/SATALED# PCH_SATALED# <29,38> SATAGP2 1 M2_SLOT2_PEDET 0=SATA 1=PCIE
n
AG36 M2_SLOT1_PEDET
C36 GPP_E0/SATAXPCIE0/SATAGP0 HDD_DET# M2_SLOT1_PEDET <29>
PCIE13_TXN/SATA0B_TXN AG35
B36 GPP_E1/SATAXPCIE1/SATAGP1 M2_SLOT2_PEDET HDD_DET# <36>
PCIE13_TXP/SATA0B_TXP AG39
G35 GPP_E2/SATAXPCIE2/SATAGP2 M2_SLOT2_PEDET <29>
PCIE13_RXN/SATA0B_RXN AD35
E35 GPP_F0/SATAXPCIE3/SATAGP3
e
PCIE13_RXP/SATA0B_RXP AD31
GPP_F1/SATAXPCIE4/SATAGP4 AD38
PCIE_PTX_DRX_P12 A35 GPP_F2/SATAXPCIE5/SATAGP5
<29> PCIE_PTX_DRX_P12 PCIE_PTX_DRX_N12 PCIE12_TXP AC43 PCH_SATALED#
M.2 SSD B35 GPP_F3/SATAXPCIE6/SATAGP6 1 2
<29> PCIE_PTX_DRX_N12 PCIE_PRX_DTX_P12 PCIE12_TXN AB44
H33 GPP_F4/SATAXPCIE7/SATAGP7 RH512 10K_0402_5%
Slot#1 <29> PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 G33 PCIE12_RXP PCH_INV_PWM HDD_DET# 1 2
id
<29> PCIE_PRX_DTX_N12 PCIE12_RXN W36 PANEL_BKLEN PCH_INV_PWM <25>
J45 GPP_F21/EDP_BKLTCTL W35 RH513 10K_0402_5%
PCH_ENVDD PANEL_BKLEN <43>
K44 PCIE20_TXP GPP_F20/EDP_BKLTEN W42 PCH_ENVDD <25>
N38 PCIE20_TXN GPP_F19/EDP_VDDEN
H_THERMTRIP# RH79 1 2 620_0402_5% H_THERMTRIP#_R
N39 PCIE20_RXP HOST AJ3 H_THERMTRIP#_R <9>
PCIE20_RXN THERMTRIP# PCH_PECI RH73 1 2 12.1_0402_1% H_PECI
H44 AL3 H_PM_SYNC_R H_PECI <9,43>
C PCIE19_TXP PECI C
f
H43 AJ4 PLTRST_CPU# H_PM_SYNC_R <9>
L39 PCIE19_TXN PM_SYNC AK2 H_PM_DOWN PLTRST_CPU# <9>
L37 PCIE19_RXP PLTRST_CPU# AH2 H_PM_DOWN <9>
PCIE19_RXN PM_DOWN
n
SKY-H-PCH_BGA837
REV = 1.3 3 OF 12 RH73 change to 12.1 ohm to fix can't read thermal issue.
@
+5VS
UH1E
C o
2
SKY-S-PCH_BGA837
G
BB3 DDI2_DDPC_CTRLCLK
1 3 DDI1_PCH_HPD AW4 DDI2_DDPC_CTRLCLK <58>
<58> DDI1_PCH_HPD GPP_I7/DDPC_CTRLCLK BD6 DDI2_DDPC_CTRLDAT
DDI2_PCH_HPD AY2 GPP_I0/DDPB_HPD0 DDI2_DDPC_CTRLDAT <58>
GPP_I8/DDPC_CTRLDATA DDI1_DDPB_CTRLCLK
TBT
D
<58> DDI2_PCH_HPD GPP_I1/DDPC_HPD1 BA5

2 @ 1 AV4 GPP_I5/DDPB_CTRLCLK DDI1_DDPB_CTRLDAT DDI1_DDPB_CTRLCLK <58>
<17,27> PCH_HDMI_HPD GPP_I2/DDPD_HPD2 BC4
RH585 0_0402_5% BA4 GPP_I6/DDPB_CTRLDATA DDI1_DDPB_CTRLDAT <58>
QH2 @ GPP_I3/DDPE_HPD3 BE5
GPP_I9/DDPD_CTRLCLK BE6
L
L2N7002WT1G 1N SC-70-3 GPP_I10/DDPD_CTRLDATA
Y44 PROC_DETECT# <9>
GPP_F14 V44 T2 PAD~D @
RH3 GPP_F23 W39
EDP_HPD BD7
CPU_EDP_HPD 2 @ 1 EDP_HPD GPP_F22
<25> CPU_EDP_HPD GPP_I4/EDP_HPD L43 T4 PAD~D @
GPP_G23 L44
1
L
0_0402_5% GPP_G22 U35
GPP_G21 R35
SKL eDP_HPD pull down 100K RH9 GPP_G20 BD36 T8 PAD~D @
100K_0402_5% GPP_H23
2
E
B B
SKY-H-PCH_BGA837
REV = 1.3 5 OF 12
@
+3VS
D
RP1
DDI2_DDPC_CTRLCLK 1 8
DDI2_DDPC_CTRLDAT 2 7
DDI1_DDPB_CTRLCLK 3 6
DDI1_DDPB_CTRLDAT 4 5
r
2.2K_8P4R_5%
A
F o PCH Strap PIN

PCH (1/7) SATA,HDA
SSD
5 4 3 2 1

5 4 3 2 1
UH1G SKY-S-PCH_BGA837
RTC CRYSTAL
PCH_RTCX1
AR17
GPP_A16/CLKOUT_48
L1 PCH_XDP_CLK_N T19 PAD~D @ RH70 1 2 10M_0402_5% PCH_RTCX2
G1 CLKOUT_ITPXDP PCH_XDP_CLK_P T21
<9> CPU_24MHZ_P CLKOUT_CPUNSSC_P L2 PAD~D @ YH1
F1 CLKOUT_ITPXDP_P
<9> CPU_24MHZ_N CLKOUT_CPUNSSC 32.768KHZ_X1A000141000300
J1
CLKOUT_CPUPCIBCLK PCH_CPU_PCIBCLK_N <9>
G2 J2
<9> PCH_CPU_BCLK_P CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_P <9> 1 2
H2
<9> PCH_CPU_BCLK_N CLKOUT_CPUBCLK
N7 CLK_PEG_GPU#
XTAL24_OUT A5 CLKOUT_PCIE_N0 CLK_PEG_GPU CLK_PEG_GPU# <46>
+1V_PCH XTAL24_IN A6 XTAL24_OUT
CLKOUT_PCIE_P0
N8
CLK_PEG_GPU <46> PEG Max Crystal ESR
XTAL24_IN
D
XCLK_BIASREF E1 L7 CLK_PCIE_N1 = 50k Ohm. D
RH71 1 2 2.7K_0402_1% CLKOUT_PCIE_N1 CLK_PCIE_P1 CLK_PCIE_N1 <29> 1 1
XCLK_BIASREF L5 NGFF1 CH45 CH46
CLKOUT_PCIE_P1 CLK_PCIE_P1 <29>
8.2P_0402_50V 8.2P_0402_50V
PCH_RTCX1 BC9
RTCX1 D3 CLK_PCIE_N2
PCH_RTCX2 BD10 CLKOUT_PCIE_N2
RTCX2 F2 CLK_PCIE_P2 CLK_PCIE_N2 <29> 2 2
+3VS PEG <46> CLKREQ#_GPU CLKOUT_PCIE_P2 CLK_PCIE_P2 <29> NGFF2
BC24 CLK_PCIE_N3
RP3 GPP_B5/SRCCLKREQ0# E5
4 5 CLKREQ#_GPU NGFF1 <29> CLKREQ_PCIE#1 AW24
GPP_B6/SRCCLKREQ1#
CLKOUT_PCIE_N3 G4 CLK_PCIE_P3 CLK_PCIE_N3 <58>
TBT
l
CLKREQ_PCIE#1 AT24 CLKOUT_PCIE_P3 CLK_PCIE_P3 <58>
3 6 GPP_B7/SRCCLKREQ2#
2 7 CLKREQ_PCIE#2 NGFF2 <29> CLKREQ_PCIE#2 BD25
GPP_B8/SRCCLKREQ3# D5 CLK_PCIE_N4
CLKREQ_PCIE#4 BB24 CLKOUT_PCIE_N4 CLK_PCIE_P4 CLK_PCIE_N4 <30>
1 8 GPP_B9/SRCCLKREQ4# E6 LAN
TBT <58> CLKREQ_PCIE#3 BE25 CLKOUT_PCIE_P4 CLK_PCIE_P4 <30>
AT33 GPP_B10/SRCCLKREQ5#
ia
10K_0804_8P4R_5% GPP_H0/SRCCLKREQ6# D8 CLK_PCIE_N5
+3VS LAN <30> CLKREQ_PCIE#4 AR31 CLKOUT_PCIE_N5 CLK_PCIE_P5 CLK_PCIE_N5 <28>
GPP_H1/SRCCLKREQ7# D7 WLAN
BD32 CLKOUT_PCIE_P5 CLK_PCIE_P5 <28>
RP5 BC32 GPP_H2/SRCCLKREQ8#
4 5 CLKREQ#_DGPU WLAN <28> CLKREQ_PCIE#5 R8 CLK_PCIE_N6
BB31 GPP_H3/SRCCLKREQ9#
3 6 CLKREQ_PCIE#5 CLKOUT_PCIE_N6 R7 CLK_PCIE_P6 CLK_PCIE_N6 <31> Card Reader
Card Reader <31> CLKREQ_PCIE#6 BC33 GPP_H4/SRCCLKREQ10#
2 7 CLKREQ_PCIE#6 CLKOUT_PCIE_P6 CLK_PCIE_P6 <31>
GPP_H5/SRCCLKREQ11#
t
BA33 CLK_PCIE_N7
1 8 Caldera GPP_H6/SRCCLKREQ12# U5
<41,43> CLKREQ#_DGPU AW33 CLKOUT_PCIE_N7 CLK_PCIE_P7 CLK_PCIE_N7 <41>
BB33 GPP_H7/SRCCLKREQ13#
CLKOUT_PCIE_P7
U7
CLK_PCIE_P7 <41>
Caldera
10K_0804_8P4R_5% BD33 GPP_H8/SRCCLKREQ14#
GPP_H9/SRCCLKREQ15# W10
CLKOUT_PCIE_N8 W11
n
R13 CLKOUT_PCIE_P8
R11 CLKOUT_PCIE_N15
CLKOUT_PCIE_P15 N3 XTAL24_IN
CLKOUT_PCIE_N9 N2
P1 CLKOUT_PCIE_P9
PCIE Diff CLK Req CLKOUT_PCIE_N14 XTAL24_OUT
e
R2 RH72 1 2 1M_0402_5%~D
CLKOUT_PCIE_P14 P3
TBT 1~4 3 CLKOUT_PCIE_N10 P2 YH2
W7 CLKOUT_PCIE_P10
LAN 5 4 Y5 CLKOUT_PCIE_N13
1 3
CLKOUT_PCIE_P13 R3
WLAN 6 5 CLKOUT_PCIE_N11 R4 2 4
id
U2 CLKOUT_PCIE_P11
CR 7 6 U3 CLKOUT_PCIE_N12
CLKOUT_PCIE_P12
NGFF1 9~12 1 24MHZ_12PF_X3G024000DC1H
NGFF2 15~16 2 SKY-H-PCH_BGA837

REV = 1.3 7 OF 12
C 1 1 C
f
@
CH47 CH48
15P_0402_50V 15P_0402_50V
2 2
n
+3VS
o
SKY-S-PCH_BGA837 UH3
UH1A
5
TC7SH08FU_SSOP5
PCH_PLTRST# 1
P
@ PAD~D T17 BD17 BB27 PCH_PLTRST# B 4
GPP_A11/PME# GPP_B13/PLTRST# PCH_PLTRST# <41,46> 2 Y PLT_RST# <28,29,30,31,43,58>
A
1
AG15
P43
C
AG14 RSVD_AG15 TBT_FORCE_PWR <58> RH199
GPP_G16/GSXCLK R39
3
+3V_PCH AF17 RSVD_AG14 100K_0402_5%
GPP_G12/GSXDOUT R36
AE17 RSVD_AF17
GPP_G13/GSXSLOAD R42
RSVD_AE17
GPP_G14/GSXDIN R41
2
RH74 1 @ 2 3.3K_0402_5% PCH_SPI_CS# AR19 GPP_G15/GSXSRESET#
AN17 TP5
RH75 1 2 1K_0402_5% PCH_SPI_WP#_R TP4
AF41 EC_SMI#
PCH_SPI_SI_R BB29 GPP_E3/CPU_GP0 EC_SMI# <43>
PCH_SPI_SO_R SPI0_MOSI AE44
BE30
L
GPP_E7/CPU_GP1 BC23
RH78 1 2 1K_0402_5% PCH_SPI_HOLD#_R PCH_SPI_CS# BD31 SPI0_MISO
GPP_B3/CPU_GP2 BD24
PCH_SPI_CLK_R BC31 SPI0_CS0# +3VS
GPP_B4/CPU_GP3
RH455 1 @ 2 1K_0402_5% PCH_SPI_HOLD#_R PAD~D T18 @ PCH_SPI_CS1# AW31 SPI0_CLK
SPI0_CS1# BC36
PCH_SPI_WP#_R BC29 GPP_H18/SML4ALERT# BE34
PCH_SPI_HOLD#_R
BD30 SPI0_IO2 GPP_H17/SML4DATA BD39 EC_SMI#
L
SPI0_IO3 GPP_H16/SML4CLK 2 1
AT31 BB36
SPI0_CS2# GPP_H15/SML3ALERT# BA35 10K_0402_5% RH110
9/5 MOW <36> FFS_INT1
AN36
GPP_D1/SPI1_CLK
GPP_H14/SML3DATA BC35
RH583 1 @ 2 0_0402_5% AL39 GPP_H13/SML3CLK
Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the <16,27> PCH_HDMI_HPD AN41 GPP_D0/SPI1_CS#
GPP_H12/SML2ALERT#
BD35
<36> FFS_INT2 GPP_D3/SPI1_MOSI AW35
required 1 kOhm pull-up resistor. In this case, customers must ensure that the SPI AN38
GPP_D2/SPI1_MISO
GPP_H11/SML2DATA BD34
E
AH43 GPP_H10/SML2CLK
B flash device on the platform has HOLD functionality disabled by default. RH584 1 2 10K_0402_5% AG44 GPP_D22/SPI1_IO3 BE11 INTRUDER#
B
+3VS GPP_D21/SPI1_IO2 INTRUDER#
Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms NV PULL High, AMD PULL Low.
with ES and SKL S/H platforms with pre-ES1/ES1 samples. SKY-H-PCH_BGA837 1 OF 12 REV = 1.3
@
r D +RTC_CELL
2
15_0804_8P4R_5%
PCH_SPI_HOLD# 4 5 PCH_SPI_HOLD#_R RH531
PCH_SPI_SO 3 6 PCH_SPI_SO_R 1M_0402_5%
o
PCH_SPI_SI 2 7 PCH_SPI_SI_R
PCH_SPI_WP# PCH_SPI_SI_R <6>
1 8 PCH_SPI_WP#_R
1
RPH5 INTRUDER#
PCH_SPI_CLK 1 2 PCH_SPI_CLK_R
F
RH104 EMI@ 15_0402_1%
+3V_PCH
SPI ROM FOR ME ( 16MByte ) 1
PN: SA00005VV10
CH49
0.1U_0402_16V7K~D
A 2 A
UH4
PCH_SPI_CS# 1 8
PCH_SPI_SO 2 /CS VCC 7 PCH_SPI_HOLD#
PCH_SPI_WP# 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK
4 /WP(IO2) CLK 5 PCH_SPI_SI
GND DI(IO0)
W25Q128FVSIQ_SO8

PCH (2/7) SMBUS, CLK, SPI, LPC
5 4 3 2 1

5 4 3 2 1
HDA for Codec and MDC RP2

HDA_SYNC Isolat i +5VS
on Circ uit
1 8
2
7 PCH_AZ_SDOUT
G
2 +3V_PCH_DSW
<32> PCH_AZ_CODEC_SDOUT 3 6 PCH_AZ_SYNC_Q
<32> PCH_AZ_CODEC_SYNC 4 5 PCH_AZ_RST# PCH_AZ_SYNC_Q 3 1 PCH_AZ_SYNC
<32> PCH_AZ_CODEC_RST#
D
33_0804_8P4R_5%
1M_0402_5%
WAKE# RH453 1 2 10K_0402_5%
2
1 2 PCH_AZ_BITCLK QH1
<32> PCH_AZ_CODEC_BITCLK PCH_BATLOW#
RH20
RH29 33_0402_5% L2N7002WT1G 1N SC-70-3 RH515 1 2 8.2K_0402_5%
27P_0402_50V8J~D
SKY-S-PCH_BGA837 AC_PRESENT
@ CH6
1 UH1D RH533 1 2 8.2K_0402_5%
1
D WAKE_PCH# RH545 1 2 10K_0402_5% D
PCH_AZ_BITCLK BA9 BB17
2 PCH_AZ_RST# BD8 HDA_BCLK GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AW22 CLKRUN#
PCH_AZ_CODEC_SDIN0 BE7 HDA_RST# GPP_A8/CLKRUN# +3V_PCH
<32> PCH_AZ_CODEC_SDIN0 BC8 HDA_SDI0 AR15
HDA_SDI1 GPD11/LANPHYPC
RH16 1 2 1K_0402_1% PCH_AZ_SDOUT BB7 AV13
<43> ME_EN PCH_AZ_SYNC BD9 HDA_SDO GPD9/SLP_WLAN# ME_SUS_PWR_ACK RH506 1 @ 2 1M_0402_5%
l
HDA_SYNC BC14
DRAM_RESET# H_DRAMRST# <14> SYS_RESET#
BD1 BD23 RH571 1 @ 2 8.2K_0402_5%
BE2 RSVD_BD1 GPP_B2/VRALERT# AL27
RSVD_BE2 GPP_B1 AR27
GPP_B0
ia
+RTC_CELL AUD_AZACPU_SDO 1 2 AUD_AZACPU_SDO_R AM1 AUDIO
N44 +3VS
<7> AUD_AZACPU_SDO AUD_AZACPU_SDI_R RH39 AN2 DISPA_SDO GPP_G17/ADR_COMPLETE AN24
30_0402_5%
PCH_SRTCRST# <7> AUD_AZACPU_SDI_R AUD_AZACPU_SCLK AUD_AZACPU_SCLK_R DISPA_SDI GPP_B11 SYS_PWROK
RH83 1 2 20K_0402_5%~D 1 2 AM2 AY1
<7> AUD_AZACPU_SCLK DISPA_BCLK SYS_PWROK SYS_PWROK <43>
RH38 30_0402_5% CLKRUN# RH85 1 2 8.2K_0402_5%
1 BC13 WAKE# 2 RH4@ 1 PCIE_WAKE#
@ PAD~D T120 AL42 WAKE# PCIE_WAKE# <29,30,43>
CH52 GPP_D8/SSP0_SCLK BC15
t
1U_0402_10V @ PAD~D T121 AN42 GPD6/SLP_A# 0_0402_5%
GPP_D7/SSP0_RXD AV15 T20 PAD~D @
@ PAD~D T122 AM43 SLP_LAN# PM_SLP_S0#
GPP_D6/SSP0_TXD BC26
2 @ PAD~D T123 AJ33 GPP_B12/SLP_S0# PM_SLP_S3# PM_SLP_S0# <43>
GPP_D5/SSP0_SFRM AW15
@ PAD~D T124 AH44 GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# <37,43,45>
GPP_D20/DMIC_DATA0 BD15 PM_SLP_S4# <43,45,65>
AJ35 GPD5/SLP_S4# PM_SLP_S5#
BA13
n
AJ38 GPP_D19/DMIC_CLK0 PM_SLP_S5# <37,43>
GPD10/SLP_S5# +3V_PCH
@ PAD~D T127 AJ42 GPP_D18/DMIC_DATA1
GPP_D17/DMIC_CLK1 AN15
+RTC_CELL GPD8/SUSCLK PCH_BATLOW# SUSCLK <28,29>
BD13
GPD0/BATLOW# PCH_BATLOW# <58> HDA_SPKR
BB19 RH82 1 @ 2 4.7K_0402_5%
e
PCH_RTCRST# PCH_RTCRST# GPP_A15/SUSACK# ME_SUS_PWR_ACK SUSACK# <43>
RH84 1 2 20K_0402_5%~D BC10 BD19
ME_SUS_PWR_ACK <43>
PCH_SRTCRST# BB10 RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK
SRTCRST#
1
1
PCH_PWROK AW11 BD11 WAKE_PCH#

<43,71> PCH_PWROK 1 2 0_0402_5% PCH_RSMRST#_R BA11 PCH_PWROK GPD2/LAN_WAKE# BB15 AC_PRESENT WAKE_PCH# <43> 2 1 DH1
CH53 CLRP1 RH133 @
id
<43> PCH_RSMRST# RSMRST# GPD1/ACPRESENT PM_SLP_SUS# ACIN <37,43,46,61,62>
1U_0402_10V SHORT PADS BB13 SDMK0340L-7-F_SOD323-2
PM_SLP_SUS# <43>
2
2 SLP_SUS# AT13 PBTN_OUT#

1 @ 2 PCH_DPWROK_R AV11 PBTN_OUT# <6,43>
<43> PCH_DPWROK GPD3/PWRBTN# AW1 SYS_RESET#
RH309 0_0402_5% SMBALERT# BB41 DSW_PWROK SYS_RESET# <6>
SYS_RESET# BD26 HDA_SPKR
PCH_SMBCLK GPP_C2/SMBALERT#
SMBUS
AW44 GPP_B14/SPKR H_CPUPWRGD HDA_SPKR <32>
PCH to DDR, XDP, FFS <14,15,36,38> PCH_SMBCLK PCH_SMBDATA GPP_C0/SMBCLK AM3
BB43 PROCPWRGD H_CPUPWRGD <9>
C <14,15,36,38> PCH_SMBDATA GPP_C1/SMBDATA C
f
SML0ALERT# BA40 PCH_ITP_PMODE
GPP_C5/SML0ALERT# AT2 PCH_ITP_PMODE <6>
SML0CLK AY44 ITP_PMODE XDP_TCK
<41> SML0CLK GPP_C3/SML0CLK AR3
SML0DATA BB39 JTAGX XDP_TMS XDP_TCK <6,9>
<41> SML0DATA GPP_C4/SML0DATA J TAG AR2
SML1ALERT# AT27 JTAG_TMS XDP_TDO XDP_TMS <6,9>
GPP_B23/SML1ALERT#/PCHHOT# AP1 Connect CPU & PCH
SML1CLK AW42 JTAG_TDO XDP_TDI XDP_TDO <6,9>
GPP_C6/SML1CLK AP2
n
SML1DATA AW45 JTAG_TDI PCH_JTAG_TCK XDP_TDI <6,9>
GPP_C7/SML1DATA AN3
+3V_PCH JTAG_TCK PCH_JTAG_TCK <6>
+3V_PCH
1/14 Pull High value checking.... SKY-H-PCH_BGA837 REV = 1.3 4 OF 12
o
@
RH460 1 2 1K_0402_5% SML1CLK
RH461 1 2 1K_0402_5% SML1DATA RH505 1 @ 2 1K_0402_5% SMBALERT#
RH501 1 2 499_0402_1% SML0CLK
RH502 1 2 499_0402_1% SML0DATA
High = VPRO
Low = Non-VPRO
C
+3VS
RH463 1 2 1K_0402_5% PCH_SMBCLK

RH462 1 2 1K_0402_5% PCH_SMBDATA
+3V_PCH
L
RH503 1 @ 2 1K_0402_5% SML0ALERT#
High = eSPI
Low = LPC
L
Follow PDG 10k pull down.
RH88 1 2 10K_0402_5% PCH_RSMRST#_R
RH90 1 2 100K_0402_5% PCH_DPWROK_R
E
B B
+3VS
+3V_PCH
D
2
RH504 1 @ 2 10K_0402_5% SML1ALERT#

SML1CLK 6 1
EC_SMB_CK2 <41,42,43,46,60>
QH5A
5
r
DMN66D0LDW-7_SOT363-6
SML1DATA 3 4
EC_SMB_DA2 <41,42,43,46,60>
QH3B
o
A
F A

PCH (3/7) DMI,FDI,PM,GFX,DP
5 4 3 2 1

5 4 3 2 1
SKY-S-PCH_BGA837
UH1B
DMI_CTX_PRX_N0
<7> DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 L27 USB20_N1
DMI_RXN0 AF5
<7> DMI_CTX_PRX_P0 DMI_CRX_PTX_N0 N27
DMI_RXP0
USB2N_1 AG7 USB20_P1 USB20_N1 <34> ----->Right Side JUSB1
<7> DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 C27 USB2P_1 USB20_N2 USB20_P1 <34>
DMI_TXN0 AD5
D <7> DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 B27
DMI_TXP0
USB2N_2 AD7 USB20_P2 USB20_N2 <35> ----->Left Side JUSB3 PowerShare (Debug Port) D
<7> DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 E24 USB2P_2 USB20_N3 USB20_P2 <35>
DMI_RXN1 AG8
<7> DMI_CTX_PRX_P1 DMI_CRX_PTX_N1 G24
DMI_RXP1
USB2N_3 AG10 USB20_P3 USB20_N3 <41> ----->Cladera
<7> DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 B28 USB2P_3 USB20_N4 USB20_P3 <41>
DMI_TXN1 AE1
<7> DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 A28
DMI_TXP1 DMI
USB2N_4 AE2 USB20_P4 USB20_N4 <37> ----->ELC
<7> DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 G27 USB2P_4 USB20_N5 USB20_P4 <37>
DMI_RXN2 AC2
<7> DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 E26
DMI_RXP2
USB2N_5 AC3 USB20_P5 USB20_N5 <28> ----->WLAN BT
<7> DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 B29 USB2P_5 USB20_N6 USB20_P5 <28>
DMI_TXN2 AF2
----->Touch Screen
l
<7> DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 C29 USB2N_6 USB20_P6 USB20_N6 <25>
DMI_TXP2 AF3
<7> DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 L29 USB2P_6 USB20_N7 USB20_P6 <25>
DMI_RXN3 AB3
<7> DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 K29
DMI_RXP3 USB 2.0
USB2N_7 AB2 USB20_P7 USB20_N7 <25> ----->Camera
<7> DMI_CRX_PTX_N3 DMI_CRX_PTX_P3 B30 USB2P_7 USB20_P7 <25>
DMI_TXN3 AL8
<7> DMI_CRX_PTX_P3 A30 USB2N_8 ----->Right Side JUSB2 (TypeC)
ia
DMI_TXP3 AL7
1 2 PCIECOMP# USB2P_8 AA1 USB20_N9
RH193 100_0402_1% PCIECOMP
B18
PCIE_RCOMPN
USB2N_9 AA2 USB20_P9 USB20_N9 <35> ----->Left Side JUSB4
C17 USB2P_9 USB20_P9 <35>
PCIE_RCOMPP AJ8
USB2N_10 AJ7
PCIE_PRX_DTX_N1 H15 USB2P_10 W2
t
<58> PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 G15 PCIE1_RXN/USB3_7_RXN USB2N_11 W3
<58> PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 A16 PCIE1_RXP/USB3_7_RXP USB2P_11 AD3
<58> PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1 B16 PCIE1_TXN/USB3_7_TXN USB2N_12 AD2
PCIe/USB 3
<58> PCIE_PTX_DRX_P1 PCIE_PTX_DRX_N2 B19 PCIE1_TXP/USB3_7_TXP USB2P_12 V2
<58> PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2 C19 PCIE2_TXN/USB3_8_TXN USB2N_13 V1
n
<58> PCIE_PTX_DRX_P2 PCIE_PRX_DTX_N2 E17 PCIE2_TXP/USB3_8_TXP USB2P_13 AJ11
<58> PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 G17 PCIE2_RXN/USB3_8_RXN USB2N_14 AJ13
PCIe1~4:TBT <58> PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N3 PCIE2_RXP/USB3_8_RXP USB2P_14
L17
<58> PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 K17 PCIE3_RXN/USB3_9_RXN +3V_PCH
e
<58> PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 B20 PCIE3_RXP/USB3_9_RXP
<58> PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3 C20 PCIE3_TXN/USB3_9_TXN USB_OC0# RPH6
<58> PCIE_PTX_DRX_P3 PCIE_PRX_DTX_N4 PCIE3_TXP/USB3_9_TXP AD43 USB_OC0# <34>
E20 GPP_E9/USB2_OC0# 1 8
<58> PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE4_RXN/USB3_10_RXN AD42 USB_OC2#
G19 GPP_E10/USB2_OC1# 2 7
<58> PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE4_RXP/USB3_10_RXP AD39 USB_OC2# <32> USB_OC2#
B21 GPP_E11/USB2_OC2# 3 6
id
<58> PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 PCIE4_TXN/USB3_10_TXN AC44 USB_OC0#
A21 GPP_E12/USB2_OC3# 4 5
<58> PCIE_PTX_DRX_P4 PCIE_PRX_DTX_N5 PCIE4_TXP/USB3_10_TXP Y43
K19 GPP_F15/USB2_OCB_4
<30> PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE5_RXN Y41
L19 GPP_F16/USB2_OCB_5 10K_8P4R_5%
<30> PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE5_RXP W44
PCIe5:LAN D22 GPP_F17/USB2_OCB_6
<30> PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5 PCIE5_TXN W43
C22 GPP_F18/USB2_OCB_7
C
<30> PCIE_PTX_DRX_P5 PCIE_PRX_DTX_N6 G22 PCIE5_TXP C
f
<28> PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 E22 PCIE6_RXN
<28> PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE6_RXP AG3 USB2_COMP RH109 1 2 113_0402_1%
PCIe6:WLAN B22 USB2_COMP
<28> PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6 PCIE6_TXN AD10 1 2
A23 USB2_VBUSSENSE
<28> PCIE_PTX_DRX_P6 PCIE_PRX_DTX_N7 PCIE6_TXP AB13 RH580 1K_0402_5%
L22 RSVD_AB13
<31> PCIE_PRX_DTX_N7 PCIE_PRX_DTX_P7 PCIE7_RXN AG2 1 2
K22 USB2_ID
n
<31> PCIE_PRX_DTX_P7 PCIE_PTX_DRX_N7 C23 PCIE7_RXP RH581 1K_0402_5%
PCIe7:CR <31> PCIE_PTX_DRX_N7 PCIE_PTX_DRX_P7 PCIE7_TXN
B23 Change to 1K pull down.
<31> PCIE_PTX_DRX_P7 K24 PCIE7_TXP BD14
L24 PCIE8_RXN GPD7/RSVD
C24 PCIE8_RXP
o
B24 PCIE8_TXN
PCIE8_TXP
SKY-H-PCH_BGA837
REV = 1.3 2 OF 12
@
L C
L
UH1F SKY-S-PCH_BGA837
C11 AT22
LPC/eSPI
<34> USB3TN1 USB3_1_TXN GPP_A1/LAD0/ESPI_IO0 LPC_AD0 <43>

B11 AV22
<34> USB3TP1 USB3_1_TXP GPP_A2/LAD1/ESPI_IO1 LPC_AD1 <43>
E
Right Side JUSB1 B7 AT19
B <34> USB3RN1 USB3_1_RXN GPP_A3/LAD2/ESPI_IO2 LPC_AD2 <43> +3VS B
A7 BD16
<34> USB3RP1 USB3_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <43>
B12
USB3_2_TXN/SSIC_1_TXN SERIRQ 1 2
A12 BE16
USB3_2_TXP/SSIC_1_TXP GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# <43> RH111 10K_0402_5%~D
C8 BA17 SERIRQ KB_RST#
USB3_2_RXN/SSIC_1_RXN GPP_A6/SERIRQ SERIRQ <43> 1 2
B8 AW17
USB3_2_RXP/SSIC_1_RXP GPP_A7/PIRQA#/ESPI_ALERT0# AT17 KB_RST# RH518 10K_0402_5%~D
B15 KB_RST# <43>
D
GPP_A0/RCIN#/ESPI_ALERT1# BC18
C15 USB3_6_TXN
GPP_A14/SUS_STAT#/ESPI_RESET#
K15 USB3_6_TXP
USB3_6_RXN
USB
K13 BC17 RH89 2 1 22_0402_5%

USB3_6_RXP GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_LPC <43>
AV19
<41> USB3TN5 B14 GPP_A10/CLKOUT_LPC1
<41> USB3TP5 C14 USB3_5_TXN
r
Caldera USB3_5_TXP M45
<41> USB3RN5 G13 GPP_G19/SMI#
USB3_5_RXN N43
<41> USB3RP5 H13 GPP_G18/NMI#
USB3_5_RXP
<35> USB3TP3 D13
USB3_3_TXP/SSIC_2_TXP AE45 JSSD2 DVESLP
<35> USB3TN3 C13 DEVSLP2 <29>
o
GPP_E6/DEVSLP2 AG43
Left Side JUSB3 <35> USB3RP3 A9 USB3_3_TXN/SSIC_2_TXN
GPP_E5/DEVSLP1 AG42
<35> USB3RN3 B10 USB3_3_RXP/SSIC_2_RXP DEVSLP0 <29>
GPP_E4/DEVSLP0 AB39 JSSD0 DVESLP
USB3_3_RXN/SSIC_2_RXN
GPP_F9/DEVSLP7 AB36
B13
SATA
<35> USB3TP4 GPP_F8/DEVSLP6 AB43

<35> USB3TN4 A14 USB3_4_TXP
GPP_F7/DEVSLP5 AB42
F
Left Side JUSB4 <35> USB3RP4 G11 USB3_4_TXN
GPP_F6/DEVSLP4 AB41
<35> USB3RN4 E11 USB3_4_RXP
GPP_F5/DEVSLP3
USB3_4_RXN
SKY-H-PCH_BGA837
REV = 1.3 6 OF 12
@
A A

PCH (4/7) PCI, USB
5 4 3 2 1

5 4 3 2 1
+3VS
SKY-S-PCH_BGA837
UH1K
BBS_BIT0 AT29
GPP_B22/GSPI1_MOSI AL44
+3VS AR29 GPP_D9
EC_SCI# GPP_B21/GSPI1_MISO AL36
AV29 GPP_D10 DGPU_HOLD_RST# <46>
<43> EC_SCI# GPP_B20/GSPI1_CLK AL35
BC27 GPP_D11 DGPU_PWR_EN DGPU_PWR_EN
GPP_B19/GSPI1_CS# AJ39 RH537 1 2 10K_0402_5%~D
NRB_BIT GPP_D12 DGPU_PWR_EN <49,68>
BD28
RH517 1 2 8.2K_0402_5% BT_OFF# BD27 GPP_B18/GSPI0_MOSI AJ43
RH520 1 @ 2 8.2K_0402_5% WL_OFF# AW27 GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS# AL43
1 2 10K_0402_5% EC_SCI# <46> GPU_GC6_FB_EN AR24 GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS# AK44
RH521 <46> GC6_EVENT# GPP_B15/GSPI0_CS# GPP_D14/ISH_UART0_TXD AK45
RC62 2 1 49.9K_0402_1% UART_2_CRXD_DTXD PD_PWR_EN RH582 1 @ 2 0_0402_5% AV44 GPP_D13/ISH_UART0_RXD
<43,60> PD_PWR_EN GPP_C9/UART0_TXD
D
RC63 2 1 49.9K_0402_1% UART_2_CTXD_DRXD BA41 D
WL_OFF# AU44 GPP_C8/UART0_RXD
<28> WL_OFF# GPP_C11/UART0_CTS#
RC65 2 @ 1 49.9K_0402_1% UART_2_CCTS_DRTS BT_OFF# AV43
<28> BT_OFF# GPP_C10/UART0_RTS#
AU41 BC38
AT44 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H20/ISH_I2C0_SCL BB38
AT43 GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_H19/ISH_I2C0_SDA
AU43 GPP_C13/UART1_TXD/ISH_UART1_TXD BD38
l
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H22/ISH_I2C1_SCL BE39
TBT_CIO_PLUG_EVENT# AN43 GPP_H21/ISH_I2C1_SDA
<58> TBT_CIO_PLUG_EVENT# UART_2_CCTS_DRTS GPP_C23/UART2_CTS#
AN44
UART_2_CTXD_DRXD AR39 GPP_C22/UART2_RTS#
<28> UART_2_CTXD_DRXD GPP_C21/UART2_TXD
ia
UART_2_CRXD_DTXD AR45 BC22
Win7 Debug <28> UART_2_CRXD_DTXD GPP_C20/UART2_RXD GPP_A23/ISH_GP5 BD18
RTD3_USB_PWR_EN AR41 GPP_A22/ISH_GP4 BE21
+3VS <58> RTD3_USB_PWR_EN RTD3_CIO_PWR_EN AR44 GPP_C19/I2C1_SCL GPP_A21/ISH_GP3 BD22 KB_DET#
<58> RTD3_CIO_PWR_EN AR38 GPP_C18/I2C1_SDA GPP_A20/ISH_GP2 BD21 KB_DET# <39>
AT42 GPP_C17/I2C0_SCL GPP_A19/ISH_GP1 BB22 CLKDET#
t
GPP_C16/I2C0_SDA GPP_A18/ISH_GP0 BC19 DGPU_PRSNT# +3V_PCH
DGPU_PWROK AM44 GPP_A17/ISH_GP7
RH516 1 2 10K_0402_5% DGPU_PWROK GPP_D4/ISH_I2C2_SDA
AJ44
<43> DGPU_PWROK GPP_D23/ISH_I2C2_SCL
n
KB_DET# RH557 1 2 10K_0402_5%~D
SKY-H-PCH_BGA837
REV = 1.3 11 OF 12
@ CLKDET# RH558 1 @ 2 10K_0402_5%~D
C
For BIOS setting dGPU present
* LOW - dGPU exist
id e +3V_PCH
RH130 1 @ 2 4.7K_0402_5%~D
Boot BIOS Strap Bit (internal PD)

BBS_BIT0
f
+3VS
@
HIGH LPC
1 2 DGPU_PRSNT# LOW(DEFAULT) SPI
RH134 10K_0402_5%
n
1 2 DGPU_PRSNT#
RH135 10K_0402_5%
o
+3V_PCH
RH524 1 @ 2 4.7K_0402_5%~D NRB_BIT
C
NO REBOOT mode (internal PD)
HIGH Enable
LOW(DEFAULT) Disable
L L
E
B B
r D
A
F o A

PCH (5/7) GPIO, CPU, MISC
5 4 3 2 1

5 4 3 2 1
+1VALW @ +1V_PCH
JP1
+1VALW @
1 2 SKY-S-PCH_BGA837
UH1H
JP2
+1V_PCH
PAD-OPEN 43x39 1 2 +1V_PCH_PRIM AA23
+1V_MPHY AA26 VCCPRIM_1P0_AA23 +3V_PCH_DSW
PAD-OPEN 43x39 AA28 VCCPRIM_1P0_AA26 AL22
VCCPRIM_1P0_AA28 VCCPRIM_1P0_AL22
CORE
AC23
RZ70 1 @ 2 0_0805_5% AC26 VCCPRIM_1P0_AC23 BA24
AC28 VCCPRIM_1P0_AC26 VCCDSW_3P3_BA24
VCCPRIM_1P0_AC28 BA31
VCCGPIO
D D
AE23 VCCPGPPA
+1V_PCH +1.0V_VCCDSW AE26 VCCPRIM_1P0_AE23 BC42
Y23 VCCPRIM_1P0_AE26 VCCPGPPBH_BC42 BD40
+3VALW RH196 Y25 VCCPRIM_1P0_Y23 VCCPGPPBH_BD40 AJ41 +3V_PCH
+3V_PCH_DSW 1 @ 2 +1V_VCCDSW BA29 VCCPRIM_1P0_Y25 VCCPGPPEF_AJ41 AL41
DCPDSW_1P0 VCCPGPPEF_AL41 AD41
1 @ 2 0_0402_5% N17 VCCPGPPG AN5
RH137 0_0603_5% R19 VCCCLK1 VCCPRIM_3P3_AN5
l
U20 VCCCLK3 +1V_PCH
V17 VCCCLK4 AD15
R17 VCCCLK2 VCCPRIM_1P0_AD15 AD13
VCCCLK6 VCCATS +3VS
BA20
K2 VCCRTCPRIM_3P3
ia
VCCCLK5_K2 BA22
+1V_MPHY K3 VCCRTC +RTC_CELL
VCCCLK5_K3 BA26 1 2
DCPRTC CH70 0.1U_0402_10V7K~D
U21 +1V_PCH_PRIM Follow TD-Team
VCCMPHY_1P0_U21 AJ20
MPHY
U23 VCCPRIM_1P0_AJ20
U25 VCCPRIM_1P0_AJ21
t
U26 VCCPRIM_1P0_AJ23 +3V_PCH
V26 VCCPRIM_1P0_AJ25
A43 VCCMPHY_1P0_V26
B43 VCCMPHYPLL_1P0_A43 BE41 +3V_PCH_SPI 2 @ 1
C44 VCCMPHYPLL_1P0_B43 VCCSPI_BE41 BE43
n
+1V_PCH 0_0603_5% RH136 +3V_PCH
C45 VCCPCIE3PLL_1P0_C44 VCCSPI_BE43 BE42
VCCPCIE3PLL_1P0_C45 VCCSPI_BE42
V28 BC44
AC17 VCCAPLLEBB_1P0 VCCPGPPCD_BC44 BA45
USB
VCCPRIM_1P0_AC17 VCCPGPPCD_BA45
e
AJ5 BC45
+3V_PCH AL5 VCCUSB2PLL_1P0_AJ5 VCCPGPPCD_BC45 BB45
+3V_PCH_DSW AN19 VCCUSB2PLL_1P0_AL5 VCCPGPPCD_BB45 +3V_PCH +3VS
VCCHDAPLL_1P0 BD3 +3V_PCH +3V_PCH
BA15 VCCPRIM_3P3_BD3
VCCHDA BE3
VCCPRIM_3P3_BE3 Close to AN5 Close to AD13 Close to BA20
id
W15 BE4
VCCDSW_3P3_W15 VCCPRIM_3P3_BE4
1U_0402_6.3V
1U_0402_6.3V
Close to BA29 +3V_PCH
SKY-H-PCH_BGA837
0.1U_0402_10V7K
0.1U_0402_10V7K
+1V_PCH REV = 1.3 8 OF 12 1 1 1 1
+1V_VCCDSW
CH188
CH187
Close to AC17 Close to BA15 @
CH189
CH186
C C
f
0.1U_0402_10V7K
2 2 2 2
1U_0402_6.3V
1U_0402_6.3V
CH200
1 1 1
CH176
CH185
n
2 2 2
+1V_PCH
Close to K2,K3
+1V_MPHY
Close to A43,B43
+1V_MPHY
Close to U21,U23,U25,U26,V26
C o +3V_PCH
Close to AD41
0.1U_0402_10V7K
1
CH190
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
L
1 1 1 1 1 1 1 1
CH179
CH180
CH183
CH177
CH178
CH181
CH182
CH184
2 2 2 2 2 2 2 2
E L +3V_PCH
Close to BC42,BD40
+3V_PCH
Close to AJ41,AL41
B
0.1U_0402_10V7K
0.1U_0402_10V7K
+RTC_CELL
1 1
D
+3V_PCH_DSW Close to BA22
CH192
CH191
Close to W15 2 2
1U_0402_6.3V
1U_0402_6.3V
0.1U_0402_10V7K
1 1 1
r
CH82
CH80
CH173
2 2 2
A
F o A

PCH (6/7) PWR
5 4 3 2 1

5 4 3 2 1
UH1LSKY-S-PCH_BGA837
UH1I
SKY-S-PCH_BGA837
C42 AB11
AC18 AR5 VSS VSS
VSS VSS D10 AB7
AN4 AR7 VSS VSS
VSS VSS D12 AB14
AN10 U15 VSS VSS
VSS VSS D15 AB31
BE14 AL4 VSS VSS
VSS VSS D16 AB32
BE18 AE29 VSS VSS
VSS VSS D17 AB38
BE23 AE4 VSS VSS
VSS VSS D19 AB4
D BE28 AE42 VSS VSS D
VSS VSS D21 AB5
BE32 AF18 VSS VSS
VSS VSS D24 AC1
BE37 AF20 VSS VSS
VSS VSS D25 AC20
BE40 AF21 VSS VSS
VSS VSS D27 AC21
BE9 AF23 VSS VSS
VSS VSS D29 AC25
C10 AF25 VSS VSS
VSS VSS D30 AC29
C2 AF26 VSS VSS
VSS VSS D31 AC45
l
C28 AF28 VSS VSS
VSS VSS D33 AB8
C37 AF29 VSS VSS
VSS VSS D35 AD11
J7 AG11 VSS VSS
VSS VSS D36 AD14
K10 AG13 VSS VSS
ia
VSS VSS E13 AB15
K27 AG31 VSS VSS
VSS VSS E15 AD32
K33 AG32 VSS VSS
VSS VSS E31 AD33 SKY-S-PCH_BGA837
K36 AG33 VSS VSS UH1J
VSS VSS E33 AD36
K4 AG38 VSS VSS
VSS VSS F44 AD4
K42 AG4
t
F8 VSS VSS AD8
K43 VSS VSS AH1
G42 VSS VSS AE18
L12 VSS VSS AH17 BD2 AR22
G9 VSS VSS AE20
L13 VSS VSS AH18 BD45 VSS_BD2 RSVD_AR22 W13
H17 VSS VSS AE21
L15 VSS VSS AH20 BD44 VSS_BD45 RSVD_W13 U13
VSS VSS
n
VSS VSS H19 AE25 VSS_BD44 RSVD_U13
L4 AH21 VSS VSS BE44
VSS VSS H22 AE28 VSS_BE44 P31
L41 AH23 VSS VSS D45 RSVD_P31
VSS VSS H24 AL10 VSS_D45 N31
L8 AH25 VSS VSS A42 RSVD_N31
VSS VSS H27 AL11 VSS_A42
M35 AH26 B45 P27
e
H29 VSS VSS AL13
M42 VSS VSS AH28 B44 VSS_B45 RSVD_P27 R27
H3 VSS VSS AL17
N10 VSS VSS AH29 A4 VSS_B44 RSVD_R27 N29
H35 VSS VSS AL19
N15 VSS VSS AH45 A3 VSS_A4 RSVD_N29 P29
J10 VSS VSS AL24
N19 VSS VSS AJ10 B2 VSS_A3 RSVD_P29 AN29
VSS VSS
id
VSS VSS J11 AL29 VSS_B2 RSVD_AN29
N22 AJ14 VSS VSS A2 R24
VSS VSS J3 AL32 VSS_A2 RSVD_R24
N24 AJ15 VSS VSS B1 P24
VSS VSS J39 AL33 VSS_B1 RSVD_P24
N35 AJ17 VSS VSS BB1
VSS VSS J5 AL38 VSS_BB1 AT3 XDP_PREQ# <9>
N36 AJ18 VSS VSS BC1 PREQ#
C VSS VSS T42 AM15 VSS_BC1 AT4 XDP_PRDY# <9> C
N4 AJ26 VSS VSS A44 PRDY#
U10 AM17 AY5
f
N41 VSS VSS AJ28 VSS_A44 CPU_XDP_TRST# <6,9>
U11 VSS VSS AM19 C1 CPU_TRST# AL2
N5 VSS VSS AJ29 PCH_TRIGGER <9>
U14 VSS VSS AM22 D1 RSVD_C1 PCH_TRIGOUT AK1
P17 VSS VSS AJ31 CPU_TRIGGER <9>
U17 VSS VSS AM24 RSVD_D1 PCH_TRIGIN
P19 VSS VSS AJ32
U18 VSS VSS AM27
VSS VSS
n
P22 AJ36 VSS VSS
VSS VSS U28 AM29
P45 AK4 VSS VSS
VSS VSS U29 AM45
R10 AK42 VSS VSS
VSS VSS U31 AN11 SKY-H-PCH_BGA837
R14 AU7 VSS VSS REV = 1.3 10 OF 12
VSS VSS U32 AN22
o
R22 AV17 VSS VSS @
VSS VSS U33 AN27
R29 AV24 VSS VSS
VSS VSS U38 AN31
R33 AV27 VSS VSS
VSS VSS U4 AN39
R38 AV31 VSS VSS
VSS VSS U8 AN7
R5 AV33 VSS VSS
VSS VSS V18 AN8
T1 AV6 VSS VSS
V20 AP11
C
T2 VSS VSS AW13
V21 VSS VSS AP4
T4 VSS VSS AW19
V23 VSS VSS AR33
Y18 VSS VSS AW29
V25 VSS VSS AR34
Y20 VSS VSS AW37
V29 VSS VSS AR42
Y21 VSS VSS AW9
V3 VSS VSS AR9
Y26 VSS VSS AY38
V45 VSS VSS AT10
Y28 VSS VSS AY45
W14 VSS VSS AT15
VSS VSS
L
Y29 B25 VSS VSS
VSS VSS W31 AT36
A18 B3 VSS VSS
VSS VSS W32 AT9
A25 B37 VSS VSS
VSS VSS W33 AU1
A32 B40 VSS VSS
VSS VSS W38 AU35
A37 B6 VSS VSS
VSS VSS W4 AU36
AA17 BA1
L
W8 VSS VSS AU39
AA18 VSS VSS BB11
Y17 VSS VSS AU45
AA20 VSS VSS BB16 VSS VSS C4
AA21 VSS VSS BB21 VSS
AA25 VSS VSS BB25
B AA29 VSS VSS BB30 B
E
AA4 VSS VSS BB34
AA42 VSS VSS BC2
AB10 VSS VSS BD43
VSS VSS SKY-H-PCH_BGA837
12 OF 12 REV = 1.3
@
D
SKY-H-PCH_BGA837
REV = 1.3 9 OF 12
@
o r
A
F A

PCH (7/7) VSS
5 4 3 2 1

5 4 3 2 1
D D
ia l
n t
C
Empty page id e C
n f
C o
B
L L B
D E
o r
A
F A

Reserved Page
5 4 3 2 1

5 4 3 2 1
D D
ia l
n t
C
id e C
Empty page n f
C o
B
L L B
D E
o r
A
F A

Reserved Page
5 4 3 2 1

A B C D E
eDP connector
LCD power control
JEDP1
0.1U_0402_16V7K 2 1 CV1 EDP_TX0_C 1
<7> CPU_EDP_TX0P EDP_TX0#_C 1
0.1U_0402_16V7K 2 1 CV2 2 41
+3VS +LCDVDD +LCDVDD_CONN <7> CPU_EDP_TX0N 2 G1
3 42
EDP_TX1_C 3 G2
W=60mils
0.1U_0402_16V7K 2 1 CV3 4 43
<7> CPU_EDP_TX1P EDP_TX1#_C 4 G3
W=60mils
UV17 0.1U_0402_16V7K 2 1 CV4 5 44
<7> CPU_EDP_TX1N 5 G4
5 1 RV480 1 @ 2 0_0603_5% 2 1 DISPOFF# 6
IN OUT <43> BKOFF# EDP_TX2_C 6
0.1U_0402_16V7K 2 1 CV8 7
<7> CPU_EDP_TX2P 7
1
2 DV1 0.1U_0402_16V7K 2 1 CV6 EDP_TX2#_C 8
1 GND <7> CPU_EDP_TX2N 8
0.1U_0402_10V7K
CV9
4.7U_0603_10V
CV10
1 SDMK0340L-7-F_SOD323-2 9 1
CV5 4 3 1 2 10K_0402_5% 0.1U_0402_16V7K 2 1 CV7 EDP_TX3_C 10 9
EN OC +3VS 1 1 <7> CPU_EDP_TX3P 10
4.7U_0603_10V RV45 10K_0402_5% RV1 0.1U_0402_16V7K 2 1 CV11 EDP_TX3#_C 11
2 <7> CPU_EDP_TX3N 11
SY6288C20AAC_SOT23-5 12
2
0.1U_0402_16V7K 2 1 CV12 EDP_AUX_C 13 12
2 2 <7> CPU_EDP_AUX 13
0.1U_0402_16V7K 2 1 CV13 EDP_AUX#_C 14
<7> CPU_EDP_AUX# 14
15
15
l
CPU_EDP_HPD 16
<16> CPU_EDP_HPD 16
+VDD_TOUCH 17
<16> PCH_ENVDD CE_EN_R 17
18
2 DBC_EN_R 18
Add Pull Down
19
ia
RV600 20 19
+3VS 20
EN can't f l oat i n.g 100K_0402_5% +LCDVDD_CONN MCM1012B900F06BP_4P 21
4 3 USB20_CAM_P7_R 22 21
<19> USB20_P7 USB20_CAM_P7_R 22
23
1
USB20_CAM_N7_R 23
10P_0402_50V8J
10P_0402_50V8J
W=60mils
24
t
24
1
1 2 USB20_CAM_N7_R 25
@RF@
@RF@
<19> USB20_N7 +LCDVDD_CONN 25
CV372
CV373
26
LV2 EMI@ TS_EN 27 26
<43> TS_EN
2
28 27
n
+3VS_CAM 28
+3VS_CAM 29
1 2 MIC_CLK 30 29
<32> MIC_CLK MIC_GND 30
RV6 @EMI@ 0_0402_5% 31
MIC_DATA 32 31
e
<32> MIC_DATA LCD_TEST 32
1 2 <43> LCD_TEST 33
RV7 @EMI@ 0_0402_5% USB20_N6 34 33
USB20_P6 35 34
36 35
id
<16> PCH_INV_PWM 36
DISPOFF# 37
USB20_N6 37
W=60mils
38
<19> USB20_N6 38
1
+INV_PWR_SRC 39
USB20_P6 RV8 40 39
<19> USB20_P6 40
10P_0402_50V8J
2 RV13 100K_0402_5% 2
@RF@
0_0402_5% ACES_50473-0400M-P01
3
MIC_CLK 1
LCD backlight power control
CV375
2 CONN@
2
1
@RF@
@EMI@
2
Laverage ZAP00
CV374
n
@ESD@ 10P_0402_50V8J
2
DV2
PESD5V0U2BT_SOT23-3
QV1
o
SI3457CDV-T1-GE3_TSOP6
W=60mils
1
B+ 6 +3VS +LCDVDD_CONN
+INV_PWR_SRC
5
10U_0603_6.3V6M
W=60mils
2
0.1U_0402_10V7K
0.1U_0402_10V7K
4 1
S
C
1 1 1 1
1000P_0402_50V7K
CV15
100K_0402_5%
RV9
CV16
CV17
CV18
1
CV14
G
1
0.1U_0603_25V7K
3
2 2 2 2
2
2
L
PWR_SRC_ON
Place close to JEDP
1
RV12
L
100K_0402_5%
2
3 3
E
1
<43> EN_INVPWR 2 QV2

G SSM3K7002FU_SC70-3~D
S
3
r D Touch screen panel power control

+3VS +VDD_TOUCH
Webcam power control
o
RV81 1 @ 2 0_0402_5%
1 1 CE_EN_R
F
CV21 CV19
4.7U_0603_10V 0.1U_0402_10V7K DBC_EN 1 @ 2 DBC_EN_R
+3VS +3VS_CAM 2 2 <43> DBC_EN
RV46 0_0402_5%
1
@ @
RV47 1 @ 2 0_0603_5% RV36 RV14
0_0402_5% 0_0402_5%
2
4 4
2015/01/30
Compal Secret Data
2016/12/31 Title
LCD Conn/Cam, Touch
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C912P 0.1
A B C D E

A B C D E
1 1
ia l
n t
2
id e 2
Empty page n f
C o
3
L L 3
D E
o r
4
F 4
2015/01/30
Compal Secret Data
2016/12/31 Title
3D Camera
A B C D E

5 4 3 2 1
4/21 Change to 0ohm.

NV suggest.
4/16 Change to 0201 1 EMI@ 2
RV25 0_0402_5%
TMDS_R_TXCN 1 @ 2 TMDS_L_TXCN
0.1U_0201_6.3V6K RV16 5.6_0402_1% +HDMI_5V_OUT
CV25 2 1 TMDS_C_TXCN
<47> TMDS_TXCN
2
<47> TMDS_TXCP
0.1U_0201_6.3V6K
CV26 2 1 TMDS_C_TXCP
RV500
150_0402_1% W=60mils
EMI@ +3VS
1
RV26 0_0402_5%
1 2 TMDS_R_TXCP 1 @ 2 TMDS_L_TXCP RV18
D D
RV17 EMI@ 5.6_0402_1% @ 10K_0402_5%
RV27 0_0402_5% JHDMI1
2
1 EMI@ 2 TMDS_R_TX0N 1 @ 2 TMDS_L_TX0N HDMI_HPLUG 19
0.1U_0201_6.3V6K RV19 5.6_0402_1% 18 HP_DET
CV27 2 1 TMDS_C_TX0N 17 +5V
<47> TMDS_TX0N DDC/CEC_GND
2
TMDS_CTRLDAT_R 16
0.1U_0201_6.3V6K RV501 TMDS_CTRLCLK_R 15 SDA
l
CV28 2 1 TMDS_C_TX0P 14 SCL
<47> TMDS_TX0P 150_0402_1% Reserved
13
EMI@ TMDS_L_TXCN CEC
12 20
1
RV28 0_0402_5% 11 CK- GND 21
CK_shield GND
ia
1 2 TMDS_R_TX0P 1 @ 2 TMDS_L_TX0P TMDS_L_TXCP 10 22
RV20 EMI@ 5.6_0402_1% TMDS_L_TX0N 9 CK+ GND 23
8 D0- GND
RV29 0_0402_5% TMDS_L_TX0P 7 D0_shield
1 EMI@ 2 TMDS_R_TX1N 1 @ 2 TMDS_L_TX1N TMDS_L_TX1N 6 D0+
0.1U_0201_6.3V6K RV21 5.6_0402_1% 5 D1-
t
CV29 2 1 TMDS_C_TX1N TMDS_L_TX1P 4 D1_shield
<47> TMDS_TX1N D1+
2
TMDS_L_TX2N 3
0.1U_0201_6.3V6K RV502 2 D2-
CV30 2 1 TMDS_C_TX1P TMDS_L_TX2P 1 D2_shield
<47> TMDS_TX1P 150_0402_1% D2+
n
EMI@
FUTUR_061-HA18-0001
1
RV30 0_0402_5% CONN@
1 2 TMDS_R_TX1P 1 @ 2 TMDS_L_TX1P
RV22 EMI@ 5.6_0402_1%
<47> TMDS_TX2P
0.1U_0201_6.3V6K
CV31 2 1 TMDS_C_TX2P
RV23
1 EMI@ 2
id e5.6_0402_1%
RV33 0_0402_5%
TMDS_R_TX2P 1 @ 2 TMDS_L_TX2P
+HDMI_5V_OUT
2
UV3
<47> TMDS_TX2N
0.1U_0201_6.3V6K
CV32 2 1 TMDS_C_TX2N
RV503
150_0402_1% W=60mils
W=60mils
C 3 C
EMI@ OUT
1
RV34 0_0402_5% +5VS 1
TMDS_R_TX2N 1 2 TMDS_L_TX2N IN
0.1U_0402_16V7K
1 2 @
RV24 EMI@ 5.6_0402_1% 2 1
GND
CV33
n
AP2330W-7_SC59-3 2
C o
4/16 Change to 0201 resistor.
TMDS_C_TX0N
TMDS_C_TX0P
TMDS_C_TXCN
TMDS_C_TXCP
TMDS_C_TX1N
TMDS_C_TX1P
TMDS_C_TX2N
TMDS_C_TX2P
RX6
RX7
RX8
RX9
RX10
RX11
RX12
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
499_0201_1%
499_0201_1%
499_0201_1%
499_0201_1%
499_0201_1%
499_0201_1%
499_0201_1%
ROYALTY HDMI W/LOGO
CPN:RO0000002HM
46@
Part Number
RO0000002HM
ROYALTY HDMI W/LOGO
Description
HDMI W/Logo:RO0000002HM
L
RX13 499_0201_1%
HDMI_Down
+3VS_VGA
1
D
2 QX1
L
G BSS138-G_SOT23-3
1
S
3
+HDMI_5V_OUT RX1
100K_0402_5%
B B
2
E
SDM10U45-7_SOD523-2
SDM10U45-7_SOD523-2
2
DV3 DV5
+3VS_VGA
D
1
To PCH +3VS
2
2
2K_0402_5%
2K_0402_5%
r
RV549
RV556
QX2
<16,17> PCH_HDMI_HPD
10K_0402_5%
10K_0402_5%
MMST3904-7-F_SOT323-3
2 RV100 1
2 RV101 1
1
C
2 1 2 HDMI_HPLUG
1
B RX2
o
E 150K_0402_5%
3
5
QV92A RV15 1 @ 2 0_0402_5% PCH_HDMI_HPD

1
RV550 27NH_LQG15HS27NJ02D_300MA_5%
G
TMDS_TRLCLK 4 3HDMI_SCLF 2 1 HDMI_SCLR 1 2 TMDS_CTRLCLK_R CX1

<47> TMDS_TRLCLK
1
+3VS
S
DMN66D0LDW-7_SOT363-6 33_0402_1% LV17 0.1U_0402_16V7K

2
To GPU
F
CV20 RX4
2
1 2 100K_0402_5%
QV92B RV555 27NH_LQG15HS27NJ02D_300MA_5%
G
TMDS_CTRLDAT HDMI_SDAF HDMI_SDAR TMDS_CTRLDAT_R
To GPU
1 6 2 1 1 2 0.1U_0402_16V7K
2
<47> TMDS_CTRLDAT
5
S
33_0402_1% LV18 UX1

PCH_HDMI_HPD
10P_0402_50V8J
10P_0402_50V8J
DMN66D0LDW-7_SOT363-6 1
P
TMDS_HPD 4 B
1 1 <46> TMDS_HPD O DGPU_PEX_RST#
CV441
CV442
Place closed to JHDMI1 2

A DGPU_PEX_RST# <46>
G
2
TC7SH08FU_SSOP5~D
3
2 2 RX5
100K_0402_5%
A A
1
HDMI LS & Conn.
5 4 3 2 1

5 4 3 2 1
+3VS_WLAN_NGFF +5VALW
D D
1
RN25 RN26 RN27
2
100K_0402_5% 100K_0402_5% 100K_0402_5%
G
2
2
WLAN_LED# 3 1 WLES ON/OFF LED#
WLES ON/OFF LED# <38>
D
ia
QN5
2
2N7002K 1N SOT23-3
G
NGFF WL Con (Key E) BT_LED# 3 1
D
QN4
+3VS_WLAN_NGFF 2N7002K 1N SOT23-3
n
JWLAN1
1 2
USB20_P5 3 GND 3.3VAUX 4
<19> USB20_P5 USB20_N5 5 USB_D+ 3.3VAUX 6 WLAN_LED#
e
<19> USB20_N5 7 USB_D- LED1# 8
9 GND PCM_CLK 10
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16 BT_LED#
id
17 SDO_DAT1 LED2# 18
T5 @ SDO_DAT2 GND
For EC to detect
Add Test Point for Debug 19 20
T6 @ SDO_DAT3 UART_WAKE#
21 22
23 SDIO_WAKE# UART_RX
debug card insert.

SDIO_RESET#
C C
f
24 1 2
0.1U_0402_16V7K 25 UART_TX 26
PCIE_PTX_DRX_P6 CN23 2 1 PCIE_PTX_DRX_P6_C 27 GND UART_CTS 28 RM31
<19> PCIE_PTX_DRX_P6 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_N6_C PETP0 UART_RTS
CN24 2 1 29 30 100K_0402_5%
n
<19> PCIE_PTX_DRX_N6 31 PETN0 RESERVED 32 EC_TX <43> +3VS_WLAN_NGFF +3VS
PCIE_PRX_DTX_P6 33 GND RESERVED 34 EC_RX <43>
0.1U_0402_16V7K
<19> PCIE_PRX_DTX_P6 PCIE_PRX_DTX_N6 35 PERP0 RESERVED 36
<19> PCIE_PRX_DTX_N6 PERN0 COEX3
1
37 38
CLK_PCIE_P5_R 39 GND COEX2 40
o
RN5
CLK_PCIE_N5_R 41 REFCLKP0 COEX1 42 SUSCLK_R RM32 1 @ 2 0_0402_5% 10K_0402_5% @ QN2
REFCLKN0 SUSCLK SUSCLK <18,29>
2
43 44 PLT_RST#_R RM33 1 2 0_0402_5%
G
@ L2N7002WT1G 1N SC-70-3
45 GND PERST0# 46 BT_OFF# PLT_RST# <17,29,30,31,43,58>
2
<17> CLKREQ_PCIE#5 WLAN_WAKE# 47 CLKEQ0# W_DISABLE2# 48 BT_OFF# <20> WL_OFF#_R 1 3
<43> WLAN_WAKE# PEWAKE0# W_DISABLE1# WL_OFF# <20>
49 50
S
51 GND I2C_DATA 52
C
RSRVD/PETP1 I2C_CLK
1
53 54 1
55 RSRVD/PETN1 ALERT 56 CN9 RN14
57 GND RESERVED 58 0.1U_0402_10V7K 10K_0402_5%
59 RSRVD/PERP1 RESERVED 60
61 RSRVD/PERN1 RESERVED 62 2
2
GND RESERVED
63
65 RESERVED 3.3VAUX
64
66 Prevent backdriver from +3VS_WLAN_NGFF to +3VS
67 RESERVED 3.3VAUX
GND
L
RM39 0_0402_5%
1 @ 2
69 68
MTG77 MTG76
LOTES_APCI0019-P009A
CLK_PCIE_P5_R
L
<17> CLK_PCIE_P5
CLK_PCIE_N5_R
B
<17> CLK_PCIE_N5
Debug Conn for BIOS +5VALW
B
E
JWDB1
RM40 0_0402_5% 1
1 @ 2 UART_2_CTXD_DRXD 2 1
<20> UART_2_CTXD_DRXD UART_2_CRXD_DTXD 2
3 5
<20> UART_2_CRXD_DTXD 4 3 G1 6
4 G2
+3VS_WLAN_NGFF
D
ACES_88266-04001
+3VALW
closed to pin 2, 4 closed to pin 64, 66
CONN@
10U_0603_6.3V6M~D
Change FT to ACES_50207-00471-P01_4P-T
+3VS_WLAN_NGFF +3VS_WLAN_NGFF
1
CM10
AOAC@
2
r
AOAC@
CM11
2
22U_0603_6.3V6M~D
0.1U_0402_10V7K~D
22U_0603_6.3V6M~D
0.1U_0402_10V7K~D
1 1 1 1 1U_0402_6.3V UM1
1 5 1
IN OUT
CM12
CM13
CM14
CM15
+3VALW
o
2
2 2 2 2 GND
4 3 2 1
<43> AOAC_WLAN EN OC
1 SY6288C20AAC_SOT23-5 AOAC@
F
AOAC@ RM34
AOAC@ 10K_0402_5%
RM95
100K_0402_5%
2
A A

WLAN
5 4 3 2 1

5 4 3 2 1
SSD
NGFF Slot_1 Key M
+3VS
JSSD1
1 2
3 GND 3P3VAUX 4
PCIE_PRX_DTX_N12 5 GND 3P3VAUX 6
<16> PCIE_PRX_DTX_N12 PCIE_PRX_DTX_P12 7 PERn3 NC 8
<16> PCIE_PRX_DTX_P12 9 PERp3 NC 10 SSD1_LED#
11 GND DAS/DSS# 12
D <16> PCIE_PTX_DRX_N12 PETn3 3P3VAUX D
13 14
<16> PCIE_PTX_DRX_P12 15 PETp3 3P3VAUX 16
PCIE_PRX_DTX_N11 17 GND 3P3VAUX 18
<16> PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 19 PERn2 3P3VAUX 20
<16> PCIE_PRX_DTX_P11 21 PERp2 NC 22
23 GND NC 24
<16> PCIE_PTX_DRX_N11 25 PETn2 NC 26
<16> PCIE_PTX_DRX_P11 27 PETp2 NC 28
l
PCIE_PRX_DTX_N10 29 GND NC 30
35 GND NC 36
<16> PCIE_PTX_DRX_N10 PETn1 NC
ia
37 38
<16> PCIE_PTX_DRX_P10 39 PETp1 DEVSLP 40 DEVSLP0 <19>
PCIE_PRX_DTX_P9 41 GND NC 42
<16> PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 43 PERn0/SATA-B+ NC 44 +3VS
<16> PCIE_PRX_DTX_N9 45 PERp0/SATA-B- NC 46
47 GND NC 48
t
+3VS <16> PCIE_PTX_DRX_N9 49 PETn0/SATA-A- NC 50
<16> PCIE_PTX_DRX_P9 PETp0/SATA-A+ PERST# PLT_RST# <17,28,29,30,31,43,58>
0.047U_0402_16V4Z
0.047U_0402_16V4Z
330U_V_6.3VM_R25
51 52
33P_0402_50V8J
22U_0805_6.3VAM
33P_0402_50V8J
GND CLKREQ# CLKREQ_PCIE#1 <17> 1
10K_0402_5%
53 54 1 1 1 1 1
<17> CLK_PCIE_N1 REFCLKN PEWake#
2
PCIE_WAKE# <18,29,30,43>
C619
55 56 +
<17> CLK_PCIE_P1 REFCLKP NC
R363
C623
C621
C618
C622
C617
57 58
n
GND NC
2 2 2 2 2 2
1
e
67 68 SUSCLK_JSSD1 1 @ 2 SUSCLK
1 2 69 NC SUSCLK(32kHz) 70 SUSCLK <18,28,29>
@ PEDET1 R360 0_0402_5%
<16> M2_SLOT1_PEDET R372 0_0402_5% 71 PEDET(OC-PCIe/GND-SATA) 3P3VAUX 72
GND 3P3VAUX
DMN65D8LW-7_SOT323-3
73 74
GND 3P3VAUX
1
D 75
id
GND
@ QN6
2 PEDET1 76
G GND1 77
GND2
S
PEDET Module Type
3
1
@ R364
C CONN@ C
20K_0402_5%
f
0 SATA
+3VS
2
n
1 PCIE
QE17B
2
G
SSD1_LED# 6 1
o
PCH_SATALED# <16,29,38>
5 G
SSD2_LED# 3 4
PCH_SATALED# <16,29,38>
S
SSD
QE17A
C
NGFF Slot_2 Key M
L
+3VS
JSSD2
1 2
3 GND 3P3VAUX 4
5 GND 3P3VAUX 6
7 PERn3 NC 8
9 PERp3 NC SSD2_LED#
L
10
11 GND DAS/DSS# 12
13 PETn3 3P3VAUX 14
15 PETp3 3P3VAUX 16
17 GND 3P3VAUX 18
19 PERn2 3P3VAUX 20
B PERp2 NC B
E
21 22
23 GND NC 24
25 PETn2 NC 26
27 PETp2 NC 28
PCIE_PRX_DTX_N16 29 GND NC 30
35 GND NC 36
D
<16> PCIE_PTX_DRX_N16 37 PETn1 NC 38
<16> PCIE_PTX_DRX_P16 39 PETp1 DEVSLP 40 DEVSLP2 <19>
PCIE_PRX_DTX_P15 41 GND NC 42
<16> PCIE_PRX_DTX_P15 PCIE_PRX_DTX_N15 43 PERn0/SATA-B+ NC 44 +3VS
<16> PCIE_PRX_DTX_N15 45 PERp0/SATA-B- NC 46
GND NC
r
47 48
+3VS <16> PCIE_PTX_DRX_N15 49 PETn0/SATA-A- NC 50
<16> PCIE_PTX_DRX_P15 PETp0/SATA-A+ PERST# PLT_RST# <17,28,29,30,31,43,58>
0.047U_0402_16V4Z
0.047U_0402_16V4Z
330U_V_6.3VM_R25
33P_0402_50V8J
22U_0805_6.3VAM
33P_0402_50V8J
51 52 1
GND CLKREQ# CLKREQ_PCIE#2 <17>
10K_0402_5%
53 54 1 1 1 1 1
<17> CLK_PCIE_N2 REFCLKN PEWake#
2
PCIE_WAKE# <18,29,30,43>
C626
55 56 +
<17> CLK_PCIE_P2
o
REFCLKP NC
R365
C625
C627
C620
C624
C628
57 58
GND NC
2 2 2 2 2 2
1
67 68 SUSCLK_JSSD2 1 2 SUSCLK
F
@
1 2 69 NC SUSCLK(32kHz) 70 SUSCLK <18,28,29>
@ PEDET2 R361 0_0402_5%
<16> M2_SLOT2_PEDET R373 0_0402_5% 71 PEDET(OC-PCIe/GND-SATA) 3P3VAUX 72
GND 3P3VAUX
DMN65D8LW-7_SOT323-3
73 74
GND 3P3VAUX
1
D 75
GND
@ QN7
2 PEDET2 76
G GND1 77
GND2
S
PEDET Module Type
3
1
@ R366
CONN@
20K_0402_5%
0 SATA
A A
2
1 PCIE

Mini Card/LED
5 4 3 2 1

5 4 3 2 1
UL1
<19> PCIE_PRX_DTX_P5
PCIE_PRX_DTX_P5 2 1 PCIE_PRX_DTX_P5_C 30
TX_P VDD33
1 W=40mils +LAN_IO
CL1 0.1U_0402_16V7K 16
PCIE_PRX_DTX_N5 2 1 PCIE_PRX_DTX_N5_C 29 AVDD33
<19> PCIE_PRX_DTX_N5 TX_N
CL2 0.1U_0402_16V7K
PCIE_PTX_DRX_P5 2 1 PCIE_PTX_DRX_P5_C 35 13 +AVDDL
<19> PCIE_PTX_DRX_P5 RX_P AVDDL
W=20mils
+LAN_IO CL3 0.1U_0402_16V7K 19
PCIE_PTX_DRX_N5 2 1 PCIE_PTX_DRX_N5_C 36 AVDDL 31 +DVDDL
<19> PCIE_PTX_DRX_N5 RX_N AVDDL
1U_0402_6.3V
0.1U_0402_16V7K~D
CL4 0.1U_0402_16V7K 34
33 AVDDL 6
<17> CLK_PCIE_P4 REFCLK_P AVDDL_REG
1
1 1
RL1 32
<17> CLK_PCIE_N4 REFCLK_N 22 +AVDDH
D 4.7K_0402_5%~D CL43 CL44 D
4 AVDDH 9
<17> CLKREQ_PCIE#4 CLKREQ# AVDDH_REG 2 2
2
PLT_RST# 2
<17,28,29,31,43,58> PLT_RST# PERST# 37 +DVDDL
PCIE_WAKE# 3 DVDDL_REG
<18,29,43> PCIE_WAKE# WAKE#
11 LAN_MDIP0
TRXP0 LAN_MDIN0
close to UL1 pin37
25 12
SMCLK TRXN0 LAN_MDIP1
The pull-up resisters might not be

26 14
SMDATA TRXP1 LAN_MDIN1
l
15
28 TRXN1 17 LAN_MDIP2
necessory due to existence

27 NC TRXP2 18 LAN_MDIN2
41 TESTMODE TRXN2 20 LAN_MDIP3
GND TRXP3 LAN_MDIN3
W=20mils
21
on PCH side.
ia
XTLI 8 TRXN3 +AVDDH
XTLI
1U_0402_6.3V
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
XTLO 7
XTLO
25MHZ_10PF_7V25000014
40
1 2 5 LX
+LAN_IO ISOLAT# 1 1 1
RL2 30K_0402_5% 24
PPS
4
t
CL5 CL6 CL7
LAN_ACTIVITY# 38 10 +RBIAS 1 2
GND
GND
LAN_LINK#_R 39 LED_0 RBIAS 2 2 2
LAN_LED2#_R 23 LED_1 RL3
LED_2
2
2.37K_0402_1%~D
OSC
OSC
n
RL4
YL1 5.1K_0402_1%~D S IC E2400-BL3A-R QFN 40P E-LAN CTRL
3
15P_0402_50V8J~D
15P_0402_50V8J~D
1
2 2
close to UL1 pin9 close to UL1 pin22
e
CL8 CL9 3/30 Change to E2400
PN:SA00008TH00
1 1
+3VALW
id
C C
1 1
CL40 CL41
f
4.7U_0603_10V 0.1U_0402_16V7K
2 2
1A
+LAN_IO
W=20mils
W=40mils
UL2 +AVDDL
1U_0402_6.3V
1U_0402_6.3V
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1
4.7U_0603_6.3V6K~D
n
OUT
1000P_0402_50V7K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
5
IN
1U_0402_6.3V
1U_0402_6.3V
2 1 1 1 1 1 1 1 1
EN_WOL# GND
CL22
4
<43> EN_WOL# EN 3 1 2 CL18 CL19 CL20 CL21 CL23 CL24 CL25
OCB +3VS 1 1 1 1 1 1 1
1 RL5
o
CL42 10K_0402_5% CL11 CL12 CL13 CL14 CL15 CL16 CL17 2 2 2 2 2 2 2 2
SY6288D20AAC_SOT23-5
2 2 2 2 2 2 2
0.1U_0402_16V7K
C
close to UL1 pin1 close to UL1 pin16 close to UL1 pin6 close to UL1 pin34 close to UL1 pin31 close to UL1 pin13 close to UL1 pin19
Same with ZAP00.

Symbol check OK. 2/25
L
JLAN
B @EMI@ B
2 1 LAN_ACTIVITY# 10
CL27 470P_0402_50V7K Yellow LED-
L
2 1 9
+LAN_IO Yellow LED+
TIMAG: S X'FORM_ IH-160 LAN,SP050006F00

RL8 330_0402_5%
RJ45_MDI3- 8
PR4- H1 H3
RJ45_MDI3+ 7 H_3P5X4P1 H_2P8
TL1 PR4+ @ @
RJ45_MDI1-
E
RL9 6
1
+VDDCT_L 1 24 RJ45_CT3 1 2 RJ45_CT PR2-
LAN_MDIN3 2 TCT1 MCT1 23 RJ45_MDI3- 75_0402_1%~D RJ45_MDI2- 5
LAN_MDIP3 3 TD1+ MX1+ 22 RJ45_MDI3+ PR3-
TD1- MX1- RL10 RJ45_MDI2+ 4
4 21 RJ45_CT2 1 2 PR3+ 17 NC
LAN_MDIN2 5 TCT2 MCT2 20 RJ45_MDI2- 75_0402_1%~D RJ45_MDI1+ 3 GND
LAN_MDIP2 6 TD2+ MX2+ 19 RJ45_MDI2+ PR2+ 16
D
TD2- MX2- RL11 RJ45_MDI0- 2 GND
7 18 RJ45_CT1 1 2 PR1- 15
LAN_MDIN1 8 TCT3 MCT3 17 RJ45_MDI1- 75_0402_1%~D RJ45_MDI0+ 1 GND
LAN_MDIP1 9 TD3+ MX3+ 16 RJ45_MDI1+ PR1+ 14
TD3- MX3- RL12 2 1 LAN_LINK# 11 GND
RJ45_CT0 Green LED-
r
10 15 1 2 @EMI@ CL28 470P_0402_50V7K
LAN_MDIN0 11 TCT4 MCT4 14 RJ45_MDI0- 75_0402_1%~D 2 1 LAN_LED2# 13
LAN_MDIP0 12 TD4+ MX4+ 13 RJ45_MDI0+ @EMI@ CL29 470P_0402_50V7K Orange LED-
TD4- MX4- 1 2 12
2N7002K_SOT23-3 +LAN_IO Green-Orange LED+
LL1
o
2 QL3 BLM15AG121SN1D_L0402_2P
S XFORM_ IH-160 LAN SANTA_130456-511
3
D
CL30 1 2 1 CONN@
10P_1808_3KV7K~D RL13 130_0402_1%~D
2
1 LAN_LED2#_R 2 1 1
RL15 130_0402_5%~D @EMI@
G
F
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
RL14 CL31
LAN_LINK#_R 2 1K_0402_1%~D 470P_0402_50V7K
A 2 A
CL32
CL33
CL34
CL35
CL36
CL37
CL38
CL39
2 1 2 1 2 1 2 1
1
+LAN_IO
1 2 1 2 1 2 1 2

LAN E2201
5 4 3 2 1

5 4 3 2 1
+3VS_CARD UR1
+3VS_CARD
11 30 SD_CD#
3V3_IN SD_CD#
2 1
20 mils 18
+DV33_18 31 MS_INS#
1U_0402_6.3V CR3 DV33_18 MS_INS#
20 mils 10
0.1U_0402_16V7K
4.7U_0603_6.3V6K
1 1
CR6 CR7 2 1 +AV12_DV12_S 32 CR_WAKE#
0.1U_0402_16V7K CR4 AV12 WAKE#
2 1
20 mils 14
D 2 2 4.7U_0603_6.3V6K CR5 DV12S for project which need fine tune SD signal can change to R D
2 1
0.1U_0402_16V7K CR8 15 SD_D1 RR7 1 @ 2 0_0402_5% SD_D1_R
+Vcc_3in1 SP1
40 mils 12 16 SD_D0 MS_D1 RR8 1 @ 2 0_0402_5% SD_D0 MS_D1_R
Card_3V3 SP2 @EMI@ @EMI@
+3VS_CARD 17 SD_CLK MS_D0 RR1 2 1 33_0402_1% SD_CLK MS_D0_R 2 1 1 2
l
Close to Pin 27 SP3
20 mils 375mA 27 EMI@
3V3aux 19 SD_CMD MS_D2 RR5 1 @ 2 0_0402_5% SD_CMD MS_D2_R RR9 CR9
12 mils SP4 22_0402_5%~D 5P_0402_50V8C
ia
6.2K_0402_1% 1 2 RR2 RREF 9 20 SD_D3 MS_D3 RR6 1 @ 2 0_0402_5% SD_D3 MS_D3_R
RREF SP5 @EMI@ @EMI@
Close pin < 200mil SD_D2 MS_CLK SD_D2 MS_CLK_R
21 RR3 2 1 33_0402_1% 2 1 1 2
SP6
t
EMI@
PCIE_PTX_DRX_P7 1 2 3 29 SD_WP MS_BS RR10 CR14
<19> PCIE_PTX_DRX_P7 HSIP SP7
CR13 0.1U_0402_16V7K 22_0402_5%~D 5P_0402_50V8C
PCIE_PTX_DRX_N7 1 2 4
n
<19> PCIE_PTX_DRX_N7 HSIN
CR12 0.1U_0402_16V7K
PCIE_PRX_DTX_P7 1 2 7
<19> PCIE_PRX_DTX_P7 HSOP
CR10 0.1U_0402_16V7K
e
PCIE_PRX_DTX_N7 1 2 8 13
<19> PCIE_PRX_DTX_N7 HSON NC
CR11 0.1U_0402_16V7K
22
NC
id
C C
5 23
<17> CLK_PCIE_P6 REFCLKP NC
6 24
<17> CLK_PCIE_N6 REFCLKN NC
f
+3VS_CARD 25
NC 40 mils
PLT_RST# 1 26
n
<17,28,29,30,43,58> PLT_RST# PERST# NC +Vcc_3in1
1 8 CR_GPIO
2 7 CR_WAKE# 2
<17> CLKREQ_PCIE#6 CLK_REQ#
o
3 6
0.1U_0402_16V7K
CR16
4 5
CR_GPIO
10U_0402_6.3V6M
CR15
28 33 1 1
RR4 10K_8P4R_5% GPIO GND
Close to JCR Pin 12
C
RTS5227-GR_QFN32_4X4 2 2
pin28:
If GPIO NO use for LED function and
GPIO must pull high
Internal Pull status
60mil 60mil 1.5A
L L
15_SP1
16_SP2
17_SP3
NO Card
PD80
PD80
PD80
SD Insert
SD_D1_PU80
SD_D0_PU80
SD_CLK_PD80 MS_D0_PD80
MS Insert
PD80
MS_D1_PD80
SD_D2 MS_CLK_R
SD_D3 MS_D3_R
SD_D2 MS_CLK_R
SD_CMD MS_D2_R
1
2
3
4
5
6
JCR
SD-DAT2
MS-VSS1
SD-CD/DAT3 MMC-RSV
MS-VCC
MS-SCLK
B
E
SD_D3 MS_D3_R 7 SD-CMD MMC-CMD
+3VS +3VS_CARD MS_INS# 8 MS-DATA3
19_SP4 PD80 SD_CMD_PU80 MS_D2_PD80 MS-INS
LR1 9
MMZ1608R301AT_2P~D SD_CMD MS_D2_R 10 SD-VSS MMC-VSS1
20_SP5 PD80 SD_D3_PU80 MS_D3_PD80 MS-DATA2
1 2 11
D
SD_CLK MS_D0_R 12 SD-VDD MMC-VDD
21_SP6 PD80 SD_D2_PU80 MS_CLK_PD80 SD_D0 MS_D1_R MS-DATA0
10U_0603_6.3V6M
CR1
0.1U_0402_16V7K
CR2
13
SD_CLK MS_D0_R 14 MS-DATA1
1 1 29_SP7 PD200 SD_WP_PD200 MS_BS_PD200 SD_WP MS_BS SD-CLK MMC-CLK
15
r
16 MS-BS
30_SD_CD# PU200 PU200 PU200 MS-VSS2
17
2 2 SD_D0 MS_D1_R 18 SD-VSS MMC-VSS2
31_MS_CD# PU200 PU200 PU200 SD_D1_R SD-DAT0 MMC-DAT
o
19
SD_CD# 20 SD-DAT1
21 SD-CD 23
SD_WP MS_BS 22 SD-GND GND1 24
SD-WP(SW) GND2
F
Close to Pin 11 T-SOL_143-2300302602_RV
A A

Card Reader RTS5179
5 4 3 2 1

5 4 3 2 1
+3.3V_DVDD
+3.3V_DVDD
BLM15AG121SN1D_L0402_2P +3.3V_DVDD
LA10 +3.3V_DVDD +3VS
1 2 VDDQ_PLL
BLM15AG121SN1D_L0402_2P
LA9 1 2 VDD_SW
1
40 mil 700mA
+3VS +3.3V_DVDD
2 1 2 +5VS
+1.2VS +3.3V_AVDD closed to Pin 16,19 CA3 RA95 UA5 RT9041E-15GQW_WDFN8_2X2
20 mil 20 mil 500mA
+3VS 0.1U_0402_10V CA4 CA5 CA1 2 @ 1
2 10U_0603_6.3V6M~D 8 1
0.1U_0402_10V 0.1U_0402_10V VIN VOUT +1.2VS
RA51 UA1 1 2 1 0_0603_5%
1 2 0_0402_5% DVDD_HDAIO 9 38 7 2 FB_1.2V
@ 2 DVDD_1 AVDD NC ADJ
2
20 29 closed to Pin 10, 11 closed to Pin 54
DVDD_2 PORTA_VDD
0.1U_0402_10V CA14
+3.3V_DVDD
48
DVDD_3 PORTD_VDD
34
20 mil 6
VDD PGOOD
3 RA127
VDD_SW EN_1.2V 5.1K_0402_1%
1 15 10 +3VS 2 1 5 4
FBDC VDD_SW_1 EN GND
20 mil 11 9
1
VDD_SW_2 VDDQ_PLL 1U_0402_10V PGND
1
54 16 12K_0402_1%
DVDD_HDAIO 6 DVDD_IO VDDQ_SW CA112
RA128
DVDD_HDAIO 12 +3VS +3.3V_AVDD @
2
VDDQ_PLL SWOUT
2
D
20 mil 10P_0402_50V8J~D RA96 0_0402_5%
19
VDDQ_PLL RA92 RA129 D
CA30 2 1 2 1 28 HPOUT-L 1 @ 2 10K_0402_5%
@ @ 5 PORTA_L 26 HPOUT-R 1 2 2
<18> PCH_AZ_CODEC_BITCLK 1 2 PCH_AZ_CODEC_SDIN0_R 7 HDA_BCLK PORTA_R 24 0_0402_5%
FB=0.8V
1
<18> PCH_AZ_CODEC_SDIN0 4 HDA_SDI PORTA_S 27
RA40 33_0402_5%~D CA6 CA7 CA8
<18> PCH_AZ_CODEC_SDOUT 3 HDA_SDO PORTA_VCOM 10U_0603_6.3V6M~D
<18> PCH_AZ_CODEC_SYNC HDA_SYNC MIC_LINE_IN_L 0.1U_0402_10V 0.1U_0402_10V
2 44 2 1 1
<18> PCH_AZ_CODEC_RST# HDA_RSTN PORTB_L
PORTB_R
43 MIC_LINE_IN_R Vo=0.8(1+Rt/Rb)=1.2V
SENSE A# 47 45 MIC1_C_L CA13 1 2 2.2U_0603_10V6K MIC1
RA64 1 2 10K_0402_1%~D 37 SENSE_A PORTC_L 46 AGND
RA42 1 2 20K_0402_1%~D 36 SENSE_B PORTC_R +3.3V_DVDD
AGND SENSE_I HP2_D_L1
33
PORTD_L HP2_D_R1
l
31
CA15 1 2 2200P_0402_50V MIC_BIAS_B 42 PORTD_R 35
AGND MIC_BIAS_C MIC_BIASB PORTD_S +1.2VS
CA24 1 2 100P_0402_50V8J~D 41 32
AGND MIC_BIASC PORTD_VCOM
MIC_BIAS_C AMP_LEFT 2
23 CA89 220U_B2_6.3VM_R35M
MIC_CLK_C 55 PORTG_L 22 AMP_RIGHT HP2_D_L1 1 2 HP2_D_L2
CA16
+
ia
51 DMIC_MCLK / MPIO1 PORTG_R UA6
<25> MIC_DATA DMIC_DATA0 / MPIO3 MPIO_2 2 2 2 0.1U_0402_10V
56 CA90 220U_B2_6.3VM_R35M 1
@ MPIO_4_PB#_PD 50 SPDIF OUT0 / MPIO2 CA9 CA10 CA11 HP2_D_R1 1 2 HP2_D_R2 HP_MIC_LINE_IN_L 2 15
+
SPDIF IN / MPIO4 40 HP_MIC_LINE_IN_R 3 L 5V_SUPPLY 14
RA54 0.1U_0402_10V 0.1U_0402_10V 0.1U_0402_10V
1 2 PC_BEEP_1 53 VREF_FILT 1 1 1 R VDD
1 2 AGND
PCBEEP / MPIO5 RA101
1
13
VSS_SW_1 MIC_LINE_IN_L2
100_0402_1%
100_0402_1%
0_0402_5%~D EAPD# 52 14 CA17 CA18 12 16 AC/DC 1 8
<43> EAPD# EAPD / MPIO0 VSS_SW_2 HP2_D_L2 L1 AC/DC DIR_SEL
RA107
RA108
17 47U_0805_6.3V6M~D 0.1U_0402_10V 11 6 2 7
AGND AMGND 1 VSSQ_SW 2 1 L2 DIR_SEL 3 6
8 DVSS_1 39 MIC_BIAS_B MIC_LINE_IN_R2 10 4 MPIO_4_PB#_PD 4 5
2
21 DVSS_2 AVSS 25 HP2_D_R2 9 R1 SEL 1 MPIO_2
49 DVSS_3 PORTA_VSS 30 QA11 QA13 R2 MUTE
EMI@ RA53 18 DVSS_4 PORTD_VSS AO3413_SOT23-3 AO3413_SOT23-3 10K_0804_8P4R_5%~D AGND
VSSQ_PLL
3
S S
CA69 2 1 0.1U_0603_25V 1 2 57 5 13
n
AGND AGND AGND
Thermal PAD 2
G G
2 8 GND CAP_SS
GND 2
EMI@ 0_0402_5%~D 7
CA70 2 1 0.1U_0603_25V 1 2 MALCOLM-EX_QFN56_7X7~D D D GND CA19
1
RA55 EMI@ 0_0805_5%~D 0.1U_0402_10V
EMI@ 1 2 AGND AGND ISL54405IRUZ-T_UTQFN16_2P6X1P8 1
e
CA71 2 1 0.1U_0603_25V RA57 EMI@ 0_0805_5%~D 1 1 CA73
AGND CA75 0.1U_0402_16V7K AGND AGND
AMGND 0.1U_0402_16V7K
2 2
2.2K_0402_5%
2.2K_0402_5%
1
1
SENSE pin
GND AGND AGND AMGND AGND
RA102
RA100
GND Close to chip side AGND
id
C C
JACK1_PLUG# JACK1_PLUG# 1 2 SENSE A#

@ 2.2U_0603_10V6K
2
PC BEEP
0.1U_0402_16V7K RA46 39.2K_0402_1%
CA65 2 1 PC_BEEP_1 JACK2_PLUG# 1 2 MIC_LINE_IN_L CA76 1 2 MIC_LINE_IN_L2
AC/DC 0 0 0
RA47 4.02K_0402_1%~D
MIC_C_PLUG
1
D 1 2
CA67 RA81 0.01U_0402_16V7K DIR X X X
PC_BEEP PC_BEEP_L JACK1_PLUG
f
1 2 1 2 CA66 2 1 2 QA3 RA48 10K_0402_1%~D
<43> BEEP# MIC_LINE_IN_R MIC_LINE_IN_R2
G SSM3K7002FU_SC70-3 CA77 1 2 MUTE 0 0 1
1U_0402_6.3V 560_0402_5% 0.01U_0402_16V7K S
3
PC_BEEP_R
CA72 2 1 2.2U_0603_10V6K SEL 0 1 X
1
CA68 L1,R1 ON OFF OFF
1 2 1 RA84 2 AGND RA106 RA105
n
<18> HDA_SPKR
24.9K_0402_1% 24.9K_0402_1% L2,R2 OFF ON OFF
1
1U_0402_6.3V 560_0402_5% +RTC_CELL

L, R OFF OFF OFF
2
RA80 @
10K_0402_5%~D C/P shunts
1
L1, R1 OFF OFF OFF
2
MIC_IN
o
RA123
C/P shunts
470K_0402_5%
UNDER WIN8 WLP (FSOP >= 1Vrms), AVDD=3.5 to 3.57Vrms AND MOUNT RA44(5K1). L2, R2 OFF OFF OFF
UNDER WIN8.1 WLP (FSOP >= 0.707Vrms). AVDD=3.3 +/- 0.3Vrms AND UNMOUNT RA44 C/P shunts
3
QA7B
5
D
DMN66D0LDW-7_SOT363-6 G QA7A
LA2 EMI@ DMN66D0LDW-7_SOT363-6
Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-R-
S
MIC_CLK_C 1 2 MIC_CLK
C
MIC_CLK <25>
6
BLM15BB221SN1D_2P
JACK1_PLUG
RA93
1 @
0_0402_5%
2
2 G
D
S
Speaker 4 ohm : 40mil Int. Speaker Connector
Speaker 8 ohm : 20mil close to Codec
1
LA7 +3VS 1 2 JSPK

TAI-TECH HCB1608KF-121T30 0603
1 2
40mil +PVDD
RA94
0_0402_5%~D
SPKR-
SPKR+
EMI@
EMI@
LA3
LA4
1
1
2 NBQ160808T-800Y-N 0603
2 NBQ160808T-800Y-N 0603
SPK_R1-_CONN
SPK_R2+_CONN
1
2 1
B+_BIAS SPK_L1-_CONN 2
SPKL- EMI@ LA5 1 2 NBQ160808T-800Y-N 0603 3
@ SPK_L2+_CONN 3
CA95
CA97
CA94
CA96
SPKL+ EMI@ LA6 1 2 NBQ160808T-800Y-N 0603 4

1U_0603_25V6K
1U_0603_25V6K
1U_0603_25V6K
1U_0603_25V6K
1
5 4
6 G1
L
G2
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
2
1 1 1 1 ACES_50278-00401-001
EMI@ CA29
EMI@ CA33
EMI@ CA31
EMI@ CA32
CONN@
B Close to UA1 B
+GVDD +GVDD 2 2 2 2
Pin12,13,14,27,28 B+_BIAS
CONN@
L
1
1
I-PEX_20455-040E-12
RA91 RA113 +3.3V_AVDD
@ 100K_0402_1% 10K_0402_1%
UA4 AMP_LEFT 40 44
PC_BEEP_R Add one more pin AMP_RIGHT 40 G5
2
1 2 RA109 39 43
2
MIC_IN 39 G4
PC_BEEP_L
RA139 100K_0402_5% 2 1 +PAVDD 12
AVCC PLIMIT
1 PLIMIT RA43 for +5VALW 38
38
10U_0805_25V6K
1 2 10K_0402_5%~D RING2 37
37
1
E
RA140 100K_0402_5% 10_0603_5% HPOUT-L 36
AUD_HP_OUT_L_CN 36
1
1U_0603_25V6K
10K_0402_5% CA98 +PVDD 13 3 35
1
RA120 PVCC GAIN/SLV
1
+5VALW B+_BIAS 35
CA99
14 RA112 HPOUT-R 34
2
PVCC SPK_MUTE JACK2_PLUG# 34

2
1 2 27 10K_0402_1% 33
CA105 28 PVCC 11 RA111 HP_MIC_LINE_IN_L 32 33
2
PVCC SYNC +3VS HP_MIC_LINE_IN_R 31 32

2.2U_0603_10V6K 0.047U_0402_16V4Z 5.6K_0402_1%
2
RA118 AMGND +3.3V_AVDD 30 31

AMP_LEFT AMP_LEFT-1 AMP_LEFT_C SPK_MUTE# SPK_MUTE# 30
1
1 2 1 2 1 2 6 29 D 29
CA103
1
1 2 1 2 CA101 5 INPL /SDZ 2 SPK_MUTE#_R 2 1 SPK_MUTE# 28 29

13.3K_0402_1% QA2
RA117 5.9K_0402_5% 0.1U_0402_16V4Z INNL G DE3 27 28
D
SSM3K7002FU_SC70-3~D 27
2
CA106 RA119 0.047U_0402_16V4Z AMGND 30 S SDMK0340L-7-F_SOD323-2~D 26
3
AMP_RIGHT 1 2 AMP_RIGHT-1 1 2 1
CA104 2 AMP_RIGHT_C 31 /FAULTZ RA44 25 26
2 1 1 2 CA102 32 INPR 1 2 10K_0402_5%~D 24 25
13.3K_0402_1% INNR 24
2.2U_0603_10V6K +GVDD RA116 5.9K_0402_5% 0.1U_0402_16V4Z 25 SPKR+ RA137 23
OUTPR 1 <43> CTL1 23
CA113
2.2U_0603_10V6K
AMGND 23 SPKR- AGND 66.5K_0402_1% 22
<35> USB20_N2_CONN
1
RA122 2 OUTNR 21 22
GVDD DEPOP#_EC <35> USB20_P2_CONN 21
1U_0603_25V6K
1 2 16 SPKL+ 20
<43> DEPOP#_EC
r
1
CA107 0.22U_0603_25V7K OUTPL 18 SPKL- 2 19 20

OUTNL <35> USB3RN4_R 19
CA100
SPKL+ 2 1 BSPL 15 18
10K_0402_5% BSPL <35> USB3RP4_R 18
SPKL- 2 1 BSNL 19 17
2
BSNL 7 SPK_MUTE QA12 16 17

CA108 0.22U_0603_25V7K <35> USB3TN4_R
CA109 0.22U_0603_25V7K MUTE AO3413_SOT23-3 15 16
MIC_BIAS_C <35> USB3TP4_R 15
AMGND SPKR+ 2 1 BSPR 26 AGND 14
BSPR <43> CTL2 14
2 1 BSNR 3
S
SPKR- 22 4 1 13
o
BSNR GND +3.3V_AVDD <35> USB20_N9_CONN 13
EMI@ RA130 10_0402_1% EMI@ CA83 330P_0402_50V CA110 0.22U_0603_25V7K 17 12
GND <35> USB20_P9_CONN 12
2.2K_0402_5%
RA126
1 2 2 1 SPKL+ 20 1 CA74 11
GND 11
1
AM0 10 21 0.1U_0402_16V7K 10
G
<35> USB3RN3_R
2
1 2 2 1 SPKL- AM1 9 AM0 GND 24 UA3 RA50 0_0402_5% 9 10

AM1 GND AUD_HP_OUT_L_C AUD_HP_OUT_L_CN <35> USB3RP3_R 9
EMI@ RA131 10_0402_1% EMI@ CA84 330P_0402_50V AM2 8 13 9 1 @ 2 8
AM2 33 2 16 VDD TIP_SENSE 5 JACK1_PLUG_C 1 2 JACK1_PLUG 7 8
GND VDD DET_TRIGGER <35> USB3TN3_R 7
EMI@ RA132 10_0402_1% EMI@ CA85 330P_0402_50V RA138 10K_0402_1% 6
F
<35> USB3TP3_R
2
1 2 2 1 SPKR+ TPA3131D2DAPR_QFN32_5X5 AGND 1 14 RING2 5 6
SCL RING2_SENSE <19> USB_OC2# 5
2 7 4
+3.3V_AVDD SDA RING2 <43> PWRSHARE_EN_EC# 4
1 2 2 1 SPKR- 4 3
A +3.3V_AVDD ADDR_SEL MIC_IN <34,43> USB_PWR_EN# 3 A
EMI@ RA133 10_0402_1% EMI@ CA86 330P_0402_50V 15 2 42
MIC_C_PLUG SLEEVE_SENSE <35> USBCHG_DET# JACK1_PLUG 2 G2
8 6 1 41
TI SA000074E00 MIC_PRESENT SLEEVE 1 1 G1
1
MIC1 11 17 CA81
RA115 12 MIC_P GND 3
TPA3131D2DAPR QFN 32P @ 10K_0402_1% MIC_N GND 10
10U_0402_6.3V6M
JIO
GND
1
+3.3V_AVDD 2
RA114 TS3A225ERTER_PWQFN16_3X3 SP01001DR00
2
2
10K_0402_1% @
JACK1_PLUG_C
Combo JACK Mic. switch
2
RA85 RA86 RA87 RA41 BAT54AW_SOT323-3

2
100K_0402_1% 100K_0402_1% 100K_0402_1% 10K_0402_5% DA15 AGND

3 EC_MUTE#
3
EC_MUTE# <43> QA14A

1
AM0 AM1 AM2 5

D
G @
1
SPK_MUTE# 1 DMN66D0LDW-7_SOT363-6
S
6
QA14B
4
2 EAPD# JACK1_PLUG 2
D
@
G
Codec Malcolm-EX
S
1
5 4 3 2 1

5 4 3 2 1
D D
ia l
n t
C
id e C
Empty page
n f
C o
B
L L B
D E
o r
A
F A

Reserved Page
5 4 3 2 1

5 4 3 2 1
+5VALW
1 1
CI1 CI2
4.7U_0603_10V
2 2
0.1U_0402_16V7K 2.0A +USB3_VCCA
<32,43> USB_PWR_EN#
USB_PWR_EN#
1
CI4
5
4
UI2
IN
EN
OUT
GND
OCB
1
3
80mil
1
USB_OC0# <19> RI1 1
@EMI@
2 0_0402_5%~D
JUSB1 On MB (Right Side)
D
SY6288D20AAC_SOT23-5 CI5 LI1 EMI@

USB20_N1 USB20_N1_CONN +USB3_VCCA
0.1U_0402_16V7K
1 2
2 <19> USB20_N1 +USB3_VCCA
0.1U_0402_16V7K
l
2
USB20_P1 4 3 USB20_P1_CONN JUSB1
<19> USB20_P1
10U_0603_6.3V6M~D
1
MCM1012B900F06BP_4P USB20_N1_CONN 2 VBUS
1
1
USB20_P1_CONN D-
ia
CI11
3
RI4 1 2 0_0402_5%~D 4 D+ CI10
@EMI@ USB3RN1_R 5 GND 47U_0805_6.3V6M~D
2
USB3RP1_R 6 StdA-SSRX- 2
7 StdA-SSRX+
USB3TN1_R 8 GND-DRAIN
t
USB3TP1_R 9 StdA-SSTX-
StdA-SSRX+
10
11 GND
2
USB3RN1_R GND
L30ESDL5V0C3-2_SOT23-3
USB3RN1 RI5 1 @ 2 0_0402_5% 12
<19> USB3RN1 GND
n
13
GND
DI2 +USB3_VCCA
ESD@
CONN@
e
Symbol check OK. 2/25
10P_0402_50V8J
1
@RF@
CI40
1
2
USB3RP1 RI8 1 @ 2 0_0402_5% USB3RP1_R
id
<19> USB3RP1
C DI3 ESD@ C
USB3TN1_L USB3TN1_R USB3RN1_R USB3RN1_R
f
RI11 1 @ 2 0_0402_5% 1 9
USB3RP1_R 2 8 USB3RP1_R
USB3TN1_R 4 7 USB3TN1_R
n
USB3TN1 CI30 1 2 0.1U_0402_10V6K~D USB3TN1_L USB3TP1_R 5 6 USB3TP1_R
<19> USB3TN1
USB3TP1 CI31 1 2 0.1U_0402_10V6K~D USB3TP1_L
<19> USB3TP1
USB3TP1_L RI13 1 @ 2 0_0402_5% USB3TP1_R 3
o
TVWDF1004AD0_DFN9
L C
B
E L B
r D
JUSB2 change to TypeC
A
F o A

USB 3.0/2.0 x2 (left side)
5 4 3 2 1

5 4 3 2 1
+3VLP +3VLP +3VLP +3VLP

LI7 EMI@
USB20_N2 USB20_N2_CONN
SDMK0340L-7-F_SOD323-2
1 2
<19> USB20_N2 USB20_N2_CONN <32>
1
D D
USB charge for DC S5
220K_0402_5%
USB20_P2 4 3 USB20_P2_CONN RU4
<19> USB20_P2 USB20_P2_CONN <32>
100K_0402_5% RU5 DU8 1
MCM1012B900F06BP_4P CU26
0.1U_0402_16V7K
2
2
5
l
CU27
1
P
2 1 2 NC 4
A Y USBCHG_DET_D <63>
G
2.2U_0603_6.3V6K
1
ia
UU5
3
TC7SZ14FU_SSOP5~D RU6
1M_0402_5%
2
t
MCM1012B900F06BP_4P DU9
3 4 USBCHG_DET# 2 1
<19> USB3RN4 USB3RN4_R <32> <32> USBCHG_DET# USBCHG_DET_EC# <43>
1 SDMK0340L-7-F_SOD323-2 1
2 1 CU28 CU29
<19> USB3RP4 USB3RP4_R <32>
n
0.1U_0402_16V7K 0.1U_0402_16V7K
EMI@ LI8
2 2
e
To PowerShare Port (On DB)
id
MCM1012B900F06BP_4P
USB3TN4_L 3 4
USB3TN4_R <32>
CI34 1 2 0.1U_0402_10V6K~D USB3TN4_L
<19> USB3TN4
C CI35 1 2 0.1U_0402_10V6K~D USB3TP4_L C
<19> USB3TP4 USB3TP4_L
f
2 1
USB3TP4_R <32>
EMI@ LI9
o n
L C
L
LI10 EMI@
USB20_N9 1 2 USB20_N9_CONN
<19> USB20_N9 USB20_N9_CONN <32>
USB20_P9 4 3 USB20_P9_CONN
<19> USB20_P9 USB20_P9_CONN <32>
B B
E
MCM1012B900F06BP_4P
D
MCM1012B900F06BP_4P
USB3RN3 3 4 USB3RN3_R
<19> USB3RN3 USB3RN3_R <32>
USB3RP3 2 1 USB3RP3_R
r
<19> USB3RP3 USB3RP3_R <32>
EMI@ LI12
A
<19> USB3TN3
<19> USB3TP3
USB3TN3
USB3TP3
CI36
CI37
1
1
F
2 0.1U_0402_10V6K~D USB3TN3_L
2 0.1U_0402_10V6K~D USB3TP3_L
oUSB3TN3_L
USB3TP3_L
MCM1012B900F06BP_4P
3
EMI@ LI11
4
1
USB3TN3_R
USB3TP3_R
USB3TN3_R <32>
USB3TP3_R <32>

USB 3.0/2.0 x2 (left side)
5 4 3 2 1

A B C D E F G H
1 1
ia l
n t
2
id e 2
n f
+3VS
Change to KXCNL-1010 LGA 16P
Free Fall Sensor
C o +3VS +5VS
Close to JHDD1
1U_0402_6.3V
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
10U_0603_6.3V6M
1 1 1 1 1 1
CN4
1 1
CN17
CN18
CN1
CN2
CN3
CN51
CN6
L
47P_0402_50V8J
@ 2 2 2 2 2 2
2 2 @ @
UN2
LNG3DM 10
1 RES 13
L
14 VDD_IO RES 15
VDD RES 16 Follow Compal common design.
FFS_INT1 11 RES
<17> FFS_INT1 FFS_INT2 9 INT 1 5
<17> FFS_INT2 INT 2 GND 12
3 GND 3
E
7
PCH_SMBDATA 6 SDO/SA0
<14,15,18,38> PCH_SMBDATA PCH_SMBCLK 4 SDA / SDI / SDO JHDD1
<14,15,18,38> PCH_SMBCLK SCL/SPC 2 1
8 NC 3 CN21 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P1_C 2 1
CS NC <16> SATA_PTX_DRX_P1 SATA_PTX_DRX_N1_C 2
CN22 1 2 0.01U_0402_16V7K 3
<16> SATA_PTX_DRX_N1 3
FFS_INT1 connect to PCH GPIO & EC S IC KXCNL-1010 LGA 16P
SATA_PRX_DTX_N1_C
4
4
CN19 1 2 0.01U_0402_16V7K 5
D
discuss with BIOS to use which pin <16> SATA_PRX_DTX_N1
CN20 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P1_C 6 5
<16> SATA_PRX_DTX_P1 7 6
8 7
+5VS +3VS 9 8
10 9
10
r
11
11
1
+3VS 12
<16> HDD_DET# 13 12
@
RN24 14 13
+5VS 15 14
100K_0402_5%~D
o
15
2
G
16
2
17 16
FFS_INT2 3 1 1 2 FFS_INT2_CONN FFS_INT2_CONN 18 17
19 18
S
20 19
21 20
F
QN3 DN1
L2N7002WT1G 1N SC-70-3 SDM10U45-7_SOD523-2 22 G1
23 G2
24 G3
G4
STARC_111H20-100000-G2-R
CONN@
4 4

HDD/ODD
A B C D E F G H

5 4 3 2 1
+3.3V_F347
D D
0.1U_0402_16V4Z~D
22P_0402_50V8J~D
0.1U_0402_16V4Z~D
1 2
CE3
CE4
1U_0402_6.3V
10P_0402_50V8J
1 1
CE2
+3.3V_F347
@RF@
place RE5 as close as UE1
CE1
CE59
@
2 1 I2C_DAT 4.7K_0402_5% 2 1 RE1
2
2 2
I2C_CLK 4.7K_0402_5% 2 1 RE2
l
UE1 RE3
6 2 SPI_MOCLK 1 @ 2 SPI_MOCLK_R
VDD P0.0 1 SPI_MOSO
USB20_P4 4 P0.1 32 SPI_MOSI 0_0603_5%
<19> USB20_P4 USB20_N4 D+ P0.2 SPI_MOCS# I2C_CLK
ia
RE4 5 31
<19> USB20_N4 D- P0.3 I2C_DAT
+5VALW 1 @ 2 0_0603_5% 30
P0.4 I2C_CLK I2C_DAT <38,41> SPI_MOCLK_R
W=40mils +3.3V_F347 7 29
REGIN P0.5 CALDERA_PRSNT# I2C_CLK <38,41>
RE5 1 @ 2 0_0603_5% 8 28
10P_0402_50V8J
+5VS VBUS P0.6 CDR_ON_ELC CALDERA_PRSNT# <41,43>
27
10P_0402_50V8J
CDR_ON_ELC <41>
1
1 2 ELC_8051_C2CK_RST# 9 P0.7
@RF@
@RF@
+3.3V_F347
t
ELC_8051_C2D_P3 RST#/C2CK SLP_S3
1U_0402_6.3V
CE57
CE58
RE7 10 26
P3.0/C2D P1.0 BATT_CHG_LED
0.1U_0402_16V4Z~D
1K_0402_1%~D 25 10K_0402_5% 2 1 RE8
10P_0402_50V8J
1 1 +3.3V_F347
2
1
PCIE_GEN3#_GEN2 P1.1
CE6
CE7
18 24 ACIN#
@RF@
<43> PCIE_GEN3#_GEN2 1 2 AMD#_NV_R 17 P2.0 P1.2 23 LID_SW_IN#_D 2 1 LID_SW_IN#
CE60
@
<43> AMD#_NV P2.1 P1.3 BATT_LOW_LED LID_SW_IN# <38,42,43>
@ RE19 0_0402_5% 16 22 DE1
2
P2.2 P1.4
n
2 2 15 21 SLP_S5 SDMK0340L-7-F_SOD323-2
14 P2.3 P1.5 20 CE8 @ 1 2 0.1U_0402_16V4Z~D
13 P2.4 P1.6 19 CE9 @ 1 2 0.1U_0402_16V4Z~D
12 P2.5 P1.7
+3.3V_F347 11 P2.6 3
e
P2.7 GND
JELC1 C8051F383-GQ_LQFP32_7X7
@
+3.3V_F347 1
1
CE13
CE14
CE15
CE16
CE17
CE18
2
2
0.1U_0402_16V4Z
CPN change to SA00007JF10

3
id
3 4
1 4
2014/04/28
CE10
5 1 1 1 1 1 1 UE2
5 6 SPI_MOSI 15_0402_5% 2 1 RE9 5 2 RE10 1 2 15_0402_5% SPI_MOSO
@ 6 +3.3V_F347 DI SO
2 7 SPI_MOCLK_R 15_0402_5% 2 1 RE11 6
C
GND1 8 2 2 2 2 2 2 CLK C
GND2 SPI_MOCS#
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
f
AMPHE_G846A06201EU RE12
1 2
10K_0402_5%~D
1
CS DEVICE SMBUS ADDRESS
Cloase to JELC1 MAXIM - LED 0100 000b
CONN@ 1 2 7
RE13 10K_0402_5%~D HOLD
RE14
1 2
10K_0402_5%~D
3
WP MAXIM - GPIO 0100 001b
n
+3.3V_F347 8
VCC VSS
4
I2C EEPROM 1010 000b
0.1U_0402_16V4Z~D
22P_0402_50V8J~D
1 EN25Q80A-100HIP_SO8
CE19
1
CE20
2
2
+3.3V_F347
C
1
RE15
100K_0402_5%
2
SLP_S3
L
1
D QE1 +3.3V_F347
2 2N7002K_SOT23-3
<18,43,45> PM_SLP_S3#
G
1
S
RE16 +3.3V_F347_1 +3VS
L
3
SIO_SLP_S3# change to PM_SLP_S3# 100K_0402_5%

+3VALW +3.3V_F347
2
SLP_S5
0_0603_5%
J2 @ RE6 RE18
1
+3.3V_F347 2 1 1 @ 2 1 2
B 2 1 B
E
D QE3 @
<18,43> PM_SLP_S5#
2 2N7002K_SOT23-3 JUMP_43X118 0_0603_5%
For Debugging
1
G
RE17 S
100K_0402_5% UE9
3
SIO_SLP_S5# change to PM_SLP_S5# 5 1

IN OUT
2
ACIN# 1 2
D
GND
+3.3V_F347 behavior
1
CE22
4 3 1 2
EN OC +3VS
2
D QE4
2N7002K_SOT23-3 +3.3V_F347
4.7U_0603_10V
2 SY6288C20AAC_SOT23-5
RE20 10K_0402_5%
S0 S3 S4 S5
<18,43,46,61,62> ACIN
G
S
AC IN ON ON ON ON
r
1
BATT only ON ON OFF OFF

3
RE21
100K_0402_5%
<43> 3V_F347_ON AC mode battery full in S5:turn off ELC controller
2
o
+3.3V_F347 BATT_LOW_LED
1
1
D QE6
RE23 2 2N7002K_SOT23-3
<43> BATT_LOW_LED#
100K_0402_5% G
F
S
2
BATT_CHG_LED
1
D QE7
2 2N7002K_SOT23-3
<43> BATT_CHG_LED#
G
S
3
A A

ELC (1)
5 4 3 2 1

5 4 3 2 1
MAX7313 change to TI TLC59116F PWM expander

Power LED W=20mils
+5VS
0.1U_0402_16V4Z
+3.3V_F347
AD3 AD2 AD1 AD1
+3.3V_F347 +3.3V_F347 +5VALW
0 0 1 1 1
+5VS
CE23
1
+5VALW
0.1U_0402_16V4Z
100K_0402_5%
RE25 1 JLOGO1 1
1
2
CE26
4.7K_0402_1% CE24 1
1
RE28
UE3 0.1U_0402_16V4Z 2
1
1
D LID_SW 3 2 D
2
RE40 RE43 24 27 2 LOGO_LED_R_DRV# 4 3 2
3
4.7K_0402_1%~D 4.7K_0402_1%~D RESET Vcc QE8
S LOGO_LED_G_DRV# 5 4
2
3 ALIEN_LED_R_DRV# Power_LED G
2 LOGO_LED_B_DRV# 6 5
I2C_CLK 25 OUT0 4 ALIEN_LED_G_DRV# 7 6
2
<37,38,41> I2C_CLK I2C_DAT SCL OUT1 ALIEN_LED_B_DRV# ALIEN_LED_R_DRV# 7

26 5 8
<37,38,41> I2C_DAT
1
SDA OUT2 6 LOGO_LED_R_DRV# AO3413_SOT23-3 ALIEN_LED_G_DRV# 9 8
AD0_2 31 OUT3 8 LOGO_LED_G_DRV# D QE9
D ALIEN_LED_B_DRV# 10 9
1
AD1_2 32 A0 OUT4 9 LOGO_LED_B_DRV# 2 2N7002K_SOT23-3 11 10
l
AD2_2 A1 OUT5 LED_R_7313#_A# <43> PWR_LED# 11
1 10 G 12
AD3_2 2 A2 OUT6 11 LED_G_7313#_A#
S
+5VALW_LED 13 12
A3 OUT7 14 LED_B_7313#_A# 14 GND
3
1
12 OUT8 15 PWR_R_7313# GND

N.C. OUT9 PWR_G_7313#
ia
13 16 ACES_50208-01201-P01_12P
RE42 RE44 28 N.C. OUT10 17 PWR_B_7313#
N.C. OUT11 HDD_R_7313# CONN@
4.7K_0402_1%~D 4.7K_0402_1%~D 29 19
30 N.C. OUT12 20 HDD_G_7313#
2
N.C. OUT13 21 HDD_B_7313#

1
OUT14
Logic up LED board

22 +5VALW
t
RE31 OUT15
10K_0402_5%~D 7 23
1
18 GND GND 33
GND GND
2
RE38
n
TLC59116FIRHBR_VQFN32_5X5 100K_0402_5%
+3.3V_F347_1 +3.3V_F347_1
1 2
LID_SW
D QE10
e
LID_SW_IN# 2 2N7002K_SOT23-3
4.7K_0402_1%
4.7K_0402_1%
<37,42,43> LID_SW_IN#
1
G
S
RE47
RE46
For IND/TP/HDD/PWR
3
QE16B
id
2
2
+3.3V_F347_1
G
+3.3V_F347_1 AD3 AD2 AD1 AD0 1 6
<40> I2C_CLK_347 I2C_CLK <37,38,41>
D
+3.3V_F347_1
5
0 1 0 0
1
G
C C
1
f
RE45 1 4 3
<40> I2C_DAT_347 I2C_DAT <37,38,41>
D
RE35 4.7K_0402_1% CE53
4.7K_0402_1% UE8 0.1U_0402_16V4Z QE16A
2
24 27 2
2
RESET Vcc
n
3 TP_LED_R#
I2C_CLK_347 25 OUT0 4 TP_LED_G#
I2C_DAT_347 26 SCL OUT1 5 TP_LED_B#
SDA OUT2 6 LTRON_LED_R_DRV#
OUT3 LTRON_LED_G_DRV# LTRON_LED_R_DRV# <39>
AD0 31 8
o
A0 OUT4 LTRON_LED_B_DRV# LTRON_LED_G_DRV# <39>
AD1 32 9
A1 OUT5 RTRON_LED_R_DRV# LTRON_LED_B_DRV# <39>
AD2 1 10
A2 OUT6 RTRON_LED_G_DRV# RTRON_LED_R_DRV# <39>
AD3 2 11
A3 OUT7 RTRON_LED_B_DRV# RTRON_LED_G_DRV# <39>
14
RTRON_LED_B_DRV# <39>
1
OUT8 KB_LED_R5_DRV#
RE34
12 15
N.C. OUT9 KB_LED_G5_DRV# KB_LED_R5_DRV# <39>
RE33 13 16
N.C. OUT10 KB_LED_B5_DRV# KB_LED_G5_DRV# <39>
4.7K_0402_1% RE36 28 17
C
N.C. OUT11 KB_LED_B5_DRV# <39>
4.7K_0402_1% 29 19
4.7K_0402_1%
30 N.C. OUT12 20
2
N.C. OUT13 21
1
OUT14 22
RE41 OUT15 To
10K_0402_5%~D 7 23
18 GND
GND
GND
GND
33 Hot +3VS_TOUCH
Key
2
L
TLC59116FIRHBR_VQFN32_5X5 R2 0_0603_5%
+3VS 1 @ 2
0.1U_0402_10V6K
1
For TouchPAD
C2
L
2
HDD_B
B
Power ON Circuit C17 B
E
0.1U_0402_16V4Z
1 2
3
JPWR1
1
+5VS_TP_LED 1
QE13B 2
5 DMN66D0LDW-7_SOT363-6 +3VLP 2 3
+3VS_TOUCH 3 4
ON/OFF switch +5VS 4 5
D
+5VALW_LED
4
+5VS 5 6
+3VALW
2
HDD_B_7313# 6 7
TP_LED_R# 7
100K_0402_5%
RE63 8
1
HDD_R 100K_0402_5% TP_LED_G# 8 9

TP_LED_B# 9
RE39
@ 10
SW1 LED_R_7313#_A# 10 11
r
1
SMT1-05-A_4P LED_G_7313#_A# 11 12
6
1 3 LED_B_7313#_A# 12 13
2
ON/OFFBTN# <43> HDD_R 13

Q2409 14
QE13A 2 4 B+_BIAS +5VS SI3456DDV-T1-GE3_TSOP6~D+5VS_TP_LED HDD_G 14 15
SATA_LED_ACT 1 HDD_B 15
2 DMN66D0LDW-7_SOT363-6 16
o
16
D
CE27 6 PWR_R_7313# 17
S
6
5
PWR_G_7313# 17
300K_0402_5%~D
0.1U_0402_16V7K 5 4 18
1
6
2
2 PWR_B_7313# 18
0.1U_0402_16V4Z
2 19
HDD_R_7313# 19
1U_0402_6.3V
R179
1 1 20
TP_CLK 20
C29
QE12A
1 21
G
HDD_G <43> TP_CLK TP_DATA 21
C2508
2 22
F 3
<16,29> PCH_SATALED# <43> TP_DATA 22 23
1
2 PCH_SMBCLK 23 24
1
2 <14,15,18,36> PCH_SMBCLK PCH_SMBDATA 24 25 31

<14,15,18,36> PCH_SMBDATA
3
EN_TPLED 25 GND1 32
26
@ ON/OFFBTN# 26 GND2 33
27
CAPS_LED# 27 GND3 34
1.5M_0402_5%~D
0.1U_0402_10V
QE12B R374 L2N7002WT1G 1N SC-70-3 28
1 <43> CAPS_LED#
1
1
D 28 GND4 35
R180
5 DMN66D0LDW-7_SOT363-6 1 2 WLES ON/OFF LED# 29
<28> WLES ON/OFF LED# NumLock LED_A# 29 GND5 36
C2509
2 @ 30
<43> TP_LED_EN <43> NumLock LED_A# 30 GND6
0_0603_5% G
4
Q2410 S 2 STARC_107K30-000001-G2
3
HDD_G_7313# CONN@
2
A A
Change Symbol OK
1
LID_SW 2
D QE14
2N7002K_SOT23-3
ON/OFF switch power button Touchpad LED circuit 2/18 -Tarry
Bottom Side pop only before MP
G
S
3

ELC (2)/TP/PWR SW
5 4 3 2 1

A B C D E
INT_KBD Conn.
KSI[0..7]
KSI[0..7] <43>
KSO[0..17]
KSO[0..17] <43>
ACES_50552-03001-001
KB_DET# 30 31
<20> KB_DET# 30 GND 32
KSO7 29
1 KSO0 28 29 GND 1
KSI1 27 28
KSI7 26 27 +3VS
KSO9 25 26
KSI6 24 25 +3VS
24
1
KSI5 23
KSO3 22 23 R149
22
1
KSI4 21 39K_0402_5%
KSI2 20 21 R148
20
6
KSO1 19 100K_0402_5%
Net follow Ranger.
2
KSI3 18 19 KB_LED_R5_DRV 2 G
D
ia
KSI0 17 18 Q2411B
Only Pin26 add KSO16 S
2
KSO13 16 17 @ DMN66D0LDW-7_SOT363-6
1
16
3
KSO5 15
KSO2 14 15 @ 5 G
D
KSO4 13 14 Q2411A @
t
S
KSO8 12 13 DMN66D0LDW-7_SOT363-6
4
KSO6 11 12
KSO11 10 11
KSO10 9 10 @
n
KSO12 8 9
KSO14 7 8 +3VS
KSO15 6 7
KSO16 5 6 +3VS
e
5
1
KSO17 4
3 4 R153
3
1
2 39K_0402_5%
GND 1 2 R152
id
1
6
100K_0402_5%
2
JKB1 CONN@ KB_LED_G5_DRV 2 G
D
S Q2412B
2
@ DMN66D0LDW-7_SOT363-6
1
3
2 2
f
+5VS @ 5 G
D
0.1U_0402_16V4Z
S Q2412A @
4
1
n
C27
@
JTRONF
2 1 +3VS
1
o
2
RTRON_LED_R_DRV# 3 2 +3VS
<38> RTRON_LED_R_DRV# 3
1
RTRON_LED_G_DRV# 4
<38> RTRON_LED_G_DRV# RTRON_LED_B_DRV# 4
5 R173
<38> RTRON_LED_B_DRV# 5
1
LTRON_LED_R_DRV# 6 39K_0402_5%
<38> LTRON_LED_R_DRV# LTRON_LED_G_DRV# 6
7 R172
<38> LTRON_LED_G_DRV#
C
7
6
LTRON_LED_B_DRV# 8 100K_0402_5%
<38> LTRON_LED_B_DRV#
2
9 8 KB_LED_B5_DRV 2 G
D
10 9 S Q2413B
2
11 10 @ DMN66D0LDW-7_SOT363-6
1
11
3
12
13 12 @ 5 G
D
14 GND S Q2413A @
GND
L
4
ACES_50208-01201-P01
CONN@
@
TRON LED Board (F) CONN
E L Hot Key Conn.

PWM
Hot Key Conn.
Key Pad
3
r D Change Symbol OK
2/18 -Tarry
JKB3 CONN@
G4 9
G3 8
G2 7
G1
10
<43> KP_DET#
KP_DET#
KSO16
KSI0
KSI5
KSI1
KSI4
1
3
5
7
9
11
JKB2 CONN@
1
3
5
7
9
2
2 4
4 6
6 8
8 10
10 12
KP_DET#
KSO16
KSI0
KSI5
KSI1
KSI4
o
6 KSI2 13 11 12 14 KSI2
+5VS 6 6 13 14 16
5 KSI3 15 KSI3
KB_LED_R5_DRV# 4 5 GND 17 15 16 18 GND
<38> KB_LED_R5_DRV# KB_LED_G5_DRV# 4 4 17 18 20
3 GND 19 GND
<38> KB_LED_G5_DRV# KB_LED_B5_DRV# 3 19 20
2
F
<38> KB_LED_B5_DRV# 2 2
1 ACES_50611-0100N-001_10P
1
ACES_87153-06411
4 4

Title
KB/HotKey conn
0.1
LA-C912P
A B C D E

5 4 3 2 1
1/28 ADD +5V_LED +5V_LED

+5VS RE104 1 @ 2 0_0603_5% +5V_LED +3VS
1
RE105 1 @ 2 0_0603_5% +3VS
+3VS KB_LED_R1_DRV#_A# KB_LED_R3_DRV#_A#
R144 R145
1
39K_0402_5% 39K_0402_5%
1
R146
6
100K_0402_5% R147
2
KB_LED_R1_DRV 2 G
D
100K_0402_5% KB_LED_R3_DRV 2 G
D
S Q28B S Q34B
2
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
1
3
3
D KB_LED_R1_DRV# 5 G
D
KB_LED_R3_DRV# 5 G
D
D
S Q28A S Q34A
4
K/B Backlight +5V_LED +5V_LED
l
+3VS
AD3 AD2 AD1 AD0
1
+3.3V_F347_1 +3VS
+3.3V_F347_1 +3.3V_F347_1 R150 KB_LED_G1_DRV#_A# R151 KB_LED_G3_DRV#_A#
0 0 1 0
ia
39K_0402_5% 39K_0402_5%
1
1
RE32
6
4.7K_0402_1% 1 R154 R155
2
CE25 100K_0402_5% KB_LED_G1_DRV 2 G
D
100K_0402_5% KB_LED_G3_DRV 2 G
D
UE4 0.1U_0402_16V4Z Q29B Q35B
t
S S
1
2
1
3
3
RE26 24 27 2
4.7K_0402_1%~D RESET Vcc KB_LED_G1_DRV# 5 G
D
KB_LED_G3_DRV# 5 G
D
3 KB_LED_R1_DRV# Q29A Q35A
n
S S
I2C_CLK_347 25 OUT0 4 KB_LED_G1_DRV# DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
<38> I2C_CLK_347
2
4
I2C_DAT_347 26 SCL OUT1 5 KB_LED_B1_DRV#
<38> I2C_DAT_347 SDA OUT2 KB_LED_R2_DRV#
6
AD0_1 31 OUT3 8 KB_LED_G2_DRV#
e
AD1_1 32 A0 OUT4 9 KB_LED_B2_DRV# +5V_LED +5V_LED
AD2_1 1 A1 OUT5 10 KB_LED_R3_DRV#
AD3_1 2 A2 OUT6 11 KB_LED_G3_DRV#
A3 OUT7
1
14 KB_LED_B3_DRV# +3VS +3VS
id
OUT8
1
12 15 KB_LED_R4_DRV# R156 KB_LED_B1_DRV#_A# R157 KB_LED_B3_DRV#_A#

13 N.C. OUT9 16 KB_LED_G4_DRV# 39K_0402_5% 39K_0402_5%
4.7K_0402_1% RE30
4.7K_0402_1% RE27
N.C. OUT10
1
RE29 28 17 KB_LED_B4_DRV#
N.C. OUT11
6
4.7K_0402_1%~D 29 19 R158 R159
2
C 30 N.C. OUT12 20 100K_0402_5% KB_LED_B1_DRV 2 G
D
100K_0402_5% KB_LED_B3_DRV 2 G
D
C
f
2
N.C. OUT13 21 S Q30B S Q36B

OUT14
1
RE37 22 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
1
OUT15
3
10K_0402_5%
7 23 KB_LED_B1_DRV# 5 G
D
KB_LED_B3_DRV# 5 G
D
GND GND
n
18 33 S Q30A S Q36A
GND GND DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
2
4
TLC59116FIRHBR_VQFN32_5X5
o
+5V_LED +5V_LED
1
+3VS +3VS
R160 KB_LED_R2_DRV#_A# R161 KB_LED_R4_DRV#_A#
C
39K_0402_5% 39K_0402_5%
1
6
6
R162 R163
2
100K_0402_5% KB_LED_R2_DRV 2 G
D
100K_0402_5% KB_LED_R4_DRV 2 G
D
S Q31B S Q37B
1
3
3
KB_LED_R2_DRV# KB_LED_R4_DRV#
L
5 5
D D
G G
JKBBL1 S Q31A S Q37A

1 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
4
2 1
KB_LED_R1_DRV#_A# 3 2
KB_LED_G1_DRV#_A# 4 3
L
KB_LED_B1_DRV#_A# 5 4
KB_LED_R2_DRV#_A# 6 5 +5V_LED +5V_LED
KB_LED_G2_DRV#_A# 7 6
KB_LED_B2_DRV#_A# 8 7
8
1
B KB_LED_R3_DRV#_A# 9 +3VS +3VS B
E
KB_LED_G3_DRV#_A# 10 9 R164 KB_LED_G2_DRV#_A# R165 KB_LED_G4_DRV#_A#
KB_LED_B3_DRV#_A# 11 10 39K_0402_5% 39K_0402_5%
11
1
1
KB_LED_R4_DRV#_A# 12
12
6
KB_LED_G4_DRV#_A# 13 R166 2 R167
2
KB_LED_B4_DRV#_A# 14 13 100K_0402_5% KB_LED_G2_DRV 2 G
D
100K_0402_5% KB_LED_G4_DRV 2 G
D
15 14 Q32B Q38B
D
+5VS
S S
16 15 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
2
1
16
3
3
17
18 17 KB_LED_G2_DRV# 5 G
D
KB_LED_G4_DRV# 5 G
D
19 18 21 S Q32A S Q38A
20 19 GND 22 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
r
4
4
20 GND
ACES_50552-02001-001
CONN@
o
+5V_LED +5V_LED
KB BL LED
1
1
+3VS +3VS
R168 KB_LED_B2_DRV#_A# R169 KB_LED_B4_DRV#_A#
F
39K_0402_5% 39K_0402_5%
1
1
6
6
R170 R171
2
2
100K_0402_5% KB_LED_B2_DRV 2 G
D
100K_0402_5% KB_LED_B4_DRV 2 G
D
S Q33B S Q39B
2
1
3
3
KB_LED_B2_DRV# 5 G
D
KB_LED_B4_DRV# 5 G
D
S Q33A S Q39A
4
4
A A

Title
ELC(3)
0.1
LA-C912P
5 4 3 2 1

5 4 3 2 1
PCIE_CLK_BUFFER
+3VS
+3VS +3VS
2 1
0.1U_0402_10V7K
0.1U_0402_10V7K
CM16
CM17
1 1
1
RM18 CM19
1
2.2_0402_1% 22U_0603_6.3V6M
1
RM96 RM20
2
E C 控制 P IN
RM21 @ 4.7K_0402_5% 1K_0402_1% 2 2
1K_0402_1%
PCI_SMCLK
2
UM4
2
1 20
2 PLL_BW_SEL VDDA 19
PCI_SMDAT
<17> CLK_PCIE_P7 3 SRCIN GNDA 18 2 1 475_0402_1%
RM25
CLKREQ#_DGPU
<17> CLK_PCIE_N7 4 SRCIN# IRef 17
OE_0# OE_1# CLKREQ#_DGPU <17,43>
USB_PWR_EN#
5 16
+3VS VDD VDD +3VS
6 15 CLK_PCIE_DGPU_C
7 GND GND 14 2 1 CM98 1 2 0.01U_0402_16V7K CLK_PCIE_DGPU#_C
DOCKING_LED ON# 8 CLK0 CLK1 13 2 RM27 1 33_0402_1% CM99 1 2 0.01U_0402_16V7K

9 CLK0# CLK1# 12 RM28 33_0402_1%
10 VDD VDD 11
DOCKING_LED OFF#
1
1
SDATA SCLK
49.9_0402_1%
RM29
49.9_0402_1%
RM38
1U_0402_6.3V
0.1U_0402_10V7K
0.1U_0402_10V7K
CM18
CM20
1 1
1
DOCK_PSID
CM21
PI6CEQ20200LIEX
D D
2 2
DOCK_ACIN
2
2
2
DOCK_EN
PRSNT#_R
l
<18> SML0DATA
<18> SML0CLK
ia
+5VALW
1
+3VALW
RM91
+5VALW 549_0402_1%
0.1U_0402_10V7K
1 CDRA_LED WHITE_R_R
2
1
CM70
RM92
100K_0402_5%~D
<43> CDR_TXRX_GOOD 2@
CDRA_LED WHITE 20mil
3
S
CDRA_LED WHITE_R#
CDRA_LED WHITE_R_R 20mil
2
5
2
G
1
P
+3VALW B 4 QM1
2 O CDR_ON_ELC <37>
AO3413_SOT23-3
6
A
Caldera connector G
D
CDRA_LED WHITE_R QM2B
1
1
2
D
G
3
<43> CDRA_LED WHITE_R S
CDRA_LED WHITE
RM41 TC7SH08FU_SSOP5~D DMN66D0LDW-7_SOT363-6
1
100K_0402_5% UM7
e
JCDRA
2
1
Caldera_ON 2 CALDERA_ON <43>
Caldera_PWRGD PEG_HTX_C_GRX_P8 CALDERA_ PWRGD <43>
3 +5VALW
PEG_HTX_C_GRX_N8
1
T0+ 4
T0- 5 PEG_HTX_C_GRX_P9
1
GND 6 RM42 +5VALW
T1+ PEG_HTX_C_GRX_N9
7 470K_0402_5% RM93
T1- 8 100_0402_1%
PEG_HTX_C_GRX_P10
2
1
GND
221 ohm for white LED
9 PEG_HTX_C_GRX_N10
T2+ 10 PEG_HTX_C_GRX_P[8..11] <7>
RM94
id
CDRA_LED RED_R_R
316 ohm for red LED
PEG_HTX_C_GRX_N[8..11] <7>
2
T2- 11 100K_0402_5%~D
GND PEG_HTX_C_GRX_P11
12 1 2 0_0402_5%
on dock cable side
RI75 @
PEG_HTX_C_GRX_N11
Follow ZAP00 design.
3
T3+ S
CDRA_LED RED 20mil
13 +3VALW
2
T3- 14 2
G
CRX_P8 USB3RP5_R USB3RP5_L
GND 15 CRX_N8 USB3RN5_L CDRA_LED RED_R_R 20mil
1
R0+ 16 2 1 CI38 USB3RN5

R0- USB3RP5_L 0.1U_0402_10V6K USB3RN5 <19>
QM3
17 CRX_P9 RM5 USB3RN5_R USB3RN5_L 0.1U_0402_10V6K 2 1 CI39 USB3RP5 AO3413_SOT23-3
GND USB3RP5 <19>
3
18 CRX_N9 10K_0402_5% CDRA_LED RED_R QM2A
D
1
R1+ 19 <43> CDRA_LED RED_R 5 G
D
R1- 20 CDRA_LED RED

S
2
GND 21 DMN66D0LDW-7_SOT363-6
CDRA_RST# CALDERA_PRSNT# <37,43>
4
C CALDERA_PRSNT# 22 RI76 1 @ 2 0_0402_5% C
PLTRST#
f
23 CRX_P10
GND 24
R2+ CRX_N10
25 CDR_BTN#
R2- 26
BUTTON# CDRA_LED WHITE CDR_BTN# <43>
27 CDRA_LED RED
2
LED_WHITE 28 +3VALW
LED_RED 29 1 2 0_0402_5%
0.1U_0402_10V7K
CRX_P11 RM17 RI77 @
GND 30 CRX_N11 100K_0402_5% 1
R3+ 31 2 1
CM23
R3- USB3TP5_R
32 CLK_PCIE_DGPU_C USB3TP5
USB3TP5 <19>
1
GND 33 RM6
n
REFCLK+ CLK_PCIE_DGPU#_C
34 @ 2 10K_0402_5%
REFCLK- USB3TN5_R
35 USB3RN5_R USB3TN5
USB3TN5 <19>
5
GND 36
SSTX+ USB3RP5_R
37 CDRA_RST#
1
P
SSTX- B CALDERA_RST# <43>
38 USB20_P3_CONN 4
GND 39 RI78 1 @ 2 0_0402_5% O 2
USBD+ USB20_N3_CONN A PCH_PLTRST# <17,46>
G
40
USBD- 41 UM3
USB3TN5_R
3
GND 42 TC7SH08FU_SSOP5
SSRX+ USB3TP5_R
43
o
SSRX- 44
GND CDR_I2C_CLK
45 MCM1012B900F06BP_4P
I2C_CLK CDR_I2C_DAT USB20_P3_CONN USB20_P3
46 3 4
I2C_DATA 47 USB20_P3 <19>
GND 48
GND USB20_N3_CONN USB20_N3
49 2 1
GND 50 USB20_N3 <19>
GND CDR_I2C_DAT I2C_DAT
RM45 1 @ 2 0_0402_5% EMI@ LM1
I2C_DAT <37,38>
CDR_I2C_CLK I2C_CLK
TE_2260531-1 RM46 1 @ 2 0_0402_5%
I2C_CLK <37,38>
CONN@
CDR_I2C_CLK
C
CDR_I2C_DAT 0_0402_5% 2 @ 1 RM89
2 1 RM90 EC_SMB_CK2 <18,41,42,43,46,60>
0_0402_5% @
EC_SMB_DA2 <18,41,42,43,46,60>
L
+2.5VOUT
20mil
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1 1 1 1 1
CM9
CM32
CM34
CM35
CM36
Tie 1kΩ to VDD = Register Access SMBus Slave mode
L
2 2 2 2 2 FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ to GND = Pin Mode
PEG_GTX_HRX_P[8..11] <7>
PEG_GTX_HRX_N[8..11] <7> +3VS
14
41
36
51
9
UM8
VDD
VDD
VDD
VDD
VDD
PEG_GTX_HRX_P11 PEG_GTX_HRX_C_P11 CRX_P11

PEG_GTX_HRX_N11 CM67 1 2 0.22U_0402_10V6K PEG_GTX_HRX_C_N11 1 45 CRX_N11
OUTB_0+ INB_0+
2
PEG_GTX_HRX_P8 CM69 1 2 0.22U_0402_10V6K PEG_GTX_HRX_C_P8 2 44 CRX_P8
CM63 1 2 0.22U_0402_10V6K 3 OUTB_0- INB_0- 43
PEG_GTX_HRX_N8 PEG_GTX_HRX_C_N8 OUTB_1+ INB_1+ CRX_N8
PEG_GTX_HRX_P10 CM66 1 2 0.22U_0402_10V6K PEG_GTX_HRX_C_P10 4 42 CRX_P10 RM66
OUTB_1- INB_1-
E
To PCH Form Caldera
PEG_GTX_HRX_N10 CM68 1 2 0.22U_0402_10V6K PEG_GTX_HRX_C_N10 5 40 CRX_N10 1K_0402_1%
B CM62 1 2 0.22U_0402_10V6K 6 OUTB_2+ INB_2+ 39 B
PEG_GTX_HRX_P9 PEG_GTX_HRX_C_P9 CRX_P9
1
CM64 1 2 0.22U_0402_10V6K 7 OUTB_2- INB_2- 38
PEG_GTX_HRX_N9 PEG_GTX_HRX_C_N9 OUTB_3+ INB_3+ CRX_N9
CM65 1 2 0.22U_0402_10V6K 8 37 ENSMB
OUTB_3- INB_3-
1
10 35
11 INA_0+ OUTA_0+ 34 @
12 INA_0- OUTA_0- 33 RM67 0_0402_5% RM64
13 INA_1+ OUTA_1+ 32 DEMA1 2 @ 1 1K_0402_1%
15 INA_1- OUTA_1- 31 EC_SMB_CK2 <18,41,42,43,46,60>
2
16 INA_2+ OUTA_2+ 30 DEMA0 2 @ 1

17 INA_2- OUTA_2- 29 EC_SMB_DA2 <18,41,42,43,46,60>
RM68 0_0402_5%
18 INA_3+ OUTA_3+ 28
INA_3- OUTA_3-
54 DEMB1
DEMB1/AD0
D
EQA1 19 53 DEMB0 CALDERA_PRSNT#
EQA0 20 EQA1 DEMB0/AD1 52 RM61 2 1 20K_0402_5%
RATE 21 EQA0 PRSNT 50 DEMA1
RXDET 22 RATE DEMA1/SCL 49 DEMA0
+3VS RXDET DEMA0/SDA 48 ENSMB Tie 1kΩ to GND = Root Complex Loopback (INA_n to OUTB_n
ENSMB 47 EQB1
+3VS
LPBK 23 EQB1/AD2 46 EQB0
Float = Normal Operation
W=20mil LPBK EQB0/AD3 Tie 1kΩ to VDD = End-point Loopback (INB_n to OUTA_n)
24
VIN
10U_0805_10V4Z
10U_0805_10V4Z
VGA_EN VGA_EN 25
VDD_SEL
1U_0402_6.3V
1U_0402_6.3V
1 2 26
27 SD_TH/READ_EN 55
1 1 1 1 ALL_DONE DAP_GND
CM29
CM30
CM31
CM33
RM14 +3VS
1
r
1K_0402_1%
@ @
RM87 2 2 2 2 RM72 DS80PCI402SQNOPB_WQFN54_10X5P5 RM74
10K_0402_5% 10K_0402_5% 1K_0402_1%
1 2 LPBK
2
1 2
@
RM78
1K_0402_1%
o
Level control Set t i ngs
EQ Set t i ngs DEMA Set t i ngs
Tie 1kΩ to GND = GEN 1,2
DEMA1 DEMA0 Float = Auto Rate select
EQA1 EQA0 db at db at Level DEMB1 DEMB0 DEM dB Suggested Use Level Pin Set t i gn Descript i on Tie 20kΩ to GND = GEN 3 without De-emphasis
Level EQB1 EQB0 2.5G 4G Suggested Use
1 0 0 0 <5 inch 4– m
il tr ace 1 0 1kΩ to GND <5 inch 4– m
il tr ace Tie 1kΩ to VDD = GEN 3 with De-emphasis
1 0 0 3.7 4.9 < 5 inch trace
<5 inch 4– m
il tr ace to GND <5 inch 4– m
il tr ace
F
2 0 R 0 2 R 20kΩ +3VS
2 0 R 5.8 7.9 5 inch 5– m
il tr ace
3 0 F -3.5 10 inch 4– m
il tr ace 3 F Float 10 inch 4– m
il tr ace @
3 0 F 7.7 9.9 5 inch 4– m
il tr ace RM71
4 0 1 0 <5 inch 4– m
il tr ace 4 1 1kΩ to VDD <5 inch 4– m il tr ace 1K_0402_1%
4 R 1 8.9 11 10 inch 5– m
il tr ace 1 2 RATE
5 R 0 -3.5 10 inch 4– m
il tr ace
5 R 0 11.2 14.3 10 inch 4– m
il tr ace 1 2
6 R R -6 15 inch 4– m
il tr ace
6 R R 11.4 14.6 15 inch 4– m
il tr ace @
7 R F 0 <5 inch 4– m
il tr ace RM69
7 R F 13.5 17 20 inch 4– m
il tr ace 20K_0402_1%~D
8 R 1 -3.5 10 inch 4– m
il tr ace
8 R 1 15 18.5 25 to 30 inch 4– m
il tr ace
9 F 0 -6 15 inch 4– m
il tr ace
9 F 0 12.8 18 30 inch 4– m
il tr ace +3VS
10 F R 0 <5 inch 4– m
il tr ace Auto RX-Detect
10 F R 17.4 22 35 inch 4– m
il tr ace @
11 F F -3.5 10 inch 4– m
il tr ace RM77
11 F F 19.7 24.4 10m, 30awg cable 4.99K_0402_1%
12 F 1 -6 15 inch 4– m
il tr ace 2 1 RXDET
12 F 1 21.1 25.8
13 1 0 0 <5 inch 4– m
il tr ace 2 1
13 1 0 21.7 27.4
10m – 12 mcabl e 14 1 R -3.5 10 inch 4– m
il tr ace @
RM73
14 1 R 23.5 29.0
15 1 F -6 15 inch 4– m
il tr ace 4.99K_0402_1%
15 1 F 25.8 31.4
16 1 1 -9 20 inch 4– m
il tr ace
16 1 1 27.3 32.7
A A
@
EQ*MB @ DEM*EGPU
RM76 RM26 +3VS +3VS
1K_0402_1% 1K_0402_1% @
1 2 1 2 RM63
+3VS +3VS
RM86 1K_0402_1%
1K_0402_1% 1 2 DEMA1
1 2 EQA1 1 2 EQB1 1 2 DEMB1
1 2
RM70 RM23 1 2
1K_0402_1% 1K_0402_1% @
@ RM65
RM62 1K_0402_1%
1K_0402_1%
@ @
RM81 RM85 +3VS +3VS
1K_0402_1% 1K_0402_1%
1 2 1 2 @ @
+3VS +3VS
RM79 RM83
1K_0402_1% 1K_0402_1%
1 2 EQA0 1 2 EQB0 1 2 DEMB0 1 2 DEMA0
RM84 RM82 1 2 1 2
1K_0402_1% 1K_0402_1%
RM75 RM88
1K_0402_1% 1K_0402_1%
@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/01/30 Deciphered Date 2016/12/31 Titl e
USB3.0
D a te : Wednesday, July 22, 2015 She e t 41 of 78
5 4 3 2 1

5 4 3 2 1
+3VS +5VS
22U_0805_6.3VAM
1
CF4
+3VS
10K_0402_5%
10K_0402_5%
10K_0402_5%
2
2
2
RF1
RF2
RF3
0.1U_0402_10V7K
1
CF6
D @ D
Address:100_1100
1
2 JFAN1
SENSOR_DIODE_P1
1
U2410 @ 2 1
1 1 EC_SMB_CK2 <43> CPU_FAN_PWM 2
1
@ C 1 8 2 1 3
VDD SCLK EC_SMB_CK2 <18,41,43,46,60> <43> CPU_FAN_FB 3
SKIN
CF2 2 CF3 @ DF1 4
2 7 EC_SMB_DA2 5 4
100P_0402_50V8J B 470P_0402_50V7K SDMK0340L-7-F_SOD323-2
2 2 D+ SDATA EC_SMB_DA2 <18,41,43,46,60> 6 G5
SENSOR_DIODE_N1
E QF2 @
3
MMBT3904WT1G_SC70-3 3 6 G6
D- ALERT# ACES_50273-00401-001
Diode circuit s used for SKIN sensor

4
THERM# GND
5
CPU FAN Control circuit CONN@
ADM1032ARMZ-REEL_MSOP8
+3VS +5VS
ia l
22U_0805_6.3VAM
1
CF5
10K_0402_5%
10K_0402_5%
10K_0402_5%
2
2
2
RF4
RF5
RF6
1
1
Fintek thermal sensor-> CPU core, DIMM 1
JFAN2
2 1
n
<43> GPU_FAN_PWM 2
2 1 3
<43> GPU_FAN_FB 3
DF2 4
+3VS SDMK0340L-7-F_SOD323-2 5 4
+3VS 6 G5
G6
1
ACES_50273-00401-001
e
1 R181 CONN@
C2498
0.1U_0402_10V6K
U2407 10K_0402_5%
@
Thermal Board for SSD
GPU FAN Control circuit
2
2 EC_SMB_CK2
1 10
VCC SCL EC_SMB_CK2 <18,41,43,46,60>
JTH1
EC_SMB_DA2
C REMOTE1+ 2 9 REMOTE3+ 1 C
DP1 SDA EC_SMB_DA2 <18,41,43,46,60> 1
2
id
R184 REMOTE3-
REMOTE1- 1 @ 2 REMOTE2- 3 8 2
DN ALERT#
REMOTE2+ 0_0402_5% 4 7 3
DP2 THERM# R185 4 G1
REMOTE3+ 5 6 1 @ 2 REMOTE3- G2
DN3 DP3 GND/DN3
0_0402_5% ACES_50273-0020N-001_2P
Address 1001_101xb
f
2nd source
SA000029210-->EMC1403-2-AIZL-TR
n
REMOTE1,2 (+/-) :
TOP CPU PWR Trace width/space:10/10 mil
Close U2407 REMOTE1+
Trace length:<8"
1
REMOTE1+ C
o
1 @ C2500 2 Q2407
2200P_0402_50V B MMST3904-7-F_SOT323-3
2
C2502 E
3
2200P_0402_50V REMOTE1-
2 REMOTE1-
REMOTE2+
1
REMOTE2+ BOTTOM GPU PWR
C
C2504
1
2200P_0402_50V C
2 REMOTE2- @ C2505 2 Q2408
2200P_0402_50V B MMST3904-7-F_SOT323-3
2
E
3
REMOTE3+ REMOTE2-
1
C2510
2200P_0402_50V
2 REMOTE3-
Lid Switch
L
(Hall Effect Switch)
B +3VALW B
0.1U_0402_16V4Z~D
L
1
2
UH5
CH2
VDD
2
LID_SW_IN#
3
OUTPUT LID_SW_IN# <37,38,43>
GND
E
1
CH1
1
10P_0402_50V8J~D
AH1806-W-7 SC59 3P OMNIPOLAR SW 2
r D
A
F o Security Classification
Compal Secret Data
Deciphered Date 2016/12/31
Title
Size
FAN/TP/PWR SW
Document Number Rev
0.1
A
5 4 3 2 1

5 4 3 2 1
SD028000080 0_0402_5%
+3VALW
SD034120280 12K_0402_1%
Board ID
SD034100300 27K_0402_1%
2
NV:5 RE64
MP Ra 100K_0402_1% SD034430280 43K_0402_1%
EMI@ SD034560280 56K_0402_1%
1
LE1 +EC_VCCA AD_BID0
+3VALW FBMA-L11-160808-800LMT_0603 SD034750280 75K_0402_1%
1 SD034100380 100K_0402_1%
2
1 2 +EC_VCCA
Rb RE66 CE28
1
CE29
1
CE30
2
@EMI@
2
@EMI@ 1 33K_0402_1% 0.1U_0402_10V7K SD034130380 130K_0402_1%
0.1U_0402_10V7K 0.1U_0402_10V7K CE31 CE32 +3VLP CE33 2
D
1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_10V7K SD034160380 160K_0402_1% D
1
2 2 1 1
2 SD034200380 200K_0402_1%
ECAGND
ECAGND <61> SD000001B80 240K_0402_1%
PLT_RST#
1
SD00000G280 270K_0402_1%
111
125
CE34 ESD@
22
33
96
67
SD034330380 330K_0402_1%
l
UE5
9
0.047U_0402_16V4Z
SD028430380 430K_0402_1%
VCC0
VCC
VCC
VCC
VCC
VCC_LPC
AVCC
2
2 1
+3VS_WLAN_NGFF
ia
10K_0402_5% RE92
Place CC30 CDRA_LED WHITE_R
<28> WLAN_WAKE# 1 21
close to RC51.1 KB_RST# 2 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F 23 BEEP#
<19> KB_RST# 3 KBRST#/GPIO01 BEEP#/GPIO10 26 CPU_FAN_PWM BEEP# <32>
SERIRQ
<19> SERIRQ LPC_FRAME# 4 SERIRQ EC_FAN_PWM/GPIO12 27 GPU_FAN_PWM CPU_FAN_PWM <42>
<19> LPC_FRAME# LPC_AD3 LPC_FRAME# PWM Output AC_OFF/GPIO13 GPU_FAN_PWM <42>
5
t
<19> LPC_AD3 LPC_AD2 7 LPC_AD3 2 1 100P_0402_50V8J ECAGND CDRA_LED WHITE_R
@EMI@ @EMI@ CE35
<19> LPC_AD2 LPC_AD1 8 LPC_AD2 63 BATT_TEMP CDRA_LED WHITE_R <41>
CE36 RE89
<19> LPC_AD1 LPC_AD0 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 PCIE_WAKE# BATT_TEMP <61,62> CDRA_LED RED_R
0.1U_0402_10V7K 0_0402_5% LPC & MISC
2 1 1 2 <19> LPC_AD0 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 65 ADP_I PCIE_WAKE# <18,29,30> CDRA_LED RED_R <41>
CLK_PCI_LPC 12 ADP_I/AD2/GPIO3A 66 AD_BID0 ADP_I <61,62>
n
<19> CLK_PCI_LPC PLT_RST# CLK_PCI_EC AD Input AD_BID/AD3/GPIO3B USBCHG_DET_EC#
13 75
<17,28,29,30,31,58> PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 PANEL_BKLEN USBCHG_DET_EC# <35>
+3VALW RE68 2 @ 1 47K_0402_5% 37 76
PANEL_BKLEN <16>
EC_SCI# 20 EC_RST# AD5/GPIO43
2 @ 1 0.1U_0402_10V7K <20> EC_SCI# PM_SLP_SUS# 38 EC_SCI#/GPIO0E
CE37
e
<18> PM_SLP_SUS# CLKRUN#/GPIO1D
68 EN_INVPWR
KB9022 no need pull Hi. DA0/GPIO3C 70 TBT_PCIE_WAKE# EN_INVPWR <25>
+3VALW
DA Output EN_DFAN1/DA1/GPIO3D ME_SUS_PWR_ACK TBT_PCIE_WAKE# <58>
KSI0 55 71
56 KSI0/GPIO30 DA2/GPIO3E 72 LCD_TEST ME_SUS_PWR_ACK <18>
KSI1
id
KSI[0..7] 57 KSI1/GPIO31 DA3/GPIO3F LCD_TEST <25>
KSI2
<39> KSI[0..7] 58 KSI2/GPIO32 83 EC_MUTE#
KSI3
2 1 GPU_OVERT# KSO[0..17] KSI4 59 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 84 PM_SLP_S4# EC_MUTE# <32> IMVP_VR_ON
<39> KSO[0..17] KSI5 60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85 CDR_TXRX_GOOD PM_SLP_S4# <18,45,65>
RE102 100K_0402_5% 1
2 1 GPU_ALERT# 61 KSI5/GPIO35 PSCLK2/GPIO4C 86 SYS_PWROK CDR_TXRX_GOOD <41>
C KSI6 PS2 Interface CE38 ESD@ C
62 KSI6/GPIO36 PSDAT2/GPIO4D 87 TP_CLK SYS_PWROK <18>
RE99 100K_0402_5% KSI7
f
1 2 EN_WOL# 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA TP_CLK <38>
KSO0 0.1U_0402_10V7K
KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <38> 2
RE79 10K_0402_5%
1 2 LID_SW_IN# KSO2 41 KSO1/GPIO21
RE70 10K_0402_5% KSO3 42 KSO2/GPIO22 97 SUSACK#
43 KSO3/GPIO23 ENKBL/GPXIOA00 98 EN_WOL# SUSACK# <18> Place CE34
KSO4
n
KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 ME_EN EN_WOL# <30> between DE1 and RE12
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH ME_EN <18>
+3VALW KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <61>
KSO8 47 KSO7/GPIO27
KSO8/GPIO28 SPI Device Interface PWRSHARE_EN_EC#
KSO9 48 119
o
1 2 EC_ESB_CLK 49 KSO9/GPIO29 MISO/GPIO5B 120 CDR_BTN# PWRSHARE_EN_EC# <32>
KSO10 CDR_BTN# <41>
RE93 4.7K_0402_5% KSO11 50 KSO10/GPIO2A MOSI/GPIO5C 126 CDRA_LED RED_R
EC_ESB_DAT KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 3V_F347_ON +3VS_TOUCH
1 2 KSO12 51 128
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A 3V_F347_ON <37>
RE94 4.7K_0402_5%
KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73 PM_SLP_S0# TP_CLK 2 1
C
KSO16 81 KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 74 WAKE_PCH# PM_SLP_S0# <18>
4.7K_0402_5% RE100
82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89 PD_IRQ# WAKE_PCH# <18> TP_DATA 2 1
KSO17 CE40 EMI@
+3VALW KSO17/GPIO49 GPIO50 90 BATT_CHG_LED# PD_IRQ# <60> 2 1 100P_0402_50V8J
4.7K_0402_5% RE101 ACIN
BATT_CHG_LED#/GPIO52 91 CAPS_LED# BATT_CHG_LED# <37>
EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 PWR_LED# CAPS_LED# <38>
RE90 GPIO
+3VS 5 4 EC_SMB_CK1 <61,62> EC_SMB_CK1 EC_SMB_DA1 78 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 93 BATT_LOW_LED# PWR_LED# <38>
EC_SMB_DA1 <61,62> EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <37>
6 3 79 95 SYSON
7 2 EC_SMB_CK2 <18,41,42,46,60> EC_SMB_CK2 EC_SMB_DA2 80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 VR_ON_R IMVP_VR_ON SYSON <45,64>
8 1 EC_SMB_DA2 <18,41,42,46,60> EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 127 PCH_DPWROK IMVP_VR_ON <45,71>
L
DPWROK_EC/GPIO59 PCH_DPWROK <18> 1
2
SM Bus @
2.2K_0804_8P4R_5% RE72 CE42
PM_SLP_S3# 6 100 PCH_RSMRST# 10K_0402_5% 0.1U_0402_10V7K
2 1 PCH_PWROK <18,37,45> PM_SLP_S3# PM_SLP_S5# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 PCH_RSMRST# <18> 2
<18,37> PM_SLP_S5# EC_SMI#_R 15 GPIO07 GPXIOA04 102 VCIN1_PH
RE75 10K_0402_5%
1
2 1 EN_INVPWR PS_ID 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 VCOUT1_PH VCIN1_PH <61>
L
103
<61> PS_ID EC_ESB_CLK 17 GPIO0A VCOUT1_PROCHOT#/GPXIOA06 104 VCOUT0_PH#
RE80 10K_0402_5% ESD@
2 1 3V_F347_ON EC_ESB_DAT 18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 VCOUT0_PH# <63> LID_SW_IN# 1 2
BKOFF#
CLKREQ#_DGPU 19 GPIO0C BKOFF#/GPXIOA08 106 PBTN_OUT# BKOFF# <25>
RE83 10K_0402_5% GPIO GPO CE43 0.1U_0402_10V7K
<17,41> CLKREQ#_DGPU 25 AC_PRESENT/GPIO0D GPXIOA09 107 2 1 PBTN_OUT# <6,18>
ESD@
<38> TP_LED_EN CPU_FAN_FB 28 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 108 CALDERA_ON RE74 43_0402_1% PCH_PWR_EN <45,66> PCH_PWROK 1 2
B FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 CALDERA_ON <41> B
<42> CPU_FAN_FB GPU_FAN_FB
E
29 CE44 0.1U_0402_10V7K
<42> GPU_FAN_FB EC_TX 30 FANFB1/GPIO15 ESD@
<28> EC_TX EC_RX EC_TX/GPIO16 ACIN_R RE107 1 SYS_PWROK
31 110 @ 2 0_0402_5% ACIN 1 2
1 2 EC_SMI#_R <28> EC_RX PCH_PWROK 32 EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 112 EC_ON ACIN <18,37,46,61,62>
@ CE46 0.1U_0402_10V7K
<17> EC_SMI# <18,71> PCH_PWROK 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <63>
RE108 0_0402_5% ON/OFFBTN#
1 2 <20,60> PD_PWR_EN 36 SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 115 LID_SW_IN# ON/OFFBTN# <38>
<58> TBT_RESET_N_EC <38> NumLock LED_A# NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04 LID_SW_IN# <37,38,42>
RE109 0_0402_5% 116 SUSP# Place CE30,CE31,CE32,CE33 close to UE1
SUSP#/GPXIOD05 117 USB_PWR_EN# SUSP# <45,58,64,74>
D
GPXIOD06 118 PECI_KB9012 1 2 USB_PWR_EN# <32,34>
122 PECI/GPXIOD07 RE76 43_0402_1%
H_PECI <9,16> RE76 follow TD-Team, 43ohm.
<66> +1VALWP_PGOOD 123 PBTN_OUT#/GPIO5D 124 +V18R
Reserve for ESD <9,45> H_VCCST_PWRGD PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VALW
PM_SLP_S3#
AGND
2 1
GND
GND
GND
GND
GND
r
UE6
CE41 ESD@ EC_ESB_CLK 1 13
0.1U_0402_10V7K KB9022QD_LQFP128_14X14 ESB_CLK TEST_EN#
11
24
35
94
113
69
DEPOP#_EC 2 14 TS_EN
PM_SLP_S5# <32> DEPOP#_EC GPIO00 GPIO08/CAS_DAT TS_EN <25>
2 1 LE2
o
ECAGND 2 1 RST# 3 15
RST# GPIO09 CALDERA_ PWRGD <41>
CE45 ESD@ FBMA-L11-160808-800LMT_0603
0.1U_0402_10V7K EC_ESB_DAT 4 16
ESB_DAT GPIO0A CALDERA_RST# <41>
Please close to EC 20mil +3VALW 5 17
<37,41> CALDERA_PRSNT# KP_DET# <39>
3/12 modify
GPIO01 GPIO0B
F
47K_0402_5%
6 18
<32> EAPD# GPIO02 GPIO0C/PWM0 GPU_ALERT# <46>
1
7 19
RE91
<32> CTL1 GPIO03 GPIO0D/PWM1 DGPU_PWROK <20>

8 20 AOAC_WLAN
H_PROCHOT# +3VS <32> CTL2 GPIO04 GPIO0E/PWM2 AOAC_WLAN <28>
<9,61,62> H_PROCHOT#
2
9 21 NV only
<46> EC_AC_BAT# GPIO05 GPIO0F/PWM3 GPU_OVERT# <46>
RST#
1
RE78 RE22 DBC_EN 10 22

<25> DBC_EN GPIO06 GPIO10/ESB_RUN# AMD#_NV <37>
0.1U_0402_16V7K~D
1 @ 2 1 @ 2 RE84
<71> VR_HOT# 11 23
0_0402_5% 0_0402_5% 10K_0402_5% 2 <37> PCIE_GEN3#_GEN2 GPIO07/CAS_CLK GPIO11/BaseAddOpt
W=60mils
CE55
12 24
GND
A +3VALW A
2
GND VCC
1
0.1U_0402_16V4Z
QE2 2 1 2 VCOUT1_PH 1
ME_EN 1
CE56
2N7002W-T/R7_SOT323-3 G KC3810_QFN24_4X4
25
2
S RE85 @
3
1 53.6K_0402_5% RE82 @
CE51 100K_0402_5% RE81 2
0.033U_0402_25V 1K_0402_5%
1
2
2

EC ENE-KB9012
5 4 3 2 1

5 4 3 2 1
D D
ia l
n t
C
id e C
n f
Screw Hole
C o
H2
H_3P5X4P1
@
H4
H_2P8
@
H6
H_2P8
@
H5
H_2P8
@
H8
H_2P8
@
L L H15
H16
H_3P8
H17
H_3P8
H18
H_3P8
H19
H_3P8
H20
H_3P8
H21
H_3P8
H24
H_3P2
1
H_3P5 @ @ @ @ @ @ @
1
1
B B
E
H9 H10 H11 H12 H13 H14 H22 H23
H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_3P8 H_3P8
@ @ @ @ @ @ @ @
1
1
H25
H_2P0N
H26
H_2P0X2P3N
r
H27
H_2P3
@
D H30
H_2P3
@
FD1
@ FIDUCAL
FD2
@ FIDUCIAL
FD3
@ FIDUCAL
FD4
@ FIDUCIAL
1
o
@ @
1
1
1
H29
H_2P3
Auto screw hold TBT hold
F
@
1
A A

Screw Hole
5 4 3 2 1

A B C D E
+5VS and +3VS switch

+5VALW +5VS
SHORT DEFAULT
U17 J4
1 14 5VS 2 1
2 VIN1 VOUT1 13 2 1
VIN1 VOUT1
C256
10U_0603_6.3V6M
C257
10U_0603_6.3V6M
R182 0_0402_5% C2506 @ JUMP_43X79
1 @ 2 5VS_GATE 3 12 1 2
<43,58,64,74> SUSP# 1 1
+VCCST Load Switch

ON1 CT1 220P_0402_50V8J
4 11
R174 10K_0402_5% VBIAS GND C2507 @
1 1
1 2 3VS_GATE 5 10 1 2 2 2
10mil ON2 CT2 470P_0402_50V7K
1 6 9 3VS
C258 +3VALW 7 VIN2 VOUT2 8
0.1U_0402_16V7K
VIN2 VOUT2
15 +3VS +1VALW +VCCST
2 GPAD
AOZ1331_SON14_2X3 J5 U19
l
20mohm/6A per channel 2
2 1
1 1
2 VIN1 R5
VIN2
C260
10U_0603_6.3V6M
C261
10U_0603_6.3V6M
@ JUMP_43X79 0_0603_5%
+3VALW +5VALW 1 1 +5VALW 7 6 1 @ 2
VIN thermal VOUT
ia
SHORT DEFAULT 3
VBIAS
1
1U_0402_6.3V
0.1U_0402_10V
@ 1 C6
1
2 2 4 5
ON GND 2 0.1U_0402_10V7K
C4
@ C5
C262
10U_0603_6.3V6M
C263
10U_0603_6.3V6M
C264
10U_0603_6.3V6M
C265
10U_0603_6.3V6M
t
2
2 TPS22961DNYR_WSON8
1 1 1 1
4.4mohm/6A
TR=12.5us@Vin=1.05V
2 2 2 2
n
<43,64> SYSON
Main source

TI SA00007XR00 (S IC TPS22961DNYR WSON 8P LOAD SWITCH)
e
2nd source AOS SA00008A800 (S IC AOZ1334DI-01 DFN 8P SINGLE LOAD SW)

3rd source EMC SA00008R600 (S IC EM5201V DFN3X3 8P LOAD SWITCH)
4st source APEC SA00006V300 (S IC APE8939GN3 DFN 8P LOAD SWITCH)
id
+3VALW
2 2
f
+3VALW_PCH switch
C269
10U_0603_6.3V6M
C270
10U_0603_6.3V6M
1 1
+3VALW +3V_PCH
+VCCSTG source +VCCSTG
n
2 2
+5VALW
SHORT DEFAULT
U18 J6
1 14 +3VALW_PCH 2 1
VIN1 VOUT1 2 1
1
2 13 +1VALW
o
VIN1 VOUT1
C266
10U_0603_6.3V6M
C267
10U_0603_6.3V6M
RE62 @ JUMP_43X79 R6
PCH_PWR_EN 2 @ 1 +3VALW_PCH_GATE 3 12 U20 @ 0_0603_5%
<43,66> PCH_PWR_EN ON1 CT1 1 1
1
0_0402_5% 4 11 2 VIN1
2
VBIAS GND @ VIN2
5 10 2 2 +5VALW 7 6 1 2
10mil
C
ON2 CT2 VIN thermal VOUT @ C9 0.1U_0402_10V7K
6 9 3
VIN2 VOUT2 VBIAS
1
C268 7 8 1
VIN2 VOUT2
1
1U_0402_6.3V
0.1U_0402_10V7K
@ C8
0.01U_0402_16V 4 5
ON GND
C7
15
2
GPAD +VCCSTG
2
AOZ1331_SON14_2X3 2 TPS22961DNYR_WSON8
20mohm/6A per channel 4.4mohm/6A
L
TR=12.5us@Vin=1.05V 1
C10
2 0.1U_0402_10V7K
<43,45,58,64,74> SUSP#
L
TI SA00007XR00 (S IC TPS22961DNYR WSON 8P LOAD SWITCH)

Main source
2nd source

AOS SA00008A800 (S IC AOZ1334DI-01 DFN 8P SINGLE LOAD SW)
3 3
3rd source EMC SA00008R600 (S IC EM5201V DFN3X3 8P LOAD SWITCH)
E
4st source APEC SA00006V300 (S IC APE8939GN3 DFN 8P LOAD SWITCH)
4/14 add for power down sequence.
D
IMVP_VR_ON <43,71>
For meet tPLT17 & tCPU28 power down sequence.

6
tPLT17 : 1us (Max) @

tCPU28 : 1us (Max)
Q7A
DMN65D8LDW-7_SOT363-6 +1.2V_VCCPLL_OC
r
For meet tPLT15 power down sequence(Un-Stuf f) 2
tPLT15 : 1us (Max)
1
o
+3VALW +1.2V_DDR +1.2V_VCCPLL_OC
+3VALW
UZ21
1
@ +1.2V_VCCPLL_OC
1
R307 @ 1 8
H_VCCST_PWRGD <9,43> SYSON <43,64> 2 VIN VOUT 7
F
100K_0402_1% R325
VIN VOUT
100K_0402_1% 1
3
@ <43,45,58,64,74> SUSP# R4 1 @ 2 0_0402_5% 3 6 C3 1 2

2
Q9B EN CT @ C11
2
DMN65D8LDW-7_SOT363-6 4 5 2200P_0402_50V 0.1U_0402_10V7K

PM_SLP_S3_H PM_SLP_S4_H +5VALW VBIAS GND 2
5 @ 5 9
Q7B GND
6
DMN65D8LDW-7_SOT363-6 @ APE8937GN2_DFN8_2X2
4
Q9A
6
2
DMN65D8LDW-7_SOT363-6 22mohm/4A
<18,43,65> PM_SLP_S4# TR=520us@Vin=0.8V
PM_SLP_S3# 2 @
1
<18,37,43> PM_SLP_S3# Q8A

4 4
DMN65D8LDW-7_SOT363-6 SUSP#
1
5 @
Q8B
4

DC/DC Interface
A B C D E

5 4 3 2 1
+3.3V_GFX_AON
GC6_EVENT#_D 1 2
RV50 10K_0402_5%
GC6_EVENT#_D 2 1 GC6_EVENT#
GC6_EVENT# <20> 1 2
OVERT#
DV9 RV527 10K_0402_5%
GPIO9_THERMAL_ALERT# 1 2
SDM10U45-7_SOD523-2
RV526 10K_0402_5%
DGPU_HOLD_RST# 2 1
@
RV530 10K_0402_5%~D
GPU_PEX_RST_HOLD# 1 2
BH21 Part 9 of 12 RV63 10K_0402_5%
<7> PEG_HTX_C_GRX_P0 BG21 PEX_RX0 AT9 NVVDD PWM_VID
<7> PEG_HTX_C_GRX_N0 BG23 PEX_RX0_N GPIO0 AT7 GPU_GC6_FB_EN NVVDD PWM_VID <68>
<7> PEG_HTX_C_GRX_P1 BH23 PEX_RX1 GPIO1 AV1 GC6_EVENT#_D GPU_GC6_FB_EN <20> NVVDD PSI 1 2
<7> PEG_HTX_C_GRX_N1 BJ23 PEX_RX1_N GPIO2 AW4 GPIO3_OC_WARN#
RV35 10K_0402_1%
<7> PEG_HTX_C_GRX_P2 BJ24 PEX_RX2 GPIO3 AW1 3V3_MAIN_EN GPIO3_OC_WARN# <49> AC_BATT# 2 1
<7> PEG_HTX_C_GRX_N2 BH24 PEX_RX2_N GPIO4 AT4 3V3_MAIN_EN <49,68>
RV61 100K_0402_5%~D
<7> PEG_HTX_C_GRX_P3 BG24 PEX_RX3 GPIO5 AT1 NVVDD PSI VGA_SMB_CK2 1 2
D <7> PEG_HTX_C_GRX_N3 BG26 PEX_RX3_N GPIO6 AT10 NVVDD PSI <68> D
RV191 1.8K_0402_5%
<7> PEG_HTX_C_GRX_P4 PEX_RX4 GPIO7 VGA_SMB_DA2
BH26 AV7 OVERT# 1 2
<7> PEG_HTX_C_GRX_N4 BJ26 PEX_RX4_N OVERT AW7 GPIO9_THERMAL_ALERT#
RV192 1.8K_0402_5%
<7> PEG_HTX_C_GRX_P5 BJ27 PEX_RX5 GPIO9 AT6 MEM_VREF SYS_PEX_RST_MON# 1 2
<7> PEG_HTX_C_GRX_N5 BH27 PEX_RX5_N GPIO10 AV2 MEM_VREF <51,52,53,54>
RV64 @ 10K_0402_5%
<7> PEG_HTX_C_GRX_P6 BG27 PEX_RX6 GPIO11 AV4 AC_BATT# +3VS_VGA
GPIO
<7> PEG_HTX_C_GRX_N6 BG29 PEX_RX6_N GPIO12 AT5
<7> PEG_HTX_C_GRX_P7 BH29 PEX_RX7 GPIO13 AW5 GPU_GC6_FB_EN 1 2
<7> PEG_HTX_C_GRX_N7 PEX_RX7_N GPIO14 TMDS_HPD new Add for HDMI2.0
BJ29 AV6 RV37 10K_0402_5%
BJ30 PEX_RX8 GPIO15 AW2 SYS_PEX_RST_MON# TMDS_HPD <27> MEM_VREF 2 1
PEX_RX8_N GPIO16 1
BH30 AW6 RV38 100K_0402_5%~D
PEX_RX9 GPIO17 DGPU_PEX_RST#
l
BG30 AW3 0.1U_0402_10V @ CV54 1 2
BG32 PEX_RX9_N GPIO18 AT8 RV59 10K_0402_5%
BH32 PEX_RX10 GPIO19 AV5 2 @
BJ32 PEX_RX10_N GPIO20 AT3 MC74VHC1G09DFT2G_SC70-5
BJ33 PEX_RX11 GPIO21 AR9 @
PEX_RX11_N GPIO22 GPU_PEX_RST_HOLD#
5
BH33 AV3 UV19
ia
BG33 PEX_RX12 GPIO23 AT2 1
G VCC
BG35 PEX_RX12_N GPIO24 <18,37,43,61,62> ACIN B 4 AC_BATT#
BH35 PEX_RX13 AV9 2 Y
BJ35 PEX_RX13_N GPIO25 <43> EC_AC_BAT# A
BJ36 PEX_RX14
3
BH36 PEX_RX14_N
BG36 PEX_RX15
PEX_RX15_N
t
AY21
DACA_RED BA21 1 2
PEG_GTX_HRX_P0_C DACA_GREEN
DACs
CV57 1 2 0.22U_0402_10V6K BC21 AW21 RV601 0_0402_5%
<7> PEG_GTX_HRX_P0 1 2 PEG_GTX_HRX_N0_C BD21 PEX_TX0 DACA_BLUE
CV62 0.22U_0402_10V6K
<7> PEG_GTX_HRX_N0 1 2 PEG_GTX_HRX_P1_C BE22 PEX_TX0_N
CV59 0.22U_0402_10V6K
<7> PEG_GTX_HRX_P1 1 2 PEG_GTX_HRX_N1_C BE23 PEX_TX1 BA20
CV60 0.22U_0402_10V6K
<7> PEG_GTX_HRX_N1 1 2 PEG_GTX_HRX_P2_C BD23 PEX_TX1_N DACA_HSYNC AY18
CV58 0.22U_0402_10V6K
n
<7> PEG_GTX_HRX_P2 1 2 PEG_GTX_HRX_N2_C BC23 PEX_TX2 DACA_VSYNC +3VS_VGA
CV63 0.22U_0402_10V6K
<7> PEG_GTX_HRX_N2 1 2 PEG_GTX_HRX_P3_C BC24 PEX_TX2_N
CV64 0.22U_0402_10V6K
PCI EXPRESS
<7> PEG_GTX_HRX_P3 1 2 PEG_GTX_HRX_N3_C BD24 PEX_TX3 AW18 DAC_VDD
CV61 0.22U_0402_10V6K
<7> PEG_GTX_HRX_N3 1 2 PEG_GTX_HRX_P4_C BE26 PEX_TX3_N DACA_VDD AW20
CV67 0.22U_0402_10V6K
<7> PEG_GTX_HRX_P4 1 2 PEG_GTX_HRX_N4_C BE25 PEX_TX4 DACA_VREF AY20
CV71 0.22U_0402_10V6K
<7> PEG_GTX_HRX_N4 1 2 PEG_GTX_HRX_P5_C BD26 PEX_TX4_N DACA_RSET SYS_PEX_RST_MON#
CV69 0.22U_0402_10V6K
e
<7> PEG_GTX_HRX_P5 1 2 PEG_GTX_HRX_N5_C BC26 PEX_TX5
CV68 0.22U_0402_10V6K
<7> PEG_GTX_HRX_N5 PEG_GTX_HRX_P6_C PEX_TX5_N
Address:0x9Eh and 0x9Ch

CV65 1 2 0.22U_0402_10V6K BC27
<7> PEG_GTX_HRX_P6 PEG_GTX_HRX_N6_C PEX_TX6
5
CV70 1 2 0.22U_0402_10V6K BD27
<7> PEG_GTX_HRX_N6 1 2 PEG_GTX_HRX_P7_C BE28 PEX_TX6_N
CV72 0.22U_0402_10V6K QV13B
<7> PEG_GTX_HRX_P7 PEG_GTX_HRX_N7_C BE29 PEX_TX7 BD4 VGA_SMB_CK2
CV66 1 2 0.22U_0402_10V6K 1 2 4 3
<7> PEG_GTX_HRX_N7 BD29 PEX_TX7_N I2CA_SCL BD3 1 2 1.8K_0402_5% EC_SMB_CK2 <18,41,42,43,60>
RV510
PEX_TX8 I2CA_SDA
2
id
BC29 RV511 1.8K_0402_5% DMN66D0LDW-7_SOT363-6
BC30 PEX_TX8_N BB5 1 2 QV13A
BD30 PEX_TX9 I2CB_SCL BB4 1 2 1.8K_0402_5% VGA_SMB_DA2 1 6
RV512
BE31 PEX_TX9_N I2CB_SDA EC_SMB_DA2 <18,41,42,43,60>
RV513 1.8K_0402_5%
PEX_TX10 I2CC_SCL_R
I2C
BE32 BD2 DMN66D0LDW-7_SOT363-6
BD32 PEX_TX10_N I2CC_SCL BD1 I2CC_SDA_R
BC32 PEX_TX11 I2CC_SDA
C BC33 PEX_TX11_N BF3 VGA_SMB_CK2 C
PEX_TX12 I2CS_SCL VGA_SMB_DA2
f
BD33 BE3
BE34 PEX_TX12_N I2CS_SDA
+3.3V_GFX_AON BE35 PEX_TX13
<69> +1.35VS_VGA_PGOOD BD35 PEX_TX13_N
BC35 PEX_TX14 +3.3V_GFX_AON
SYS_PEX_RST_MON#
2
BC36 PEX_TX14_N GPU_PLLVDD

GPU_PLLVDD
2
RV56 BD36 PEX_TX15 Y39
n
10K_0402_5% RV62 PEX_TX15_N GPCPLL_AVDD0 AD11
10K_0402_5% BJ21 GPCPLL_AVDD1 AT11
12
PEX_WAKE_N LXS_PLLVDD
G
AW27 VID_PLLVDD
1.8K_0402_1%
QV12
1
CLK_REQ#
1
1 3 BD20 SP_PLLVDD
1.8K_0402_1%
<17> CLKREQ#_GPU <17> CLK_PEG_GPU PEX_REFCLK
RV547
RV548
BC20 AW28
D
<17> CLK_PEG_GPU# CLK_REQ# BB20 PEX_REFCLK_N VID_PLLVDD
o
2N7002K 1N SOT23-3 PEX_CLKREQ_N
CLK
1 2 PEX_TSTCLK_OUT BH38 BB2
@ XTALIN
PEX_TSTCLK_OUT# XTAL_OUT
2
RV54 200_0402_1% BG38 PEX_TSTCLK_OUT XTALIN BA1
PEX_TSTCLK_OUT_N XTALOUT
5
10K_0402_5%
DGPU_PEX_RST# 1 2 DGPU_PEX_RST#_R BE20 BB1 XTALOUT 1 2 RV51
@ QV89B
RV40 1 2 0_0402_5% PEX_TERMP BJ38 PEX_RST_N XTALOUTBUFF BB3 XTALSSIN 1 2 I2CC_SCL_R 4 3
PEX_TERMP XTALSSIN I2CC_SCL <49>
RV57 2.49K_0402_1% RV49
2
10K_0402_5% DMN66D0LDW-7_SOT363-6
C
QV89A
I2CC_SDA_R 1 6
I2CC_SDA <49>
N16x GB3B-256 DMN66D0LDW-7_SOT363-6
L
DV4
DAN202UT106_SC70-3
GPU_GC6_FB_EN 2
1
GPU_PGOOD 3 FBVDD_EN <69>
<67,68> GPU_PGOOD 1 2
1
RV52 10M_0402_5%
L
+3VALW RV125
0.1U_0402_10V7K
100K_0402_5%~D YV1 TXC@

1
3XTAL_OUT
CV212
1 2 XTALIN 1
2
RV58 10K_0402_5% 1 3
TXC@ GND GND TXC@
2@ CV498 CV499
B 22P_0402_50V8J 2 4 22P_0402_50V8J B
E
5
DGPU_HOLD_RST# 1
P
<20> DGPU_HOLD_RST# B 4 SYS_PEX_RST_MON#

PCH_PLTRST# 2 O 27MHZ 16PF +-30PPM 7M27070004F50Q5
<17,41> PCH_PLTRST# A
1
G
UV14 RV187
3
300ohms
TC7SH08FU_SSOP5~D 10K_0402_5%
(ESR=) Bead
2
D
150mA
LV15 YV1 CV74 CV73
VID_PLLVDD
1
+3.3V_GFX_AON 1 2
+1.05VS_VGA
10U_0603_6.3V6M
RV208
0.1U_0402_10V7K
0.1U_0402_10V7K
47U_0805_6.3V6M~D
CV397
CV80
CV76
0_0402_5%~D 2 1 1 PBY160808T-301Y-N
SYS_PEX_RST_MON#
1
CV398
@
1
10K_0402_5%
5
RV39
27MHZ 10P_0402_50V8J 10P_0402_50V8J
r
2
1 2 2 HAR@ HAR@ HAR@

GPIO9_THERMAL_ALERT# 4 3 SJ10000B300 SE071100J80 SE071100J80
GPU_ALERT# <43>
DV8
2
SYS_PEX_RST_MON# 2 DMN66D0LDW-7_SOT363-6
Under GPU
QV91B
1 DGPU_PEX_RST#
DGPU_PEX_RST# <27> SYS_PEX_RST_MON#
o
GPU_PEX_RST_HOLD#
For HDMI HPD
3
2
ZZZ ZZZ
BAT54A-7-F_SOT23-3 OVERT# 1 6
GPU_OVERT# <43>
QV91A
F
LV9 X7656331L29 X7656331L30
Xtal@ Xtal@
GPU_PLLVDD 1 2
+1.05VS_VGA X7656331L33 X7656331L34
22U_0805_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1 1 BLM18KG300TN1D_2P
CV109
CV108
1 1 1 1
30 ohms @100MHz (ESR=0.01)
CV396
CV394
CV149
CV147
2 2
2 2 2 2
A A

N15P-GX (1/5) PEG & DAC
Custom 0.1
5 4 3 2 1

5 4 3 2 1
Part 10 of 12
BC18
BD18 IFPA_TXC AW14
BH14 IFPA_TXC_N 3V3AUX_NC BE15 AJ7 Part 12 of 12 AK5
BG14 IFPA_TXD0 IFPB_AUX_SCL BF12 AJ2 MIOAD0 MIOA_CTL3 AJ1
BD15 IFPA_TXD0_N NC BF18 AJ6 MIOAD1 MIOA_HSYNC AK8
BC15 IFPA_TXD1 NC AK10 AJ5 MIOAD2 MIOA_VSYNC AM4
IFPA_TXD1_N NC trace width: 16mils MIOAD3 MIOA_DE
BF17 AM10 AK4
BE17 IFPA_TXD2 NC AN10
differential voltage sensing. AJ4 MIOAD4 AK1
BD17 IFPA_TXD2_N GPIO27 AR10 differential 50ohm signal routing. AK9 MIOAD5 MIOA_CLKOUT AK2
D BC17 IFPA_TXD3 GPIO26 AY14 AK3 MIOAD6 MIOA_CLKOUT_N AJ3 D
NC
IFPA_TXD3_N NC BC11 AM3 MIOAD7 MIOA_CLKIN
NC BF15 AK7 MIOAD8
BH18 IFPB_AUX_SDA_N BG5 +VGA_CORE AM2 MIOAD9
BG18 IFPB_TXC IFPA_AUX_SDA_N BJ5 AK6 MIOAD10
BJ15 IFPB_TXC_N IFPA_AUX_SCL MIOAD11 AR8
BJ14 IFPB_TXD4 AM8 MIOB_CTL3 AM7
2
BG15 IFPB_TXD4_N AM6 MIOBD0 MIOB_HSYNC AN7
BH15 IFPB_TXD5 RV532 AM9 MIOBD1 MIOB_VSYNC AR3
BH17 IFPB_TXD5_N 100_0402_1% AN9 MIOBD2 MIOB_DE
ia
BG17 IFPB_TXD6 AN5 MIOBD3 AN3
BJ17 IFPB_TXD6_N AN8 MIOBD4 MIOB_CLKOUT AN2
1
BJ18 IFPB_TXD7 AR7 MIOBD5 MIOB_CLKOUT_N AM5
IFPB_TXD7_N VCCSENSE_VGA MIOBD6 MIOB_CLKIN
t
AY23 AN4
NVVDD_SENSE VCCSENSE_VGA <68> AN1 MIOBD7
BC14 AR6 MIOBD8
<27> TMDS_TX2P BD14 IFPC_L0 AN6 MIOBD9
n
<27> TMDS_TX2N IFPC_L0_N VSSSENSE_VGA MIOBD10
BF14 AW23 AR2
<27> TMDS_TX1P IFPC_L1 GND_SENSE VSSSENSE_VGA <68> MIOBD11
BE14
<27> TMDS_TX1N IFPC_L1_N
BD12
e
<27> TMDS_TX0P BC12 IFPC_L2
<27> TMDS_TX0N IFPC_L2_N
BD11 2 1 AJ9
<27> TMDS_TXCP IFPC_L3 MIOACAL_PD_VDDQ
BE11 RV533 100_0402_1% AJ8
<27> TMDS_TXCN IFPC_L3_N MIOACAL_PU_GND
id
C TEST 10K_0402_5% AM1
C
BG12 BA23 1 2 MIOA_VREF

new Add for HDMI2.0 IFPD_L0 TESTMODE
BH12 RV67
IFPD_L0_N GPU_JTAG_TCK
f
BJ12 BJ20 PAD~D T100 @ AR5
BJ11 IFPD_L1 JTAG_TCK BG20 GPU_JTAG_TDI PAD~D T97 @ AR4 MIOBCAL_PD_VDDQ
BH11 IFPD_L1_N JTAG_TDI BH20 GPU_JTAG_TDO PAD~D T98 @ MIOBCAL_PU_GND
BG11 IFPD_L2 JTAG_TDO BF20 GPU_JTAG_TMS PAD~D T99 @ AR1
n
BG9 IFPD_L2_N JTAG_TMS BF21 GPU_JTAG_TRST# 1 2 MIOB_VREF
BH9 IFPD_L3 JTAG_TRST_N
IFPD_L3_N
LVDS/TMDS
RV69
o
10K_0402_5% N16x GB3B-256
BE8
BF8 IFPE_L0
BF6 IFPE_L0_N
BG6 IFPE_L1 SERIAL
C
BD6 IFPE_L1_N BA3 ROM_CS
BE6 IFPE_L2 ROM_CS_N BA2 ROM_SCLK
BD5 IFPE_L2_N ROM_SCLK BA5 ROM_SI ROM_SCLK <55> +3VS_VGA +3VS_VGA +3VS_VGA
IFPE_L3 ROM_SI ROM_SO ROM_SI <55>
0.1U_0402_16V4Z~D
BE5 BA4
10K_0402_5%
ROM_SO <55>
1
IFPE_L3_N ROM_SO
RV167
BF9 1
IFPF_L0
CV195
BE9
BJ9 IFPF_L0_N
B B
2
BJ8 IFPF_L1
GENERAL
L
BH8 IFPF_L1_N UV10 2
BG8 IFPF_L2 AW9 ROM_CS 1 8
BJ6 IFPF_L2_N BUFRST ROM_SO 1 2 ROM_SO_R 2 CS# VCC 7 RV169 33_0402_5%~D
BH6 IFPF_L3 RV168 33_0402_5%~D 3 SO HOLD# 6 ROM_SCLK_R 1 2 ROM_SCLK
E
IFPF_L3_N 4 WP# SCK 5 ROM_SI_R 1 2 ROM_SI
BB7 1 2 GND SI RV170 33_0402_5%~D
MULTI_STRAP_REF0_GND RV66 40.2K_0402_1% W25X20CLSNIG SOIC 8P
<27> TMDS_TRLCLK BG2
BF2 IFPC_AUX_SCL
<27> TMDS_CTRLDAT
D
IFPC_AUX_SDA_N BA6 STRAP0
STRAP0 STRAP0 <55>
AW8 STRAP1
STRAP1 STRAP1 <55>
W25X20CL 2M-Bit/256K-byte
BG4 BA7 STRAP2
BF4 IFPD_AUX STRAP2 BA8 STRAP2 <55>
STRAP3
STRAP3 <55>
r
IFPD_AUX_N STRAP3 BB6 STRAP4
STRAP4 <55>
SA00003GM30
STRAP4
BG3
IFPE_AUX_SCL
o
BH3
IFPE_AUX_SDA_N BF1
THERMDP BE1
BJ4 THERMDN
IFPF_AUX_SCL
F
BH4 AV8
IFPF_AUX_SDA_N GPIO8
A A
N16x GB3B-256 Security Classification Compal Secret Data

B 0.1
5 4 3 2 1

5 4 3 2 1
UV1E
FBA_D0 Part 5 of 12 FBA_CAS#_L

FBA_D1 V43 U47 FBA_CKE_L
V41 FBA_D0 FBA_CMD0 U48 FBA_CAS#_L <51>
FBA_D2 FBA_D1 FBA_CMD1 FBA_RST#_L FBA_CKE_L <51>
FBA_D3 V44 U49 FBA_RAS#_L
UV1F
FBA_D2 FBA_CMD2 FBA_RST#_L <51>
FBA_D4 V42 V48 FBA_MA1_MA9_L
FBA_D3 FBA_CMD3 FBA_RAS#_L <51>
FBA_D5 U43 V49 FBA_MA0_MA10_L FBB_D0 FBB_CAS#_L
U44 FBA_D4 FBA_CMD4 V47 FBA_MA1_MA9_L <51> D30 C29
FBA_D6 FBA_MA12_RFU_L FBB_D1 Part 6 of 12 FBB_CKE_L
U41 FBA_D5 FBA_CMD5 AA49 FBA_MA0_MA10_L <51> G30 FBB_D0 FBB_CMD0 B29 FBB_CAS#_L <52>
UV1G
FBA_D7 FBA_D6 FBA_CMD6 FBA_ABI#_L FBA_MA12_RFU_L <51> FBB_D2 FBB_D1 FBB_CMD1 FBB_RST#_L FBB_CKE_L <52>
FBA_D8 U42 AA48 FBA_MA6_MA11_L FBB_D3 E30 A29 FBB_RAS#_L
FBA_D7 FBA_CMD7 FBA_ABI#_L <51> FBB_D2 FBB_CMD2 FBB_RST#_L <52>
FBA_D9 AA46 AC48 FBA_MA7_MA8_L FBB_D4 F30 A30 FBB_MA1_MA9_L FBC_D0 Part 7 of 12 FBC_CAS#_L
AC46 FBA_D8 FBA_CMD8 AC49 FBA_MA6_MA11_L <51> G29 FBB_D3 FBB_CMD3 B30 FBB_RAS#_L <52> A8 B3
FBA_D10 FBA_D9 FBA_CMD9 FBA_WE#_L FBA_MA7_MA8_L <51> FBB_D5 FBB_D4 FBB_CMD4 FBB_MA0_MA10_L FBB_MA1_MA9_L <52> FBC_D1 FBC_D0 FBC_CMD0 FBC_CKE_L FBC_CAS#_L <53>
AA45 AC47 F29 B32 D8 A4 Part 8 of 12
FBA_D11 FBA_D10 FBA_CMD10 FBA_MA5_BA1_L FBA_WE#_L <51> FBB_D6 FBB_D5 FBB_CMD5 FBB_MA12_RFU_L FBB_MA0_MA10_L <52> FBC_D2 FBC_D1 FBC_CMD1 FBC_RST#_L FBC_CKE_L <53> FBD_D0 FBD_CAS#_L
AA47 AD49 J29 A32 B8 B4 AF7 AG3
FBA_D12 FBA_D11 FBA_CMD11 FBA_MA4_BA2_L FBA_MA5_BA1_L <51> FBB_D7 FBB_D6 FBB_CMD6 FBB_ABI#_L FBB_MA12_RFU_L <52> FBC_D3 FBC_D2 FBC_CMD2 FBC_RAS#_L FBC_RST#_L <53> FBD_D1 FBD_D0 FBD_CMD0 FBD_CKE_L FBD_CAS#_L <54>
FBA_D13 Y46 AD48 FBA_MA2_BA0_L FBB_D8 H29 C32 FBB_MA6_MA11_L FBC_D4 C8 A5 FBC_MA1_MA9_L FBD_D2 AF9 AG2 FBD_RST#_L
Y49 FBA_D12 FBA_CMD12 AD47 FBA_MA4_BA2_L <51> C33 FBB_D7 FBB_CMD7 A33 FBB_ABI#_L <52> C5 FBC_D3 FBC_CMD3 A6 FBC_RAS#_L <53> AF6 FBD_D1 FBD_CMD1 AG1 FBD_CKE_L <54>
FBA_D14 FBA_D13 FBA_CMD13 FBA_MA3_BA3_L FBA_MA2_BA0_L <51> FBB_D9 FBB_D8 FBB_CMD8 FBB_MA7_MA8_L FBB_MA6_MA11_L <52> FBC_D5 FBC_D4 FBC_CMD4 FBC_MA0_MA10_L FBC_MA1_MA9_L <53> FBD_D3 FBD_D2 FBD_CMD2 FBD_RAS#_L FBD_RST#_L <54>
Y45 AF47 E33 B33 B5 B6 AF8 AF3
D FBA_D15 FBA_D14 FBA_CMD14 FBA_CS#_L FBA_MA3_BA3_L <51> FBB_D10 FBB_D9 FBB_CMD9 FBB_WE#_L FBB_MA7_MA8_L <52> FBC_D6 FBC_D5 FBC_CMD5 FBC_MA12_RFU_L FBC_MA0_MA10_L <53> FBD_D4 FBD_D3 FBD_CMD3 FBD_MA1_MA9_L FBD_RAS#_L <54> D
FBA_D16 Y48 AF48 FBA_CAS#_H FBB_D11 F33 B35 FBB_MA5_BA1_L FBC_D7 D5 B11 FBC_ABI#_L FBD_D5 AG7 AF1 FBD_MA0_MA10_L
FBA_D15 FBA_CMD15 FBA_CS#_L <51> FBB_D10 FBB_CMD10 FBB_WE#_L <52> FBC_D6 FBC_CMD6 FBC_MA12_RFU_L <53> FBD_D4 FBD_CMD4 FBD_MA1_MA9_L <54>
AJ46 BB49 D33 A35 C4 A11 AG6 AF2
FBA_D17 FBA_D16 FBA_CMD16 FBA_CKE_H FBA_CAS#_H <51> FBB_D12 FBB_D11 FBB_CMD11 FBB_MA4_BA2_L FBB_MA5_BA1_L <52> FBC_D8 FBC_D7 FBC_CMD7 FBC_MA6_MA11_L FBC_ABI#_L <53> FBD_D6 FBD_D5 FBD_CMD5 FBD_MA12_RFU_L FBD_MA0_MA10_L <54>
FBA_D18 AG47 BA48 FBA_RST#_H FBB_D13 C30 C35 FBB_MA2_BA0_L FBC_D9 B9 C12 FBC_MA7_MA8_L FBD_D7 AG9 AC1 FBD_ABI#_L
AG46 FBA_D17 FBA_CMD17 BA49 FBA_CKE_H <51> K33 FBB_D12 FBB_CMD12 A36 FBB_MA4_BA2_L <52> E11 FBC_D8 FBC_CMD8 A12 FBC_MA6_MA11_L <53> AG8 FBD_D6 FBD_CMD6 AC2 FBD_MA12_RFU_L <54>
FBA_D19 FBA_D18 FBA_CMD18 FBA_RAS#_H FBA_RST#_H <51> FBB_D14 FBB_D13 FBB_CMD13 FBB_MA3_BA3_L FBB_MA2_BA0_L <52> FBC_D10 FBC_D9 FBC_CMD9 FBC_WE#_L FBC_MA7_MA8_L <53> FBD_D8 FBD_D7 FBD_CMD7 FBD_MA6_MA11_L FBD_ABI#_L <54>
FBA_D20 AG45 AW49 FBA_MA1_MA9_H FBB_D15 E32 B36 FBB_CS#_L FBC_D11 D9 B12 FBC_MA5_BA1_L FBD_D9 AC5 AA2 FBD_MA7_MA8_L
FBA_D19 FBA_CMD19 FBA_RAS#_H <51> FBB_D14 FBB_CMD14 FBB_MA3_BA3_L <52> FBC_D10 FBC_CMD10 FBC_WE#_L <53> FBD_D8 FBD_CMD8 FBD_MA6_MA11_L <54>
FBA_D21 AF44 AV48 FBA_MA0_MA10_H FBB_D16 D32 B38 FBB_CAS#_H FBC_D12 A9 C15 FBC_MA4_BA2_L FBD_D10 AA4 AA1 FBD_WE#_L
FBA_D20 FBA_CMD20 FBA_MA1_MA9_H <51> FBB_D15 FBB_CMD15 FBB_CS#_L <52> FBC_D11 FBC_CMD11 FBC_MA5_BA1_L <53> FBD_D9 FBD_CMD9 FBD_MA7_MA8_L <54>
AF45 AV49 H39 D49 H11 A15 AC4 AA3
FBA_D22 FBA_D21 FBA_CMD21 FBA_MA12_RFU_H FBA_MA0_MA10_H <51> FBB_D17 FBB_D16 FBB_CMD16 FBB_CKE_H FBB_CAS#_H <52> FBC_D13 FBC_D12 FBC_CMD12 FBC_MA2_BA0_L FBC_MA4_BA2_L <53> FBD_D11 FBD_D10 FBD_CMD10 FBD_MA5_BA1_L FBD_WE#_L <54>
AD46 AN48 G39 C48 F9 B15 AC3 Y1
FBA_D23 FBA_D22 FBA_CMD22 FBA_ABI#_H FBA_MA12_RFU_H <51> FBB_D18 FBB_D17 FBB_CMD17 FBB_RST#_H FBB_CKE_H <52> FBC_D14 FBC_D13 FBC_CMD13 FBC_MA3_BA3_L FBC_MA2_BA0_L <53> FBD_D12 FBD_D11 FBD_CMD11 FBD_MA4_BA2_L FBD_MA5_BA1_L <54>
FBA_D24 AD45 AN49 FBA_MA6_MA11_H FBB_D19 F39 B46 FBB_RAS#_H FBC_D15 J11 B17 FBC_CS#_L FBD_D13 AD4 Y2 FBD_MA2_BA0_L
FBA_D23 FBA_CMD23 FBA_ABI#_H <51> FBB_D18 FBB_CMD18 FBB_RST#_H <52> FBC_D14 FBC_CMD14 FBC_MA3_BA3_L <53> FBD_D12 FBD_CMD12 FBD_MA4_BA2_L <54>
FBA_D25 AD44 AM47 FBA_MA7_MA8_H FBB_D20 D41 A46 FBB_MA1_MA9_H FBC_D16 E8 A17 FBC_CAS#_H FBD_D14 AD2 Y3 FBD_MA3_BA3_L
FBA_D24 FBA_CMD24 FBA_MA6_MA11_H <51> FBB_D19 FBB_CMD19 FBB_RAS#_H <52> FBC_D15 FBC_CMD15 FBC_CS#_L <53> FBD_D13 FBD_CMD13 FBD_MA2_BA0_L <54>
FBA_D26 AD43 AM49 FBA_WE#_H FBB_D21 F38 A45 FBB_MA0_MA10_H FBC_D17 K17 C27 FBC_CKE_H FBD_D15 AD5 V3 FBD_CS#_L
AD42 FBA_D25 FBA_CMD25 AM48 FBA_MA7_MA8_H <51> G38 FBB_D20 FBB_CMD20 C44 FBB_MA1_MA9_H <52> G17 FBC_D16 FBC_CMD16 B27 FBC_CAS#_H <53> AD1 FBD_D14 FBD_CMD14 V2 FBD_MA3_BA3_L <54>
FBA_D27 FBA_D26 FBA_CMD26 FBA_MA5_BA1_H FBA_WE#_H <51> FBB_D22 FBB_D21 FBB_CMD21 FBB_MA12_RFU_H FBB_MA0_MA10_H <52> FBC_D18 FBC_D17 FBC_CMD17 FBC_RST#_H FBC_CKE_H <53> FBD_D16 FBD_D15 FBD_CMD15 FBD_CAS#_H FBD_CS#_L <54>
FBA_D28 AC42 AJ47 FBA_MA4_BA2_H FBB_D23 D38 A44 FBB_ABI#_H FBC_D19 J17 A27 FBC_RAS#_H FBD_D17 R4 C2 FBD_CKE_H
FBA_D27 FBA_CMD27 FBA_MA5_BA1_H <51> FBB_D22 FBB_CMD22 FBB_MA12_RFU_H <52> FBC_D18 FBC_CMD18 FBC_RST#_H <53> FBD_D16 FBD_CMD16 FBD_CAS#_H <54>
FBA_D29 AA44 AJ49 FBA_MA2_BA0_H FBB_D24 E38 B44 FBB_MA6_MA11_H FBC_D20 G15 C26 FBC_MA1_MA9_H FBD_D18 U3 D1 FBD_RST#_H
FBA_D28 FBA_CMD28 FBA_MA4_BA2_H <51> FBB_D23 FBB_CMD23 FBB_ABI#_H <52> FBC_D19 FBC_CMD19 FBC_RAS#_H <53> FBD_D17 FBD_CMD17 FBD_CKE_H <54>
FBA_D30 AA43 AJ48 FBA_MA3_BA3_H FBB_D25 F36 C42 FBB_MA7_MA8_H FBC_D21 K15 A26 FBC_MA0_MA10_H FBD_D19 U4 D2 FBD_RAS#_H
AA42 FBA_D29 FBA_CMD29 AG48 FBA_MA2_BA0_H <51> K35 FBB_D24 FBB_CMD24 B42 FBB_MA6_MA11_H <52> K14 FBC_D20 FBC_CMD20 B26 FBC_MA1_MA9_H <53> U5 FBD_D18 FBD_CMD18 E1 FBD_RST#_H <54>
FBA_D31 FBA_D30 FBA_CMD30 FBA_CS#_H FBA_MA3_BA3_H <51> FBB_D26 FBB_D25 FBB_CMD25 FBB_WE#_H FBB_MA7_MA8_H <52> FBC_D22 FBC_D21 FBC_CMD21 FBC_MA12_RFU_H FBC_MA0_MA10_H <53> FBD_D20 FBD_D19 FBD_CMD19 FBD_MA1_MA9_H FBD_RAS#_H <54>
AA40 AG49 E36 A42 H14 A23 V6 F2
FBA_D32 FBA_D31 FBA_CMD31 FBA_CS#_H <51> FBB_D27 FBB_D26 FBB_CMD26 FBB_MA5_BA1_H FBB_WE#_H <52> FBC_D23 FBC_D22 FBC_CMD22 FBC_ABI#_H FBC_MA12_RFU_H <53> FBD_D21 FBD_D20 FBD_CMD20 FBD_MA0_MA10_H FBD_MA1_MA9_H <54>
FBA_D33 AT48 AF49 FBB_D28 D36 A41 FBB_MA4_BA2_H FBC_D24 J14 B23 FBC_MA6_MA11_H FBD_D22 V5 F1 FBD_MA12_RFU_H
FBA_D32 FBA_CMD32 FBB_D27 FBB_CMD27 FBB_MA5_BA1_H <52> FBC_D23 FBC_CMD23 FBC_ABI#_H <53> FBD_D21 FBD_CMD21 FBD_MA0_MA10_H <54>
FBA_D34 AT46 AF46 FBB_D29 G35 B41 FBB_MA2_BA0_H FBC_D25 E14 B21 FBC_MA7_MA8_H FBD_D23 Y4 L2 FBD_ABI#_H
FBA_D33 FBA_CMD33 FBB_D28 FBB_CMD28 FBB_MA4_BA2_H <52> FBC_D24 FBC_CMD24 FBC_MA6_MA11_H <53> FBD_D22 FBD_CMD22 FBD_MA12_RFU_H <54>
INTERFACE A
FBA_D35 AT49 FBB_D30 F35 C39 FBB_MA3_BA3_H FBC_D26 F14 A21 FBC_WE#_H FBD_D24 Y5 L1 FBD_MA6_MA11_H
AT47 FBA_D34 D35 FBB_D29 FBB_CMD29 B39 FBB_MA2_BA0_H <52> A14 FBC_D25 FBC_CMD25 C21 FBC_MA7_MA8_H <53> Y6 FBD_D23 FBD_CMD23 M3 FBD_ABI#_H <54>
FBA_D36 FBA_D35 FBB_D31 FBB_D30 FBB_CMD30 FBB_CS#_H FBB_MA3_BA3_H <52> FBC_D27 FBC_D26 FBC_CMD26 FBC_MA5_BA1_H FBC_WE#_H <53> FBD_D25 FBD_D24 FBD_CMD24 FBD_MA7_MA8_H FBD_MA6_MA11_H <54>
AW47 E35 A39 B14 A20 Y7 M1
FBA_D37 FBA_D36 FBB_D32 FBB_D31 FBB_CMD31 FBB_CS#_H <52> FBC_D28 FBC_D27 FBC_CMD27 FBC_MA4_BA2_H FBC_MA5_BA1_H <53> FBD_D26 FBD_D25 FBD_CMD25 FBD_WE#_H FBD_MA7_MA8_H <54>
FBA_D38 AW48 Y47 FBB_D33 M44 A38 FBC_D29 E12 B20 FBC_MA2_BA0_H FBD_D27 Y8 M2 FBD_MA5_BA1_H
MEMORY
BA47 FBA_D37 FBA_CMD34 AR47 P42 FBB_D32 FBB_CMD32 C38 F12 FBC_D28 FBC_CMD28 C20 FBC_MA4_BA2_H <53> AC9 FBD_D26 FBD_CMD26 R3 FBD_WE#_H <54>
FBA_D39 FBA_D38 FBA_CMD35 FBB_D34 FBB_D33 FBB_CMD33 FBC_D30 FBC_D29 FBC_CMD29 FBC_MA3_BA3_H FBC_MA2_BA0_H <53> FBD_D28 FBD_D27 FBD_CMD27 FBD_MA4_BA2_H FBD_MA5_BA1_H <54>
INTERFACE B
AW46 M43 G12 C18 AC7 R1
FBA_D40 FBA_D39 FBB_D35 FBB_D34 FBC_D31 FBC_D30 FBC_CMD30 FBC_CS#_H FBC_MA3_BA3_H <53> FBD_D29 FBD_D28 FBD_CMD28 FBD_MA2_BA0_H FBD_MA4_BA2_H <54>
FBA_D41 AR46 FBB_D36 P43 FBC_D32 G14 B18 FBD_D30 AC6 R2 FBD_MA3_BA3_H
FBA_D40 FBB_D35 FBC_D31 FBC_CMD31 FBC_CS#_H <53> FBD_D29 FBD_CMD29 FBD_MA2_BA0_H <54>
l
AN45 R45 G26 D18 AC8 U2
FBA_D42 FBA_D41 FBB_D37 FBB_D36 FBC_D33 FBC_D32 FBC_CMD32 FBD_D31 FBD_D30 FBD_CMD30 FBD_CS#_H FBD_MA3_BA3_H <54>
FBA_D43 AR49 FBB_D38 R46 D29 FBC_D34 J26 A18 FBD_D32 AC10 U1
FBA_D42 FBB_D37 FBB_CMD34 FBC_D33 FBC_CMD33 FBD_D31 FBD_CMD31 FBD_CS#_H <54>
MEMORY
INTERFACE C
AR48 R43 C41 F26 H2 V1
FBA_D44 FBA_D43 FBB_D39 FBB_D38 FBB_CMD35 FBC_D35 FBC_D34 FBD_D33 FBD_D32 FBD_CMD32
FBA_D45 AT45 FBA_CLK0 FBB_D40 R44 FBC_D36 H26 FBD_D34 H4 V4
FBA_D44 FBB_D39 FBC_D35 FBD_D33 FBD_CMD33
INTERFACE D
FBA_D46 AR44 AF41 FBA_CLK0# FBB_D41 M47 FBC_D37 G27 FBD_D35 H1
FBA_D45 FBA_CLK0 FBA_CLK0 <51> FBB_D40 FBC_D36 FBD_D34
AN41 AF40 P44 F27 C9 H3
FBA_D47 FBA_D46 FBA_CLK0_N FBA_CLK1 FBA_CLK0# <51> FBB_D42 FBB_D41 FBC_D38 FBC_D37 FBC_CMD34 FBD_D36 FBD_D35
MEMORY
AN42 AJ44 M46 J27 C24 F5
FBA_D48 FBA_D47 FBA_CLK1 FBA_CLK1# FBA_CLK1 <51> FBB_D43 FBB_D42 FBC_D39 FBC_D38 FBC_CMD35 FBD_D37 FBD_D36
FBA_D49 AG40 AJ45 FBB_D44 M45 FBC_D40 H27 FBD_D38 E2 AD3
FBA_D48 FBA_CLK1_N FBA_CLK1# <51> FBB_D43 FBC_D39 FBD_D37 FBD_CMD34
MEMORY
AG43 P47 E23 E4 J3
ia
FBA_D50 FBA_D49 FBB_D45 FBB_D44 FBB_CLK0 FBC_D41 FBC_D40 FBD_D39 FBD_D38 FBD_CMD35
FBA_D51 AG41 FBB_D46 P49 E41 FBB_CLK0# FBC_D42 D21 FBD_D40 D3
AJ43 FBA_D50 P45 FBB_D45 FBB_CLK0 F41 FBB_CLK0 <52> D23 FBC_D41 J4 FBD_D39
FBA_D52 FBA_D51 FBA_WCK0 FBB_D47 FBB_D46 FBB_CLK0_N FBB_CLK1 FBB_CLK0# <52> FBC_D43 FBC_D42 FBD_D41 FBD_D40
FBA_D53 AJ40 V46 FBA_WCK0_N FBB_D48 P46 E42 FBB_CLK1# FBC_D44 C23 FBD_D42 L5
FBA_D52 FBA_WCK01 FBA_WCK0 <51> FBB_D47 FBB_CLK1 FBB_CLK1 <52> FBC_D43 FBD_D41
FBA_D54 AK40 V45 FBB_D49 F46 D42 FBC_D45 A24 FBC_CLK0 FBD_D43 J2
FBA_D53 FBA_WCK01_N FBA_WCK0_N <51> FBB_D48 FBB_CLK1_N FBB_CLK1# <52> FBC_D44 FBD_D42
FBA_D55 AK42 Y42 FBB_D50 E47 FBC_D46 B24 F15 FBC_CLK0# FBD_D44 J1
AK41 FBA_D54 FBA_WCKB01 Y41 D47 FBB_D49 E24 FBC_D45 FBC_CLK0 E15 FBC_CLK0 <53> J6 FBD_D43
FBA_D56 FBA_D55 FBA_WCKB01_N FBA_WCK1 FBB_D51 FBB_D50 FBC_D47 FBC_D46 FBC_CLK0_N FBC_CLK1 FBC_CLK0# <53> FBD_D45 FBD_D44 FBD_CLK0
AK45 AD41 D48 D24 J18 H5 V9
FBA_D57 FBA_D56 FBA_WCK23 FBA_WCK1_N FBA_WCK1 <51> FBB_D52 FBB_D51 FBB_WCK0 FBC_D48 FBC_D47 FBC_CLK1 FBC_CLK1# FBC_CLK1 <53> FBD_D46 FBD_D45 FBD_CLK0 FBD_CLK0# FBD_CLK0 <54>
FBA_D58 AK43 AD40 FBB_D53 F48 F32 FBB_WCK0_N FBC_D49 D15 K18 FBD_D47 L9 V10 FBD_CLK1
FBA_D57 FBA_WCK23_N FBA_WCK1_N <51> FBB_D52 FBB_WCK01 FBB_WCK0 <52> FBC_D48 FBC_CLK1_N FBC_CLK1# <53> FBD_D46 FBD_CLK0_N FBD_CLK0# <54>
FBA_D59 AK48 AC41 FBB_D54 H46 G32 FBC_D50 C17 FBD_D48 L8 R6 FBD_CLK1#
AK49 FBA_D58 FBA_WCKB23 AC40 H47 FBB_D53 FBB_WCK01_N H32 FBB_WCK0_N <52> D17 FBC_D49 U10 FBD_D47 FBD_CLK1 R5 FBD_CLK1 <54>
t
FBA_D60 FBA_D59 FBA_WCKB23_N FBA_WCK2 FBB_D55 FBB_D54 FBB_WCKB01 FBC_D51 FBC_D50 FBD_D49 FBD_D48 FBD_CLK1_N FBD_CLK1# <54>
AM45 AT44 H48 J32 E17 U7
FBA_D61 FBA_D60 FBA_WCK45 FBA_WCK2_N FBA_WCK2 <51> FBB_D56 FBB_D55 FBB_WCKB01_N FBB_WCK1 FBC_D52 FBC_D51 FBC_WCK0 FBD_D50 FBD_D49
AM44 AT43 L45 G36 F18 F8 U9
FBA_D62 FBA_D61 FBA_WCK45_N FBA_WCK2_N <51> FBB_D57 FBB_D56 FBB_WCK23 FBB_WCK1_N FBB_WCK1 <52> FBC_D53 FBC_D52 FBC_WCK01 FBC_WCK0_N FBC_WCK0 <53> FBD_D51 FBD_D50
FBA_D[0..63] FBA_D63 AK44 AR43 FBB_D58 L44 H36 FBC_D54 E18 G8 FBD_D52 R7 FBD_WCK0
AM43 FBA_D62 FBA_WCKB45 AR42 J46 FBB_D57 FBB_WCK23_N K36 FBB_WCK1_N <52> D20 FBC_D53 FBC_WCK01_N H9 FBC_WCK0_N <53> R10 FBD_D51 AF4
<51> FBA_D[0..63] FBA_D63 FBA_WCKB45_N FBA_WCK3 FBB_D59 FBB_D58 FBB_WCKB23 FBC_D55 FBC_D54 FBC_WCKB01 FBD_D53 FBD_D52 FBD_WCK01 FBD_WCK0_N FBD_WCK0 <54>
C AM42 H49 J36 E20 G9 P10 AF5 C
FBA_DBI0# FBA_WCK67 FBA_WCK3_N FBA_WCK3 <51> FBB_D60 FBB_D59 FBB_WCKB23_N FBB_WCK2 FBC_D56 FBC_D55 FBC_WCKB01_N FBC_WCK1 FBD_D54 FBD_D53 FBD_WCK01_N FBD_WCK0_N <54>
FBA_DBI1# U40 AM41 FBB_D61 L47 M42 FBB_WCK2_N FBC_D57 G20 H12 FBC_WCK1_N FBD_D55 P8 AD8
<51> FBA_DBI0# FBA_DQM0 FBA_WCK67_N FBA_WCK3_N <51> FBB_D60 FBB_WCK45 FBB_WCK2 <52> FBC_D56 FBC_WCK23 FBC_WCK1 <53> FBD_D54 FBD_WCKB01
AC45 AN47 J49 M41 H20 J12 P9 AD9
<51> FBA_DBI1# FBA_DBI2# FBA_DQM1 FBA_WCKB67 FBB_D62 FBB_D61 FBB_WCK45_N FBB_WCK2_N <52> FBC_D58 FBC_D57 FBC_WCK23_N FBC_WCK1_N <53> FBD_D56 FBD_D55 FBD_WCKB01_N FBD_WCK1
FBA_DBI3# AG44 AN46 FBB_D[0..63] FBB_D63 L48 L42 FBC_D59 F20 C11 FBD_D57 P5 Y9 FBD_WCK1_N
<51> FBA_DBI2# AA41 FBA_DQM2 FBA_WCKB67_N L49 FBB_D62 FBA_WCKB45 L43 H21 FBC_D58 FBC_WCKB23 D11 P6 FBD_D56 FBD_WCK23 Y10 FBD_WCK1 <54>
FBA_DBI4# FBB_WCK3 FBC_D60 FBC_WCK2 FBD_D58
n
<51> FBA_DBI3# FBA_DQM3 <52> FBB_D[0..63] FBB_D63 FBB_WCKB45_N FBC_D59 FBC_WCKB23_N FBD_D57 FBD_WCK23_N FBD_WCK1_N <54>
FBA_DBI5# AV45 FBB_DBI0# H45 FBB_WCK3_N FBC_D61 F23 D26 FBC_WCK2_N FBD_D59 P2 AA9
<51> FBA_DBI4# FBA_DQM4 FBB_WCK67 FBB_WCK3 <52> FBC_D60 FBC_WCK45 FBC_WCK2 <53> FBD_D58 FBD_WCKB23
FBA_DBI6# AR45 FBB_DBI1# E29 H44 FBC_D62 G23 E26 FBD_D60 P1 AA10 FBD_WCK2
<51> FBA_DBI5# FBA_DQM5 <52> FBB_DBI0# FBB_DQM0 FBB_WCK67_N FBB_WCK3_N <52> FBC_D61 FBC_WCK45_N FBC_WCK2_N <53> FBD_D59 FBD_WCKB23_N
AG42 G33 J45 FBC_D[0..63] H23 H24 M5 H6
<51> FBA_DBI6# FBA_DBI7# FBA_DQM6 <52> FBB_DBI1# FBB_DBI2# FBB_DQM1 FBB_WCKB67 FBC_D63 FBC_D62 FBC_WCKB45 FBD_D61 FBD_D60 FBD_WCK45 FBD_WCK2_N FBD_WCK2 <54>
AM46 H38 J44 K23 J24 M6 H7
<51> FBA_DBI7# FBA_DQM7 <52> FBB_DBI2# FBB_DBI3# FBB_DQM2 FBB_WCKB67_N <53> FBC_D[0..63] FBC_D63 FBC_WCKB45_N FBC_WCK3 FBD_D62 FBD_D61 FBD_WCK45_N FBD_WCK2_N <54>
FBA_EDC0 FBB_DBI4# C36 FBC_DBI0# J20 FBC_WCK3_N FBD_D[0..63] FBD_D63 M7 J8
<52> FBB_DBI3# FBB_DQM3 FBC_WCK67 FBC_WCK3 <53> FBD_D62 FBD_WCKB45
FBA_EDC1 U45 FBB_DBI5# P41 FBC_DBI1# E6 K20 P7 J7 FBD_WCK3
<51> FBA_EDC[7..0] FBA_DQS_WP0 <52> FBB_DBI4# FBB_DQM4 <53> FBC_DBI0# FBC_DQM0 FBC_WCK67_N FBC_WCK3_N <53> <54> FBD_D[0..63] FBD_D63 FBD_WCKB45_N
FBA_EDC2 Y43 FBB_DBI6# P48 FBC_DBI2# E9 J21 FBD_DBI0# M8 FBD_WCK3_N
AF42 FBA_DQS_WP1 <52> FBB_DBI5# F47 FBB_DQM5 <53> FBC_DBI1# H17 FBC_DQM1 FBC_WCKB67 K21 AG10 FBD_WCK67 M9 FBD_WCK3 <54>
FBA_EDC3 FBA_DQS_WP2 <52> FBB_DBI6# FBB_DBI7# FBB_DQM6 <53> FBC_DBI2# FBC_DBI3# FBC_DQM2 FBC_WCKB67_N <54> FBD_DBI0# FBD_DBI1# FBD_DQM0 FBD_WCK67_N FBD_WCK3_N <54>
e
FBA_EDC4 AC44 L46 FBC_DBI4# D12 FBD_DBI2# AA5 L3
FBA_DQS_WP3 <52> FBB_DBI7# FBB_DQM7 <53> FBC_DBI3# FBC_DQM3 <54> FBD_DBI1# FBD_DQM1 FBD_WCKB67
FBA_EDC5 AV47 FBB_EDC0 FBC_DBI5# K27 FBD_DBI3# U6 L4
FBA_DQS_WP4 +3VS_VGA <53> FBC_DBI4# FBC_DQM4 <54> FBD_DBI2# FBD_DQM2 FBD_WCKB67_N
Under GPU
FBA_EDC6 AN43 FBB_EDC1 J30 FBC_DBI6# E21 FBD_DBI4# AA8
AJ42 FBA_DQS_WP5 H33 FBB_DQS_WP0 <53> FBC_DBI5# F17 FBC_DQM5 <54> FBD_DBI3# E3 FBD_DQM3
FBA_EDC7 FBA_DQS_WP6 LV14 FBB_EDC2 FBB_DQS_WP1 <53> FBC_DBI6# FBC_DBI7# FBC_DQM6 <54> FBD_DBI4# FBD_DBI5# FBD_DQM4
AK47 D39 J23 J5
FBA_DQS_WP7 +FB_PLLAVDD <52> FBB_EDC[7..0] FBB_EDC3 FBB_DQS_WP2 <53> FBC_DBI7# FBC_DQM7 <54> FBD_DBI5# FBD_DBI6# FBD_DQM5
AJ39 1 2 FBB_EDC4 J35 FBC_EDC0 FBD_DBI7# U8
FBA_PLL_AVDD FBB_DQS_WP3 <54> FBD_DBI6# FBD_DQM6
U46 R42 D6 M4
22U_0805_6.3V6M
0.1U_0402_16V7K
FBA_DQS_RN0 FBB_EDC5 FBB_DQS_WP4 FBC_EDC1 FBC_DQS_WP0 <54> FBD_DBI7# FBD_DQM7

Y44 M48 F11
CV148
1 1 PBY160808T-300Y-N_2P FBB_EDC6 FBC_EDC2 FBD_EDC0

AF43 FBA_DQS_RN1 F49 FBB_DQS_WP5 H15 FBC_DQS_WP1 AG5
CV364
FBA_DQS_RN2 FBB_EDC7 FBB_DQS_WP6 <53> FBC_EDC[7..0] FBC_EDC3 FBC_DQS_WP2 FBD_EDC1 FBD_DQS_WP0

AC43 J47 C14 AD7
id
FBA_DQS_RN3 FBB_DQS_WP7 +FB_PLLAVDD FBC_EDC4 FBC_DQS_WP3 <54> FBD_EDC[7..0] FBD_EDC2 FBD_DQS_WP1
AV46 BB48 L36 FBC_EDC5 E27 FBD_EDC3 V8
AN44 FBA_DQS_RN4 FB_CLAMP R39 2 2 H30 FBB_PLL_AVDD F24 FBC_DQS_WP4 AA7 FBD_DQS_WP2
FBA_DQS_RN5 FB_VREF FBB_DQS_RN0
100mA FBC_EDC6 FBC_DQS_WP5 FBD_EDC4 FBD_DQS_WP3
AJ41 J33 H18 F4
FBA_DQS_RN6 FBB_DQS_RN1 FBC_EDC7 FBC_DQS_WP6 FBD_EDC5 FBD_DQS_WP4
AK46 E39 G21 L7
0.1U_0402_16V7K
FBA_DQS_RN7 FBB_DQS_RN2 FBC_DQS_WP7 +FB_PLLAVDD FBD_EDC6 FBD_DQS_WP5
H35 1 L26 R8
FBB_DQS_RN3 FBC_PLL_AVDD FBD_EDC7 FBD_DQS_WP6
1
GPU_PLLVDD R41 C6 100mA P3
CV365
FBB_DQS_RN4 FBC_DQS_RN0 FBD_DQS_WP7 +FB_PLLAVDD
AC39 RV153 M49 G11 AA11
L21 FB_REFPLL_DLL_AVDD0 E49 FBB_DQS_RN5 J15 FBC_DQS_RN1 AG4 FBD_PLL_AVDD
100mA
0.1U_0402_10V7K
0.1U_0402_16V7K
10K_0402_5%
FB_REFPLL_DLL_AVDD1 J48 FBB_DQS_RN6 2 D14 FBC_DQS_RN2 AD6 FBD_DQS_RN0
0.1U_0402_10V7K
1 FBB_DQS_RN7 FBC_DQS_RN3 1 FBD_DQS_RN1

D27 V7
CV75
CV366
0.1U_0402_16V7K
1
2
G24 FBC_DQS_RN4 AA6 FBD_DQS_RN2

CV131
f
FBC_DQS_RN5 FBD_DQS_RN3 1
G18 F3
CV367
2
Under GPU FBC_DQS_RN6 2 FBD_DQS_RN4
N16x GB3B-256 F21 L6
2 FBC_DQS_RN7 R9 FBD_DQS_RN5
P4 FBD_DQS_RN6 2
FBD_DQS_RN7
+1.35VS_VGA
Under GPU
+1.35VS_VGA N16x GB3B-256
close to ball : L26 +1.35VS_VGA
Under GPU
close to ball : AA11
n
1
1
+1.35VS_VGA
1
1
RV114 RV113 N16x GB3B-256
RV110 RV109 10K_0402_5% 10K_0402_5% RV150 RV152
10K_0402_5% 10K_0402_5% N16x GB3B-256 10K_0402_5% 10K_0402_5%
1
FBB_CKE_L
2
FBA_CKE_L FBB_CKE_H RV147 RV148 FBD_CKE_L
2
2
B FBA_CKE_H 10K_0402_5% 10K_0402_5% FBD_CKE_H B
FBB_RST#_L
FBA_RST#_L FBB_RST#_H FBC_CKE_L FBD_RST#_L
2
o
FBA_RST#_H FBC_CKE_H FBD_RST#_H
FBC_RST#_L
1
FBC_RST#_H
1
1
RV112 RV111
RV107 RV108 10K_0402_5% 10K_0402_5% RV149 RV151
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
1
2
2
RV115 RV146
2
2
10K_0402_5% 10K_0402_5%
2
C
Packa g e Supported CMD Mapping
GB2B-64 H RST signal pull down resister

should be at the end of the
GB4B-128 H daisy-chain of this trace.
GB3-256 F
Mode H Mode H Mode F Mode F

Addr e s s 0..31 Addr e s s 32..63 Addr e s s 0..31 Addr e s s 32..63
L
CMD0 CS* CMD16 CS* CMD0 CAS* CMD16 CAS*
CMD1 A3_BA3 CMD17 A3_BA3 CMD1 CK1* CMD17 CK1*
CMD2 A2_BA0 CMD18 A2_BA0 CMD2 RST* CMD18 RST*
CMD3 A4_BA2 CMD19 A4_BA2 CMD3 RAS* CMD19 RAS*
CMD4 A5_BA1 CMD20 A5_BA1 CMD4 A1_A9 CMD20 A1_A9
CMD5 WE* CMD21 WE* CMD5 A0_A10 CMD21 A0_A10
L
CMD6 A7_A8 CMD22 A7_A8 CMD6 A12_RFU CMD22 A12_RFU
CMD7 A6_A11 CMD23 A6_A11 CMD7 ABI* CMD23 ABI*
CMD8 ABI* CMD24 ABI* CMD8 A6_A11 CMD24 A6_A11
A CMD9 A12_RFU CMD25 A12_RFU CMD9 A7_A8 CMD25 A7_A8 A
CMD10 A0_A10 CMD26 A0_A10 CMD10 WE* CMD26 WE*
E
CMD11 A1_A9 CMD27 A1_A9 CMD11 A5_BA1 CMD27 A5_BA1
CMD12 RAS* CMD28 RAS* CMD12 A4_BA2 CMD28 A4_BA2
CMD13 RST* CMD29 RST* CMD13 A2_BA0 CMD29 A2_BA0
CMD14 CK1* CMD30 CK1* CMD14 A3_BA3 CMD30 A3_BA3
CMD15 CAS* CMD31 CAS* CMD15 CS* CMD31 CS*
CMD32 NO USED CMD32 NO USED
CMD33 NO USED CMD33 NO USED Security Classification Compal Secret Data
D
CMD34 Debug0 CMD34 Debug0 Issued Date 2015/01/30 Deciphered Date 2016/12/31 Title
CMD35 Debug1 CMD35 Debug1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (5/5) POWER/ GND
5 4 3 2 1
o r
F
5 4 3 2 1
+3VS_VGA
For GDDR5 set t i ng. Near GP

U 3500mA Under GPU Near GPU
Part 11 of 12
+1.05VS_VGA +3VS_VGA
100P_0402_50V8J~D
1
+1.35VS_VGA AA39 AW33
FBVDDQ PEX_IOVDD
CV408
AC11 AY32
AD10 FBVDDQ PEX_IOVDD AY33
CV85
CV86
CV88
CV87
CV137
CV138
FBVDDQ PEX_IOVDD
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
4.7U_0603_6.3V6K
2
4.7U_0603_6.3V6K
AD39 AY35
CV81
CV93
CV89
CV90
CV96
CV95
CV99
CV94
CV98
CV139
CV140
CV117
CV118
CV114
CV119
CV111
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
AF11 FBVDDQ PEX_IOVDD BA33
10K_0402_1%
1.8K_0402_1%
FBVDDQ PEX_IOVDD
1
AF39 BA35
1.8K_0402_1%
AG39 FBVDDQ PEX_IOVDD BB33
RV551
RV552
RV242
1 1 1 1 1 1 2 2 2 2 2 2 AK39 FBVDDQ PEX_IOVDD 2 2 2 2 2 2 1 1 1 1 UV20
AM39 FBVDDQ AY24 4 16
AM40 FBVDDQ PEX_IOVDDQ AY26 VS VPU
2
AN40 FBVDDQ PEX_IOVDDQ AY27
B47 FBVDDQ PEX_IOVDDQ AY29 +1.05VS_VGA VIN1N 11 13
C45 FBVDDQ PEX_IOVDDQ AY30 VIN1P 12 IN-1 TC
+1.35VS_VGA C46 FBVDDQ PEX_IOVDDQ BA24 IN+1 10
FBVDDQ PEX_IOVDDQ PV
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
D D
C47 BA26 VIN2N 14
CV83
CV91
CV82
CV84
CV92
CV97
CV144
CV146
CV143
CV145
CV110
CV116
CV120
CV115
1 1 1 1 1 1 1 1 1 1 FBVDDQ PEX_IOVDDQ 1 1 1 1 IN-2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
D44 BA27 VIN2P 15 9
D45 FBVDDQ PEX_IOVDDQ BA29 IN+2 Critical
D46 FBVDDQ PEX_IOVDDQ BA30 1 8 RV554 1 @ 2 0_0402_5%
2 2 2 2 2 2 2 2 2 2 E44 FBVDDQ PEX_IOVDDQ BA32 2 2 2 2 2 IN-3 Warning GPIO3_OC_WARN# <46>
E45 FBVDDQ PEX_IOVDDQ BB24 IN+3 5 RV241 2 1 10K_0402_1%
F42 FBVDDQ PEX_IOVDDQ BB27 I2CC_SCL 6 A0
POWER
FBVDDQ PEX_IOVDDQ <46> I2CC_SCL I2CC_SDA SCL
F44 BB30 7 3
FBVDDQ PEX_IOVDDQ <46> I2CC_SDA SDA GND
F45
FBVDDQ +3.3V_GFX_AON
Under GPU(below 150mils)
G41
+1.35VS_VGA G42 FBVDDQ INA3221AIRGVR_VQFN16_4X4
FBVDDQ PEX_PLL_HVDD
210mA
H41 AW30
H42 FBVDDQ PEX_PLL_HVDD AW32
H43 FBVDDQ PEX_SVDD_3V3 AW26 PEX_PLLVDD
CV141
CV142
CV100
CV101
CV102
CV103
CV112
CV113
CV105
CV107
CV104
CV106
CV136
CV135
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
FBVDDQ PEX_PLLVDD
0.1U_0402_10V7K
4.7U_0603_6.3V6K
J38
CV122
CV123
CV121
1 1 1
1U_0402_6.3V
J39 FBVDDQ
FBVDDQ +3VS_VGA
Under GPU
J42 AW15
2 2 2 2 2 2 2 2 2 2 2 2 2 2 J43 FBVDDQ VDD33 AY15
K24 FBVDDQ VDD33 AJ10 2 2 2 CSSP_B+1 2 VIN1P
K26 FBVDDQ VDD33 AJ11 <68> CSSP_B+
RV540 10_0402_1%
1U_0402_10V
ia
FBVDDQ VDD33
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0805_25V6-K
K29 AK11
CV127
CV128
CV129
CV130
CV409
FBVDDQ VDD33 1 1 1 1 2
K30 AM11
K32 FBVDDQ VDD33 AN11
FBVDDQ VDD33 +1.05VS_VGA
Under GPU
L14 AR11
+1.35VS_VGA L15 FBVDDQ VDD33 2 2 2 2 1
L17 FBVDDQ AW17
L18 FBVDDQ 3V3_AON AY17 CSSN_B+1 2 VIN1N
1U_0402_10V
FBVDDQ 3V3_AON <68> CSSN_B+
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0805_25V6-K
L20 RV542 10_0402_1%
CV209
CV206
CV207
CV208
CV205
CV215
CV203
CV204
CV126
CV124
CV125
1 1 1 1 1 1 1 1 FBVDDQ 1 1 1
L23 BB15
FBVDDQ IFPAB_PLLVDD
Under GPU
L24 BE18
L27 FBVDDQ IFPAB_RSET +3.3V_GFX_AON
2 2 2 2 2 2 2 2 L29 FBVDDQ BB17 2 2 2 CSSP_VGA 1 2 VIN2P
FBVDDQ IFPAB_IOVDD <68> CSSP_VGA
L30 BA17 RV543 10_0402_1%
10U_0603_6.3V6M
L32 FBVDDQ IFPAB_IOVDD
CV410
2
1U_0402_10V
FBVDDQ
0.1U_0402_10V7K
4.7U_0805_25V6-K
L33 BA18
CV132
CV133
CV134
FBVDDQ IFPB_IOVDD 1 1 1
L35 BB18
L41 FBVDDQ IFPB_IOVDD
C P11 FBVDDQ BB12 1 C
FBVDDQ IFPCD_PLLVDD
e
P39 BB14 2 2 2
R11 FBVDDQ IFPCD_RSET CSSN_VGA 1 2 VIN2N
R40 FBVDDQ BA11 <68> CSSN_VGA
RV544 10_0402_1%
FBVDDQ IFPCD_IOVDD
FBVDD/FBVDDQ U11
FBVDDQ IFPCD_IOVDD
BA12
(+1.35VS_VGA) 22uF 10uF 4.7uF 1uF 0.1uF U39

FBVDDQ
2
V11 BB11
0_0201_5%
FBVDDQ NC
id
V39 BE12
V40 FBVDDQ NC +3VS_VGA
1 RV2
FBVDDQ
GPU 6 6 10(U) 14(U) 8(U) Y11
Y40 FBVDDQ IFPD_IOVDD
BA14
BA15
@
Under GPU LV16
FBVDDQ IFPD_IOVDD IFPC_PLL_VDD 1 2
Memory 2X8 4X8 10X8 IFPEF_PLVDD

BB9
BF11
PBY160808T-301Y-N
f
IFPEF_RSET
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
300ohms (ESR=0.12)
CV197
CV340
CV341
CV346
CV347
1 1 1 1 1
1U_0402_6.3V
AG11
PROBE_FBVDDQ
1
AF10 BC8
1K_0402_1%
PROBE_FB_GND IFPEF_IOVDD BD8
RH17
IFPEF_IOVDD 2 2 2 2 2
new Add for HDMI2.0
n
BC9
2
IFPF_IOVDD BD9
IFPF_IOVDD
22uF 10uF 4.7uF 1uF 0.1uF
FBx_PLL_DLL_AVDD
o
+1.35VS_VGA +1.05VS_VGA
Under GPU
R49
+GPU_PLLVDD(1.05) <69> FB_VDDQ_SENSE P40
FB_VDDQ_SENSE
FB_CAL_PD_VDDQ
FBx_PLL_AVDD 1 2 R48
FB_CAL_PU_GND
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1X4 RV771 2 40.2_0402_1% R47
CV196
CV316
CV336
CV337
CV342
CV344
CV343
CV345
1 1 1 1 1 1 1 1
+FB_PLLAVDD(3.3)
1U_0402_6.3V
1U_0402_6.3V
RV781 2 40.2_0402_1% FB_CALTERM_GND
RV79 60.4_0402_1%
C
2 2 2 2 2 2 2 2
B 22uF 10uF 4.7uF 1uF 0.1uF Place near balls B

N16x GB3B-256
PEX_IOVDD/Q(1.05) 4 4 2 4(U)
PEX_PLLVDD(1.05) 1 1 1(U) +3VS_VGA / +3.3V_GFX_AON

PEX_SVDD_3V3
+3.3V_GFX_AON 2 1
L L +3VS +3.3V_GFX_AON
1
10K_0402_5%
10K_0402_5%
22uF 10uF 4.7uF 1uF 0.1uF
RV538 RV541
3V3_Main
2
+3VS_VGA 1 1 2(U) +3.3V_GFX_AON
E
UV11
+3VS 60 mil
60 mil12 VIN1 VOUT1
14
3V3_AON
13
VIN1 VOUT1
+3.3V_GFX_AON 1 1 1(U) 3 12
CV368
1 2 220P_0402_50V8J
<20,68> DGPU_PWR_EN ON1 CT1
+5VS 4 11
VBIAS GND CV369
3V3_MAIN_EN 5 10 1 2 220P_0402_50V8J +3VS_VGA
<46,68> 3V3_MAIN_EN ON2 CT2
D
+3.3V_GFX_AON 6 9
7 VIN2 VOUT2 8
VIN2 VOUT2 60 mil
60 mil
1.05V 22uF 10uF 4.7uF 1uF 0.1uF GPAD
15
A AOZ1331_SON14_2X3 A
r
SP_PLLVDD
VID_PLLVDD 1 1 1X2
GPU_PLLAVDD
1 5
F o 4 3
Issued Date
2
2015/01/30
Compal Secret Data
Deciphered Date 2016/12/31 Title
Size
Custom
Date:
Document Number
LA-C912P
Wednesday, July 22, 2015
1
Sheet 49 of 78
Re v
0.1

5 4 3 2 1
UV1A
UV1B
+VGA_CORE +VGA_CORE
+VGA_CORE +VGA_CORE UV1D Part 1 of 12 BB32 Part 2 of 12 K2
Part 4 of 12 A2 AJ25 BB34 GND GND K4
UV1C BA39 BH48 A3 GND GND AJ27 BB35 GND GND K42
AA14 AH31 BA42 VDD VDD BH49 A47 GND GND AJ29 BB36 GND GND K45
AA16 VDD Part 3 of 12 VDD AJ14 BA43 VDD VDD BJ39 A48 GND GND AJ31 BB8 GND GND K46
AA18 VDD VDD AJ16 BA44 VDD VDD BJ41 AA15 GND GND AK14 BC2 GND GND K48
AA24 VDD VDD AJ22 BB37 VDD VDD BJ45 AA21 GND GND AK20 BC5 GND GND L13
AA26 VDD VDD AJ24 BB38 VDD VDD BJ46 AA23 GND GND AK22 BE10 GND GND L16
AA28 VDD VDD AJ26 BB39 VDD VDD BJ47 AA25 GND GND AK24 BE13 GND GND L19
D
AA30 VDD VDD AJ28 BB40 VDD VDD BJ48 AA27 GND GND AK26 BE16 GND GND L22 D
AA32 VDD VDD AJ30 BB41 VDD VDD P15 AA29 GND GND AK28 BE19 GND GND L25
AB15 VDD VDD AJ32 BB42 VDD VDD P17 AA31 GND GND AK30 BE2 GND GND L28
AB17 VDD VDD AK15 BB43 VDD VDD P19 AB11 GND GND AK32 BE21 GND GND L31
AB19 VDD VDD AK17 BB44 VDD VDD P21 AB14 GND GND AL11 BE24 GND GND L34
AB21 VDD VDD AK19 BB45 VDD VDD P23 AB16 GND GND AL15 BE27 GND GND L37
AB23 VDD VDD AK21 BB46 VDD VDD P25 AB18 GND GND AL17 BE30 GND GND N11
AB25 VDD VDD AK23 BB47 VDD VDD P27 AB2 GND GND AL19 BE33 GND GND N2
l
AB27 VDD VDD AK25 BC38 VDD VDD P29 AB20 GND GND AL2 BE36 GND GND N39
AB29 VDD VDD AK27 BC39 VDD VDD P31 AB22 GND GND AL21 BE37 GND GND N4
AB31 VDD VDD AK29 BC41 VDD VDD R14 AB24 GND GND AL23 BE4 GND GND N41
AC14 VDD VDD AK31 BC42 VDD VDD R16 AB26 GND GND AL25 BE7 GND GND N42
VDD VDD VDD VDD GND GND GND GND
ia
AC16 AL14 BC45 R18 AB28 AL27 BF10 N45
AC18 VDD VDD AL16 BC46 VDD VDD R20 AB30 GND GND AL29 BF13 GND GND N46
AC20 VDD VDD AL18 BD38 VDD VDD R22 AB32 GND GND AL31 BF16 GND GND N48
t
AC28 VDD VDD AL26 BD44 VDD VDD R30 AB42 GND GND AL42 BF24 GND GND P14
AC30 VDD VDD AL28 BD45 VDD VDD R32 AB45 GND GND AL45 BF25 GND GND P16
AC32 VDD VDD AL30 BD46 VDD VDD T15 AB46 GND GND AL46 BF26 GND GND P18
AD15 VDD VDD AL32 BD47 VDD VDD T17 AB48 GND GND AL48 BF27 GND GND P20
AD17 VDD VDD AM15 BD48 VDD VDD T19 AB5 GND GND AL5 BF28 GND GND P22
n
AD19 VDD VDD AM17 BD49 VDD VDD T21 AB8 GND GND AL8 BF29 GND GND P24
AD21 VDD VDD AM19 BE38 VDD VDD T23 AB9 GND GND AL9 BF30 GND GND P26
AD23 VDD VDD AM21 BE39 VDD VDD T25 AC15 GND GND AM14 BF31 GND GND P28
e
AD29 VDD VDD AM27 BE42 VDD VDD T31 AC21 GND GND AM20 BF34 GND GND R15
AD31 VDD VDD AM29 BE43 VDD VDD U14 AC23 GND GND AM22 BF35 GND GND R17
AE14 VDD VDD AM31 BE44 VDD VDD U16 AC25 GND GND AM24 BF36 GND GND R19
AE16 VDD VDD AM32 BE45 VDD VDD U18 AC27 GND GND AM26 BF37 GND GND R21
id
AE18 VDD VDD AN39 BE46 VDD VDD U20 AC29 GND GND AM28 BF5 GND GND R23
AE20 VDD VDD AP39 BE47 VDD VDD U22 AC31 GND GND AM30 BF7 GND GND R25
AE22 VDD VDD AR39 BE48 VDD VDD U24 AD14 GND GND AP11 BG1 GND GND R27
AE24 VDD VDD AR40 BE49 VDD VDD U26 AD16 GND GND AP2 BH1 GND GND R29
AE26 VDD VDD AR41 BF38 VDD VDD U28 AD18 GND GND AP4 BH10 GND GND R31
C AE28 VDD VDD AT39 BF39 VDD VDD U30 AD20 GND GND AP41 BH13 GND GND T11 C
f
AE30 VDD VDD AT40 BF40 VDD VDD U32 AD22 GND GND AP42 BH16 GND GND T14
AE32 VDD VDD AT41 BF41 VDD VDD V15 AD24 GND GND AP45 BH19 GND GND T16
AF15 VDD VDD AU39 BF42 VDD VDD V17 AD26 GND GND AP46 BH2 GND GND T18
n
AF21 VDD VDD AV41 BF45 VDD VDD V23 AD32 GND GND AP8 BH28 GND GND T22
AF23 VDD VDD AV42 BF46 VDD VDD V25 AE11 GND GND AP9 BH31 GND GND T24
AF25 VDD VDD AV43 BF47 VDD VDD V27 AE15 GND GND AT42 BH34 GND GND T26
AF27 VDD VDD AV44 BF48 VDD VDD V29 AE17 GND GND AU11 BH37 GND GND T28
AF29 VDD VDD AW35 BF49 VDD VDD V31 AE19 GND GND AU2 BH5 GND GND T30
o
AF31 VDD VDD AW36 BG39 VDD VDD W14 AE2 GND GND AU4 BH7 GND GND T32
AG14 VDD VDD AW37 BG41 VDD VDD W16 AE21 GND GND AU45 BJ2 GND GND T39
AG16 VDD VDD AW41 BG42 VDD VDD W18 AE23 GND GND AU46 BJ3 GND GND T4
AG18 VDD VDD AW42 BG44 VDD VDD W20 AE25 GND GND AU48 C1 GND GND T41
C
AG24 VDD VDD AW45 BG47 VDD VDD W26 AE31 GND GND AU9 D10 GND GND T46
AG26 VDD VDD AY36 BG48 VDD VDD W28 AE39 GND GND AW13 D13 GND GND T48
AG28 VDD VDD AY42 BG49 VDD VDD W30 AE4 GND GND AW16 D16 GND GND T5
AG30 VDD VDD AY45 BH39 VDD VDD W32 AE41 GND GND AW19 D19 GND GND T8
AG32 VDD VDD BA36 BH40 VDD VDD Y15 AE42 GND GND AW22 D22 GND GND T9
AH15 VDD VDD BA37 BH41 VDD VDD Y17 AE45 GND GND AW25 D25 GND GND U15
AH17 VDD VDD BA38 BH42 VDD VDD Y19 AE46 GND GND AW29 D28 GND GND U17
AH19 VDD VDD Y31 BH43 VDD VDD Y21 AE48 GND GND AW31 D31 GND GND U19
AH21 VDD VDD BH44 VDD VDD Y23 AE5 GND GND AW34 D34 GND GND U21
L
AH23 VDD BH45 VDD VDD Y25 AE8 GND GND AY2 D37 GND GND U23
AH25 VDD BH46 VDD VDD Y27 AE9 GND GND AY4 D4 GND GND U25
AH27 VDD BH47 VDD VDD Y29 AF14 GND GND AY46 D40 GND GND U27
AH29 VDD VDD VDD AF16 GND GND AY48 D43 GND GND U29
VDD AF18 GND GND AY5 D7 GND GND U31
GND GND GND GND
L
N16x GB3B-256 AF20 AY8 E10 V14
N16x GB3B-256 GND GND GND GND
AF22 B1 E13 V16
AF24 GND GND B10 E16 GND GND V18
GND GND GND GND
NVVDD 22uF 10uF 4.7uF 4.7uF 1uF 330uF 100uF
E
AF32 B2 E28 V26
B
AG15 GND GND B22 E31 GND GND V28 B
AG17 GND GND B25 E34 GND GND V30

AG19 GND GND B28 E37 GND GND V32
GND GND GND GND
+VGA_CORE 9 4 5 35(U) 20(U) AG21
AG23 GND GND
B31
B34
E40
E43 GND GND
W11
W15
AG25 GND GND B37 E46 GND GND W17
AG27 GND GND B40 E48 GND GND W19
D
GND GND GND GND
4 0 AG29
AG31 GND GND
B43
B45
E5
E7 GND GND
W2
W21
AH11 GND GND B48 F6 GND GND W23
AH14 GND GND B49 G2 GND GND W25
+VGA_CORE AH16 GND GND B7 G4 GND GND W27
GND GND GND GND
r
AH18 BA13 G45 W29
AH2 GND GND BA16 G46 GND GND W31
GND GND GND GND
CV159
CV325
CV323
CV319
CV317
CV324
CV318
CV322
CV320
CV321
AH20 BA19 G48 W39

4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 1 1 1 1 1 1 1 GND GND GND GND

AH22 BA22 G5 W4
AH24 GND GND BA25 H10 GND GND W41
o
2 2 2 2 2 2 2 2 2 2 AH28 GND GND BA31 H16 GND GND W45
AH32 GND GND BB10 H22 GND GND W48
+VGA_CORE AH4 GND GND BB16 H28 GND GND W8
F
AH42 GND GND BB22 H34 GND GND Y14
GND GND GND GND
CV326
CV335
CV332
CV329
CV328
CV334
CV327
CV333
CV331
CV330
AH45 BB23 H37 Y16

4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 1 1 1 1 1 1 1 GND GND GND GND

AH46 BB25 H40 Y18
AH48 GND GND BB26 H8 GND GND Y20
AH5 GND GND BB28 J13 GND GND Y22
2 2 2 2 2 2 2 2 2 2 AH8 GND GND BB29 J16 GND GND Y24
AH9 GND GND BB31 J19 GND GND Y26
AJ15 GND GND Y32 J22 GND GND Y28
AJ17 GND GND J25 GND GND Y30
AJ19 GND J28 GND GND J34
AJ21 GND AW24 J31 GND GND J37
+VGA_CORE AJ23 GND GND BB21 GND GND
GND GND
A A
N16x GB3B-256
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
470U_D2_2VM_R4.5M
0.1U_0402_10V7K
0.1U_0402_10V7K
CV411
CV412
CV413
CV414
CV415
CV379
CV380
CV157
CV158
CV152
CV151
CV150
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 1 1 1 1 1 2 2 2 2 2 N16x GB3B-256
CV1025
2 2 2 2 2 2 2 1 1 1 1 1
2

C 0.1
5 4 3 2 1

5 4 3 2 1
Memory Part i t i on A- L ower 32 bi st UV6

MF=0
UV7 MF=1
FBA_D[0..63] MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0
<48> FBA_D[0..63]
FBA_EDC[7..0] A4 FBA_D0 A4 FBA_D56
<48> FBA_EDC[7..0] FBA_EDC0 DQ24 DQ0 FBA_D1 FBA_EDC7 DQ24 DQ0 FBA_D57
C2 A2 C2 A2
FBA_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2 FBA_EDC6 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D58
FBA_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D3 FBA_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D59
FBA_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D4 FBA_EDC4 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D60
EDC3 EDC0 DQ28 DQ4 FBA_D5 BYTE0 EDC3 EDC0 DQ28 DQ4 FBA_D61 BYTE7
E2 E2
DQ29 DQ5 F4 FBA_D6 DQ29 DQ5 F4 FBA_D62
FBA_DBI0# D2 DQ30 DQ6 F2 FBA_D7 FBA_DBI7# D2 DQ30 DQ6 F2 FBA_D63
D <48> FBA_DBI0# FBA_DBI1# DBI0# DBI3# DQ31 DQ7 FBA_D8 <48> FBA_DBI7# FBA_DBI6# DBI0# DBI3# DQ31 DQ7 FBA_D48 D
D13 A11 D13 A11
<48> FBA_DBI1# FBA_DBI2# DBI1# DBI2# DQ16 DQ8 FBA_D9 <48> FBA_DBI6# FBA_DBI5# DBI1# DBI2# DQ16 DQ8 FBA_D49
P13 A13 P13 A13
<48> FBA_DBI2# FBA_DBI3# DBI2# DBI1# DQ17 DQ9 FBA_D10 <48> FBA_DBI5# FBA_DBI4# DBI2# DBI1# DQ17 DQ9 FBA_D50
P2 B11 P2 B11
<48> FBA_DBI3# DBI3# DBI0# DQ18 DQ10 FBA_D11 <48> FBA_DBI4# DBI3# DBI0# DQ18 DQ10 FBA_D51
B13 BYTE1 B13
FBA_CLK0 J12 DQ19 DQ11 E11 FBA_D12 FBA_CLK1 J12 DQ19 DQ11 E11 FBA_D52
<48> FBA_CLK0 FBA_CLK0# CK DQ20 DQ12 FBA_D13 <48> FBA_CLK1 FBA_CLK1# CK DQ20 DQ12 FBA_D53 BYTE6
J11 E13 J11 E13
<48> FBA_CLK0# FBA_CKE_L CK# DQ21 DQ13 FBA_D14 <48> FBA_CLK1# FBA_CKE_H CK# DQ21 DQ13 FBA_D54
J3 F11 J3 F11
<48> FBA_CKE_L CKE# DQ22 DQ14 FBA_D15 <48> FBA_CKE_H CKE# DQ22 DQ14 FBA_D55
F13 F13
DQ23 DQ15 U11 FBA_D16 DQ23 DQ15 U11 FBA_D40
FBA_MA2_BA0_L H11 DQ8 DQ16 U13 FBA_D17 FBA_MA4_BA2_H H11 DQ8 DQ16 U13 FBA_D41
<48> FBA_MA2_BA0_L FBA_MA5_BA1_L BA0/A2 BA2/A4 DQ9 DQ17 FBA_D18 <48> FBA_MA4_BA2_H FBA_MA3_BA3_H BA0/A2 BA2/A4 DQ9 DQ17 FBA_D42
K10 T11 K10 T11
l
K11 T13 BYTE2 K11 T13
H10 N11 H10 N11 BYTE5
<48> FBA_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 FBA_D21 <48> FBA_MA5_BA1_H BA3/A3 BA1/A5 DQ12 DQ20 FBA_D45
N13 N13
DQ13 DQ21 M11 FBA_D22 DQ13 DQ21 M11 FBA_D46
FBA_MA7_MA8_L K4 DQ14 DQ22 M13 FBA_D23 FBA_MA0_MA10_H K4 DQ14 DQ22 M13 FBA_D47
ia
<48> FBA_MA7_MA8_L FBA_MA1_MA9_L A8/A7 A10/A0 DQ15 DQ23 FBA_D24 <48> FBA_MA0_MA10_H FBA_MA6_MA11_H A8/A7 A10/A0 DQ15 DQ23 FBA_D32
H5 U4 H5 U4
H4 U2 H4 U2
K5 T4 K5 T4
<48> FBA_MA6_MA11_L FBA_MA12_RFU_L A11/A6 A9/A1 DQ2 DQ26 FBA_D27 <48> FBA_MA1_MA9_H FBA_MA12_RFU_H A11/A6 A9/A1 DQ2 DQ26 FBA_D35
J5 T2 BYTE3 J5 T2 BYTE4
<48> FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27 FBA_D28 <48> FBA_MA12_RFU_H A12/RFU/NC DQ3 DQ27 FBA_D36
N4 N4
A5 DQ4 DQ28 N2 FBA_D29 A5 DQ4 DQ28 N2 FBA_D37
t
U5 VPP/NC DQ5 DQ29 M4 FBA_D30 +1.35VS_VGA U5 VPP/NC DQ5 DQ29 M4 FBA_D38
2 RV116 1 VPP/NC DQ6 DQ30 M2 FBA_D31 2 RV117 1 VPP/NC DQ6 DQ30 M2 FBA_D39
1K_0402_1% DQ7 DQ31 1K_0402_1% DQ7 DQ31
J1 +1.35VS_VGA J1 +1.35VS_VGA
2G@ MF 2G@ MF
2 RV118 1 J10 2 RV119 1 J10
n
2 RV120 1 1K_0402_1% J13 SEN B1 2 RV121 1 1K_0402_1% J13 SEN B1
121_0402_1% 2G@ ZQ VDDQ D1 121_0402_1% 2G@ ZQ VDDQ D1
VDDQ F1 VDDQ F1
2G@ FBA_ABI#_L VDDQ 2G@ FBA_ABI#_H VDDQ
J4 M1 J4 M1
<48> FBA_ABI#_L FBA_RAS#_L ABI# VDDQ <48> FBA_ABI#_H FBA_CAS#_H ABI# VDDQ
G3 P1 G3 P1
e
<48> FBA_RAS#_L FBA_CS#_L RAS# CAS# VDDQ <48> FBA_CAS#_H FBA_WE#_H RAS# CAS# VDDQ
G12 T1 G12 T1
FBA_CLK0 <48> FBA_CS#_L FBA_CAS#_L CS# WE# VDDQ <48> FBA_WE#_H FBA_RAS#_H CS# WE# VDDQ
L3 G2 L3 G2
<48> FBA_CAS#_L FBA_WE#_L CAS# RAS# VDDQ <48> FBA_RAS#_H FBA_CS#_H CAS# RAS# VDDQ
L12 L2 L12 L2
<48> FBA_WE#_L WE# CS# VDDQ <48> FBA_CS#_H WE# CS# VDDQ
B3 B3
VDDQ VDDQ
1
C D3 D3 C
VDDQ VDDQ
id
RV123 F3 F3
80.6_0402_1% FBA_WCK0_N D5 VDDQ H3 FBA_WCK3_N D5 VDDQ H3
<48> FBA_WCK0_N FBA_WCK0 WCK01# WCK23# VDDQ FBA_CLK1 <48> FBA_WCK3_N FBA_WCK3 WCK01# WCK23# VDDQ
D4 K3 D4 K3
<48> FBA_WCK0 WCK01 WCK23 VDDQ <48> FBA_WCK3 WCK01 WCK23 VDDQ
M3 M3
2
FBA_CLK0# FBA_WCK1_N P5 VDDQ P3 FBA_WCK2_N P5 VDDQ P3

<48> FBA_WCK1_N FBA_WCK1 <48> FBA_WCK2_N FBA_WCK2
1
P4 WCK23# WCK01# VDDQ T3 P4 WCK23# WCK01# VDDQ T3
<48> FBA_WCK1 WCK23 WCK01 VDDQ <48> FBA_WCK2 WCK23 WCK01 VDDQ
2G@ E5 RV175 E5
f
VDDQ N5 80.6_0402_1% VDDQ N5
A10 VDDQ E10 A10 VDDQ E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
2
+FBA_VREFC J14 VREFD VDDQ B12 FBA_CLK1# +FBA_VREFC J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
VDDQ VDDQ
n
F12 2G@ F12
VDDQ H12 VDDQ H12
FBA_RST#_L J2 VDDQ K12 FBA_RST#_H J2 VDDQ K12
<48> FBA_RST#_L RESET# VDDQ <48> FBA_RST#_H RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
o
VDDQ G13 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
K1 VSS VDDQ B14 K1 VSS VDDQ B14
B5 VSS VDDQ D14 B5 VSS VDDQ D14
G5 VSS VDDQ F14 G5 VSS VDDQ F14
L5 VSS VDDQ M14 L5 VSS VDDQ M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
C
B10 VSS VDDQ T14 B10 VSS VDDQ T14
D10 VSS VDDQ D10 VSS VDDQ
G10 VSS G10 VSS
L10 VSS A1 L10 VSS A1
P10 VSS VSSQ C1 P10 VSS VSSQ C1
T10 VSS VSSQ E1 T10 VSS VSSQ E1
H14 VSS VSSQ N1 H14 VSS VSSQ N1
K14 VSS VSSQ R1 K14 VSS VSSQ R1
+1.35VS_VGA VSS VSSQ U1 +1.35VS_VGA VSS VSSQ U1
VSSQ VSSQ
L
H2 H2
G1 VSSQ K2 G1 VSSQ K2
L1 VDD VSSQ A3 L1 VDD VSSQ A3
B VDD VSSQ VDD VSSQ B
G4 C3 G4 C3
L4 VDD VSSQ E3 L4 VDD VSSQ E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
L
C10 VDD VSSQ U3 C10 VDD VSSQ U3
R10 VDD VSSQ C4 R10 VDD VSSQ C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4
G11 VDD VSSQ F5 G11 VDD VSSQ F5
+1.35VS_VGA L11 VDD VSSQ M5 L11 VDD VSSQ M5
P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
E
VDD VSSQ VDD VSSQ
1
L14 C11 L14 C11

RV189 VDD VSSQ R11 VDD VSSQ R11
549_0402_1% 2G@ VSSQ A12 VSSQ A12
VSSQ VSSQ
W=16mils
C12 C12
RV194 VSSQ VSSQ
E12 E12
2
1 2G@ 2 +FBA_VREFC VSSQ N12 VSSQ N12

VSSQ VSSQ
820P_0402_25V7
820P_0402_25V7
931_0402_1% R12 R12

1
VSSQ VSSQ
CV301
CV303
170-BALL U12 170-BALL U12
D
1 1 VSSQ VSSQ
RV196 H13 H13
1.33K_0402_1% SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ VSSQ
1
D
A14 A14
2 2 2 VSSQ C14 VSSQ C14
<46,52,53,54> MEM_VREF
2
G VSSQ E14 VSSQ E14

S QV23 VSSQ N14 VSSQ N14
r
3
VSSQ VSSQ
2G@ L2N7002WT1G 1N SC-70-3 2G@ one Close to UV8 VSSQ
R14
U14 VSSQ
R14
U14
one Close to UV9 VSSQ VSSQ
2G@ 2G@ X76@ X76@
o
H5GQ1H24BFR-T2C_BGA170 H5GQ1H24BFR-T2C_BGA170
F
A A
CV225
CV224
CV227
CV170
CV169
CV173
CV223
CV228
CV226
CV171
CV172
CV168
CV154
CV167
CV201
CV229
CV218
CV217
CV220
CV163
CV162
CV166
CV216
CV221
CV219
CV165
CV164
CV161
CV153
CV160
CV200
CV222
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@

Title
Issued Date 2015/01/30 Deciphered Date 2016/12/31
N15P_GDDR5_A Lower
5 4 3 2 1

5 4 3 2 1
Memory Part i t i on A- L ower 32 bi st UV8 MF=0 UV9 MF=1

MF=0 MF=1 MF=1 MF=0
FBB_D[0..63] MF=0 MF=1 MF=1 MF=0
<48> FBB_D[0..63] FBB_D56
A4
FBB_EDC[7..0] A4 FBB_D0 FBB_EDC7 C2 DQ24 DQ0 A2 FBB_D57
<48> FBB_EDC[7..0] FBB_EDC0 DQ24 DQ0 FBB_D1 FBB_EDC6 EDC0 EDC3 DQ25 DQ1 FBB_D58
C2 A2 C13 B4
FBB_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBB_D2 FBB_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBB_D59
FBB_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBB_D3 FBB_EDC4 R2 EDC2 EDC1 DQ27 DQ3 E4 FBB_D60
FBB_EDC3 EDC2 EDC1 DQ27 DQ3 FBB_D4 BYTE0 EDC3 EDC0 DQ28 DQ4 FBB_D61 BYTE7
R2 E4 E2
EDC3 EDC0 DQ28 DQ4 E2 FBB_D5 DQ29 DQ5 F4 FBB_D62
DQ29 DQ5 F4 FBB_D6 FBB_DBI7# D2 DQ30 DQ6 F2 FBB_D63
D FBB_DBI0# DQ30 DQ6 FBB_D7 <48> FBB_DBI7# FBB_DBI6# DBI0# DBI3# DQ31 DQ7 FBB_D48 D
D2 F2 D13 A11
<48> FBB_DBI0# FBB_DBI1# DBI0# DBI3# DQ31 DQ7 FBB_D8 <48> FBB_DBI6# FBB_DBI5# DBI1# DBI2# DQ16 DQ8 FBB_D49
D13 A11 P13 A13
<48> FBB_DBI1# FBB_DBI2# DBI1# DBI2# DQ16 DQ8 FBB_D9 <48> FBB_DBI5# FBB_DBI4# DBI2# DBI1# DQ17 DQ9 FBB_D50
P13 A13 P2 B11
<48> FBB_DBI2# FBB_DBI3# DBI2# DBI1# DQ17 DQ9 FBB_D10 <48> FBB_DBI4# DBI3# DBI0# DQ18 DQ10 FBB_D51
P2 B11 B13
FBB_CLK0 <48> FBB_DBI3# DBI3# DBI0# DQ18 DQ10 FBB_D11 FBB_CLK1 DQ19 DQ11 FBB_D52
B13 BYTE1 J12 E11 BYTE6
FBB_CLK0 DQ19 DQ11 FBB_D12 <48> FBB_CLK1 FBB_CLK1# CK DQ20 DQ12 FBB_D53
J12 E11 J11 E13
<48> FBB_CLK0 FBB_CLK0# CK DQ20 DQ12 FBB_D13 <48> FBB_CLK1# FBB_CKE_H CK# DQ21 DQ13 FBB_D54
J11 E13 J3 F11
<48> FBB_CLK0# FBB_CKE_L CK# DQ21 DQ13 FBB_D14 <48> FBB_CKE_H CKE# DQ22 DQ14 FBB_D55
1
J3 F11 F13
<48> FBB_CKE_L CKE# DQ22 DQ14 FBB_D15 DQ23 DQ15 FBB_D40
RV178 F13 U11
80.6_0402_1% DQ23 DQ15 U11 FBB_D16 FBB_MA4_BA2_H H11 DQ8 DQ16 U13 FBB_D41
FBB_MA2_BA0_L DQ8 DQ16 FBB_D17 <48> FBB_MA4_BA2_H FBB_MA3_BA3_H BA0/A2 BA2/A4 DQ9 DQ17 FBB_D42
H11 U13 K10 T11
l
<48> FBB_MA2_BA0_L FBB_MA5_BA1_L BA0/A2 BA2/A4 DQ9 DQ17 FBB_D18 <48> FBB_MA3_BA3_H FBB_MA2_BA0_H BA1/A5 BA3/A3 DQ10 DQ18 FBB_D43
K10 T11 K11 T13
<48> FBB_MA5_BA1_L <48> FBB_MA2_BA0_H
2
FBB_CLK0# FBB_MA4_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBB_D19 FBB_MA5_BA1_H H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBB_D44
<48> FBB_MA4_BA2_L FBB_MA3_BA3_L BA2/A4 BA0/A2 DQ11 DQ19 FBB_D20 <48> FBB_MA5_BA1_H BA3/A3 BA1/A5 DQ12 DQ20 FBB_D45 BYTE5
H10 N11 BYTE2 N13
<48> FBB_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 FBB_D21 DQ13 DQ21 FBB_D46
2G@ N13 M11
DQ13 DQ21 M11 FBB_D22 FBB_MA0_MA10_H K4 DQ14 DQ22 M13 FBB_D47
ia
FBB_MA7_MA8_L DQ14 DQ22 FBB_D23 <48> FBB_MA0_MA10_H FBB_MA6_MA11_H A8/A7 A10/A0 DQ15 DQ23 FBB_D32
K4 M13 H5 U4
<48> FBB_MA7_MA8_L FBB_MA1_MA9_L A8/A7 A10/A0 DQ15 DQ23 FBB_D24 <48> FBB_MA6_MA11_H FBB_MA7_MA8_H A9/A1 A11/A6 DQ0 DQ24 FBB_D33
H5 U4 H4 U2
<48> FBB_MA1_MA9_L FBB_MA0_MA10_L A9/A1 A11/A6 DQ0 DQ24 FBB_D25 <48> FBB_MA7_MA8_H FBB_MA1_MA9_H A10/A0 A8/A7 DQ1 DQ25 FBB_D34
H4 U2 K5 T4
<48> FBB_MA0_MA10_L FBB_MA6_MA11_L A10/A0 A8/A7 DQ1 DQ25 FBB_D26 <48> FBB_MA1_MA9_H FBB_MA12_RFU_H A11/A6 A9/A1 DQ2 DQ26 FBB_D35
K5 T4 J5 T2 BYTE4
<48> FBB_MA6_MA11_L FBB_MA12_RFU_L A11/A6 A9/A1 DQ2 DQ26 FBB_D27 <48> FBB_MA12_RFU_H A12/RFU/NC DQ3 DQ27 FBB_D36
J5 T2 BYTE3 N4
<48> FBB_MA12_RFU_L A12/RFU/NC DQ3 DQ27 FBB_D28 DQ4 DQ28 FBB_D37
N4 A5 N2
t
A5 DQ4 DQ28 N2 FBB_D29 +1.35VS_VGA U5 VPP/NC DQ5 DQ29 M4 FBB_D38
U5 VPP/NC DQ5 DQ29 M4 FBB_D30 2 RV131 1 VPP/NC DQ6 DQ30 M2 FBB_D39
2 RV132 1 VPP/NC DQ6 DQ30 M2 FBB_D31 1K_0402_1% DQ7 DQ31
1K_0402_1% DQ7 DQ31 J1 +1.35VS_VGA
+1.35VS_VGA 2G@ MF
2G@ J1 2 RV133 1 J10
n
2 RV134 1 J10 MF 2 RV135 1 1K_0402_1% J13 SEN B1
2 RV136 1 1K_0402_1% J13 SEN B1 121_0402_1% 2G@ ZQ VDDQ D1
121_0402_1% 2G@ ZQ VDDQ D1 VDDQ F1
VDDQ 2G@ FBB_ABI#_H VDDQ
2G@ F1 J4 M1
FBB_ABI#_L VDDQ <48> FBB_ABI#_H FBB_CAS#_H ABI# VDDQ
J4 M1 G3 P1
e
<48> FBB_ABI#_L FBB_RAS#_L ABI# VDDQ <48> FBB_CAS#_H FBB_WE#_H RAS# CAS# VDDQ
G3 P1 G12 T1
<48> FBB_RAS#_L FBB_CS#_L RAS# CAS# VDDQ <48> FBB_WE#_H FBB_RAS#_H CS# WE# VDDQ
G12 T1 L3 G2
<48> FBB_CS#_L FBB_CAS#_L CS# WE# VDDQ FBB_CLK1 <48> FBB_RAS#_H FBB_CS#_H CAS# RAS# VDDQ
L3 G2 L12 L2
<48> FBB_CAS#_L FBB_WE#_L CAS# RAS# VDDQ <48> FBB_CS#_H WE# CS# VDDQ
L12 L2 B3
<48> FBB_WE#_L WE# CS# VDDQ VDDQ
C B3 D3 C
1
VDDQ VDDQ
id
D3 F3
VDDQ F3 RV138 FBB_WCK3_N D5 VDDQ H3
FBB_WCK0_N VDDQ <48> FBB_WCK3_N FBB_WCK3 WCK01# WCK23# VDDQ
D5 H3 80.6_0402_1% D4 K3
<48> FBB_WCK0_N FBB_WCK0 WCK01# WCK23# VDDQ <48> FBB_WCK3 WCK01 WCK23 VDDQ
D4 K3 M3
<48> FBB_WCK0 WCK01 WCK23 VDDQ FBB_WCK2_N VDDQ
M3 P5 P3
<48> FBB_WCK2_N
2
FBB_WCK1_N P5 VDDQ P3 FBB_CLK1# FBB_WCK2 P4 WCK23# WCK01# VDDQ T3
<48> FBB_WCK1_N FBB_WCK1 WCK23# WCK01# VDDQ <48> FBB_WCK2 WCK23 WCK01 VDDQ
P4 T3 E5
f
<48> FBB_WCK1 WCK23 WCK01 VDDQ VDDQ
E5 2G@ N5
VDDQ N5 A10 VDDQ E10
A10 VDDQ E10 U10 VREFD VDDQ N10
U10 VREFD VDDQ N10 +FBB_VREFC J14 VREFD VDDQ B12
+FBB_VREFC J14 VREFD VDDQ B12 VREFC VDDQ D12
VREFC VDDQ VDDQ
n
D12 F12
VDDQ F12 VDDQ H12
VDDQ H12 FBB_RST#_H J2 VDDQ K12
FBB_RST#_L VDDQ <48> FBB_RST#_H RESET# VDDQ
J2 K12 M12
<48> FBB_RST#_L RESET# VDDQ VDDQ
M12 P12
VDDQ P12 VDDQ T12
o
VDDQ T12 VDDQ G13
VDDQ G13 H1 VDDQ L13
H1 VDDQ L13 K1 VSS VDDQ B14
K1 VSS VDDQ B14 B5 VSS VDDQ D14
B5 VSS VDDQ D14 G5 VSS VDDQ F14
G5 VSS VDDQ F14 L5 VSS VDDQ M14
L5 VSS VDDQ M14 T5 VSS VDDQ P14
C
T5 VSS VDDQ P14 B10 VSS VDDQ T14
B10 VSS VDDQ T14 D10 VSS VDDQ
D10 VSS VDDQ G10 VSS
G10 VSS L10 VSS A1
L10 VSS A1 P10 VSS VSSQ C1
P10 VSS VSSQ C1 T10 VSS VSSQ E1
T10 VSS VSSQ E1 H14 VSS VSSQ N1
H14 VSS VSSQ N1 K14 VSS VSSQ R1
K14 VSS VSSQ R1 +1.35VS_VGA VSS VSSQ U1
+1.35VS_VGA VSS VSSQ VSSQ
L
U1 H2
VSSQ H2 G1 VSSQ K2
G1 VSSQ K2 L1 VDD VSSQ A3
L1 A3 G4 C3
G4 VDD VSSQ C3 L4 VDD VSSQ E3
L4 VDD VSSQ E3 C5 VDD VSSQ N3
C5 VDD VSSQ N3 R5 VDD VSSQ R3
L
R5 VDD VSSQ R3 C10 VDD VSSQ U3
C10 VDD VSSQ U3 R10 VDD VSSQ C4
R10 VDD VSSQ C4 D11 VDD VSSQ R4
+1.35VS_VGA D11 VDD VSSQ R4 G11 VDD VSSQ F5
G11 VDD VSSQ F5 L11 VDD VSSQ M5
L11 VDD VSSQ M5 P11 VDD VSSQ F10
VDD VSSQ VDD VSSQ
1
P11 F10 G14 M10
E
RV197 G14 VDD VSSQ M10 L14 VDD VSSQ C11
549_0402_1% L14 VDD VSSQ C11 VDD VSSQ R11
VDD VSSQ VSSQ
W=16mils
R11 A12
RV200 VSSQ VSSQ
A12 C12
2
1 2 +FBB_VREFC VSSQ C12 VSSQ E12

VSSQ VSSQ
820P_0402_25V7
820P_0402_25V7
931_0402_1% E12 N12

VSSQ VSSQ
1
CV305
CV307
2G@ 1 1 N12 R12

RV202 VSSQ R12 170-BALL VSSQ U12
D
2G@ 1.33K_0402_1% 170-BALL VSSQ U12 VSSQ H13
1
D VSSQ H13 SGRAM GDDR5 VSSQ K13

2 2 2 SGRAM GDDR5 VSSQ K13 VSSQ A14
<46,51,53,54> MEM_VREF
2
G VSSQ A14 VSSQ C14

S QV24 VSSQ C14 VSSQ E14
3
VSSQ VSSQ
L2N7002WT1G 1N SC-70-3 2G@
one Close to UV8 E14 N14
r
VSSQ N14 VSSQ R14
one Close to UV9 VSSQ R14 VSSQ U14
2G@ 2G@ 2G@ VSSQ VSSQ
U14
VSSQ
o
H5GQ1H24AFR-T2L_BGA170
X76@
X76@
F
A A
CV238
CV239
CV248
CV243
CV242
CV247
CV237
CV249
CV246
CV244
CV245
CV241
CV156
CV240
CV214
CV250
CV232
CV231
CV234
CV199
CV198
CV213
CV230
CV235
CV233
CV210
CV211
CV175
CV155
CV174
CV202
CV236
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@

2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@ 2G@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V

Title
N15P_GDDR5_A Upper
5 4 3 2 1

5 4 3 2 1
Memory Part i t i on A- L ower 32 bi st UV13 MF=0 UV12 MF=1

MF=0 MF=1 MF=1 MF=0
FBC_D[0..63] MF=0 MF=1 MF=1 MF=0
<48> FBC_D[0..63] FBC_D56
A4
FBC_EDC[7..0] A4 FBC_D0 FBC_EDC7 C2 DQ24 DQ0 A2 FBC_D57
<48> FBC_EDC[7..0] FBC_EDC0 DQ24 DQ0 FBC_D1 FBC_EDC6 EDC0 EDC3 DQ25 DQ1 FBC_D58
C2 A2 C13 B4
FBC_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D2 FBC_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D59
FBC_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D3 FBC_EDC4 R2 EDC2 EDC1 DQ27 DQ3 E4 FBC_D60
FBC_EDC3 EDC2 EDC1 DQ27 DQ3 FBC_D4 BYTE0 EDC3 EDC0 DQ28 DQ4 FBC_D61 BYTE7
R2 E4 E2
EDC3 EDC0 DQ28 DQ4 E2 FBC_D5 DQ29 DQ5 F4 FBC_D62
DQ29 DQ5 F4 FBC_D6 FBC_DBI7# D2 DQ30 DQ6 F2 FBC_D63
FBC_DBI0# DQ30 DQ6 FBC_D7 <48> FBC_DBI7# FBC_DBI6# DBI0# DBI3# DQ31 DQ7 FBC_D48
D
D2 F2 D13 A11 D
<48> FBC_DBI0# FBC_DBI1# DBI0# DBI3# DQ31 DQ7 FBC_D8 <48> FBC_DBI6# FBC_DBI5# DBI1# DBI2# DQ16 DQ8 FBC_D49
D13 A11 P13 A13
<48> FBC_DBI1# FBC_DBI2# DBI1# DBI2# DQ16 DQ8 FBC_D9 <48> FBC_DBI5# FBC_DBI4# DBI2# DBI1# DQ17 DQ9 FBC_D50
P13 A13 P2 B11
<48> FBC_DBI2# FBC_DBI3# DBI2# DBI1# DQ17 DQ9 FBC_D10 <48> FBC_DBI4# DBI3# DBI0# DQ18 DQ10 FBC_D51
P2 B11 B13
FBC_CLK0 <48> FBC_DBI3# DBI3# DBI0# DQ18 DQ10 FBC_D11 FBC_CLK1 DQ19 DQ11 FBC_D52
FBC_CLK0 DQ19 DQ11 FBC_D12 <48> FBC_CLK1 FBC_CLK1# CK DQ20 DQ12 FBC_D53
J12 E11 J11 E13
<48> FBC_CLK0 FBC_CLK0# CK DQ20 DQ12 FBC_D13 <48> FBC_CLK1# FBC_CKE_H CK# DQ21 DQ13 FBC_D54
J11 E13 J3 F11
1 <48> FBC_CLK0# FBC_CKE_L CK# DQ21 DQ13 FBC_D14 <48> FBC_CKE_H CKE# DQ22 DQ14 FBC_D55
J3 F11 F13
<48> FBC_CKE_L CKE# DQ22 DQ14 FBC_D15 DQ23 DQ15 FBC_D40
RV179 F13 U11
80.6_0402_1% DQ23 DQ15 U11 FBC_D16 FBC_MA4_BA2_H H11 DQ8 DQ16 U13 FBC_D41
FBC_MA2_BA0_L DQ8 DQ16 FBC_D17 <48> FBC_MA4_BA2_H FBC_MA3_BA3_H BA0/A2 BA2/A4 DQ9 DQ17 FBC_D42
H11 U13 K10 T11
<48> FBC_MA2_BA0_L FBC_MA5_BA1_L BA0/A2 BA2/A4 DQ9 DQ17 FBC_D18 <48> FBC_MA3_BA3_H FBC_MA2_BA0_H BA1/A5 BA3/A3 DQ10 DQ18 FBC_D43
K10 T11 K11 T13
l
<48> FBC_MA5_BA1_L <48> FBC_MA2_BA0_H
2
FBC_CLK0# FBC_MA4_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D19 FBC_MA5_BA1_H H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBC_D44
<48> FBC_MA4_BA2_L FBC_MA3_BA3_L BA2/A4 BA0/A2 DQ11 DQ19 FBC_D20 <48> FBC_MA5_BA1_H BA3/A3 BA1/A5 DQ12 DQ20 FBC_D45 BYTE5
H10 N11 BYTE2 N13
<48> FBC_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 FBC_D21 DQ13 DQ21 FBC_D46
3G@ N13 M11
DQ13 DQ21 M11 FBC_D22 FBC_MA0_MA10_H K4 DQ14 DQ22 M13 FBC_D47
FBC_MA7_MA8_L DQ14 DQ22 FBC_D23 <48> FBC_MA0_MA10_H FBC_MA6_MA11_H A8/A7 A10/A0 DQ15 DQ23 FBC_D32
K4 M13 H5 U4
ia
<48> FBC_MA7_MA8_L FBC_MA1_MA9_L A8/A7 A10/A0 DQ15 DQ23 FBC_D24 <48> FBC_MA6_MA11_H FBC_MA7_MA8_H A9/A1 A11/A6 DQ0 DQ24 FBC_D33
H5 U4 H4 U2
<48> FBC_MA1_MA9_L FBC_MA0_MA10_L A9/A1 A11/A6 DQ0 DQ24 FBC_D25 <48> FBC_MA7_MA8_H FBC_MA1_MA9_H A10/A0 A8/A7 DQ1 DQ25 FBC_D34
H4 U2 K5 T4
<48> FBC_MA0_MA10_L FBC_MA6_MA11_L A10/A0 A8/A7 DQ1 DQ25 FBC_D26 <48> FBC_MA1_MA9_H FBC_MA12_RFU_H A11/A6 A9/A1 DQ2 DQ26 FBC_D35
K5 T4 J5 T2 BYTE4
<48> FBC_MA6_MA11_L FBC_MA12_RFU_L A11/A6 A9/A1 DQ2 DQ26 FBC_D27 <48> FBC_MA12_RFU_H A12/RFU/NC DQ3 DQ27 FBC_D36
J5 T2 BYTE3 N4
<48> FBC_MA12_RFU_L A12/RFU/NC DQ3 DQ27 FBC_D28 DQ4 DQ28 FBC_D37
N4 A5 N2
A5 DQ4 DQ28 N2 FBC_D29 +1.35VS_VGA U5 VPP/NC DQ5 DQ29 M4 FBC_D38
t
U5 VPP/NC DQ5 DQ29 M4 FBC_D30 2 RV165 1 VPP/NC DQ6 DQ30 M2 FBC_D39
2 RV161 1 VPP/NC DQ6 DQ30 M2 FBC_D31 1K_0402_1% DQ7 DQ31
1K_0402_1% DQ7 DQ31 J1 +1.35VS_VGA
+1.35VS_VGA 3G@ MF
3G@ J1 2 RV140 1 J10
2 RV159 1 J10 MF 2 RV160 1 1K_0402_1% J13 SEN B1
n
121_0402_1% 3G@ ZQ VDDQ D1 VDDQ F1
VDDQ 3G@ FBC_ABI#_H VDDQ
F1 J4 M1
3G@ FBC_ABI#_L VDDQ <48> FBC_ABI#_H FBC_CAS#_H ABI# VDDQ
J4 M1 G3 P1
<48> FBC_ABI#_L FBC_RAS#_L ABI# VDDQ <48> FBC_CAS#_H FBC_WE#_H RAS# CAS# VDDQ
G3 P1 G12 T1
e
<48> FBC_RAS#_L FBC_CS#_L RAS# CAS# VDDQ <48> FBC_WE#_H FBC_RAS#_H CS# WE# VDDQ
G12 T1 L3 G2
<48> FBC_CS#_L FBC_CAS#_L CS# WE# VDDQ FBC_CLK1 <48> FBC_RAS#_H FBC_CS#_H CAS# RAS# VDDQ
L3 G2 L12 L2
<48> FBC_CAS#_L FBC_WE#_L CAS# RAS# VDDQ <48> FBC_CS#_H WE# CS# VDDQ
L12 L2 B3
<48> FBC_WE#_L WE# CS# VDDQ VDDQ
B3 D3
VDDQ VDDQ
1
C D3 F3 C
VDDQ FBC_WCK3_N VDDQ
id
F3 RV141 D5 H3
FBC_WCK0_N VDDQ <48> FBC_WCK3_N FBC_WCK3 WCK01# WCK23# VDDQ
D5 H3 80.6_0402_1% D4 K3
<48> FBC_WCK0_N FBC_WCK0 WCK01# WCK23# VDDQ <48> FBC_WCK3 WCK01 WCK23 VDDQ
D4 K3 M3
<48> FBC_WCK0 WCK01 WCK23 VDDQ FBC_WCK2_N VDDQ
M3 P5 P3
<48> FBC_WCK2_N
2
FBC_WCK1_N P5 VDDQ P3 FBC_CLK1# FBC_WCK2 P4 WCK23# WCK01# VDDQ T3
<48> FBC_WCK1_N FBC_WCK1 WCK23# WCK01# VDDQ <48> FBC_WCK2 WCK23 WCK01 VDDQ
P4 T3 E5
<48> FBC_WCK1 WCK23 WCK01 VDDQ VDDQ
E5 3G@ N5
f
U10 VREFD VDDQ N10 +FBC_VREFC J14 VREFD VDDQ B12
+FBC_VREFC J14 VREFD VDDQ B12 VREFC VDDQ D12
VREFC VDDQ D12 VDDQ F12
VDDQ VDDQ
n
F12 H12
VDDQ H12 FBC_RST#_H J2 VDDQ K12
FBC_RST#_L VDDQ <48> FBC_RST#_H RESET# VDDQ
J2 K12 M12
<48> FBC_RST#_L RESET# VDDQ VDDQ
M12 P12
VDDQ P12 VDDQ T12
VDDQ T12 VDDQ G13
o
C
G10 VSS L10 VSS A1
+1.35VS_VGA K14 VSS VSSQ R1 +1.35VS_VGA VSS VSSQ U1
VSS VSSQ U1 VSSQ H2
VSSQ VSSQ
L
H2 G1 K2
L1 VDD VSSQ A3 G4 VDD VSSQ C3
G4 C3 L4 E3
L
+1.35VS_VGA R10 VDD VSSQ C4 D11 VDD VSSQ R4
D11 VDD VSSQ R4 G11 VDD VSSQ F5
VDD VSSQ VDD VSSQ
1
L11 M5 P11 F10

RV143 P11 VDD VSSQ F10 G14 VDD VSSQ M10
549_0402_1% G14 VDD VSSQ M10 L14 VDD VSSQ C11
E
VDD VSSQ VDD VSSQ
W=16mils
L14 C11 R11
RV164 VDD VSSQ VSSQ
R11 A12
2
1 2 +FBC_VREFC VSSQ A12 VSSQ C12

VSSQ VSSQ
820P_0402_25V7
820P_0402_25V7
931_0402_1% C12 E12

1
VSSQ VSSQ
CV179
CV300
3G@ 1 1 E12 N12

RV145 VSSQ N12 VSSQ R12
3G@ 1.33K_0402_1% VSSQ R12 170-BALL VSSQ U12
1
D
170-BALL VSSQ U12 VSSQ H13
D
2 2 2 VSSQ H13 SGRAM GDDR5 VSSQ K13
<46,51,52,54> MEM_VREF
2
G SGRAM GDDR5 VSSQ K13 VSSQ A14

S QV21 VSSQ A14 VSSQ C14
3
VSSQ VSSQ
L2N7002WT1G 1N SC-70-3 3G@ one Close to UV8 VSSQ
C14
E14 VSSQ
E14
N14
one Close to UV9 VSSQ N14 VSSQ R14
r
R14 U14
VSSQ U14 VSSQ
VSSQ X76@
X76@
o
F
A A
CV268
CV269
CV280
CV275
CV274
CV279
CV267
CV281
CV278
CV276
CV277
CV273
CV271
CV272
CV270
CV282
CV253
CV257
CV264
CV259
CV258
CV263
CV252
CV265
CV262
CV260
CV261
CV283
CV255
CV256
CV254
CV266
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
3G@
CV338
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
47U_0805_6.3V6M~D

Title
N15P_GDDR5_A Upper
5 4 3 2 1

5 4 3 2 1
Memory Part i t i on D UV15 MF=0 UV16 MF=1

MF=0 MF=1 MF=1 MF=0
FBD_D[0..63] MF=0 MF=1 MF=1 MF=0
<48> FBD_D[0..63] FBD_D56
A4
FBD_EDC[7..0] A4 FBD_D0 FBD_EDC7 C2 DQ24 DQ0 A2 FBD_D57
<48> FBD_EDC[7..0] FBD_EDC0 DQ24 DQ0 FBD_D1 FBD_EDC6 EDC0 EDC3 DQ25 DQ1 FBD_D58
C2 A2 C13 B4
FBD_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBD_D2 FBD_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBD_D59
FBD_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBD_D3 FBD_EDC4 R2 EDC2 EDC1 DQ27 DQ3 E4 FBD_D60
FBD_EDC3 EDC2 EDC1 DQ27 DQ3 FBD_D4 BYTE0 EDC3 EDC0 DQ28 DQ4 FBD_D61 BYTE7
R2 E4 E2
EDC3 EDC0 DQ28 DQ4 E2 FBD_D5 DQ29 DQ5 F4 FBD_D62
DQ29 DQ5 F4 FBD_D6 FBD_DBI7# D2 DQ30 DQ6 F2 FBD_D63
D FBD_DBI0# DQ30 DQ6 FBD_D7 <48> FBD_DBI7# FBD_DBI6# DBI0# DBI3# DQ31 DQ7 FBD_D48 D
D2 F2 D13 A11
<48> FBD_DBI0# FBD_DBI1# DBI0# DBI3# DQ31 DQ7 FBD_D8 <48> FBD_DBI6# FBD_DBI5# DBI1# DBI2# DQ16 DQ8 FBD_D49
D13 A11 P13 A13
<48> FBD_DBI1# FBD_DBI2# DBI1# DBI2# DQ16 DQ8 FBD_D9 <48> FBD_DBI5# FBD_DBI4# DBI2# DBI1# DQ17 DQ9 FBD_D50
P13 A13 P2 B11
<48> FBD_DBI2# FBD_DBI3# DBI2# DBI1# DQ17 DQ9 FBD_D10 <48> FBD_DBI4# DBI3# DBI0# DQ18 DQ10 FBD_D51
P2 B11 B13
FBD_CLK0 <48> FBD_DBI3# DBI3# DBI0# DQ18 DQ10 FBD_D11 FBD_CLK1 DQ19 DQ11 FBD_D52
FBD_CLK0 DQ19 DQ11 FBD_D12 <48> FBD_CLK1 FBD_CLK1# CK DQ20 DQ12 FBD_D53
J12 E11 J11 E13
<48> FBD_CLK0 FBD_CLK0# CK DQ20 DQ12 FBD_D13 <48> FBD_CLK1# FBD_CKE_H CK# DQ21 DQ13 FBD_D54
J11 E13 J3 F11
<48> FBD_CLK0# FBD_CKE_L CK# DQ21 DQ13 FBD_D14 <48> FBD_CKE_H CKE# DQ22 DQ14 FBD_D55
1
J3 F11 F13
<48> FBD_CKE_L CKE# DQ22 DQ14 FBD_D15 DQ23 DQ15 FBD_D40
RV182 F13 U11
80.6_0402_1% DQ23 DQ15 U11 FBD_D16 FBD_MA4_BA2_H H11 DQ8 DQ16 U13 FBD_D41
FBD_MA2_BA0_L DQ8 DQ16 FBD_D17 <48> FBD_MA4_BA2_H FBD_MA3_BA3_H BA0/A2 BA2/A4 DQ9 DQ17 FBD_D42
H11 U13 K10 T11
l
<48> FBD_MA2_BA0_L FBD_MA5_BA1_L BA0/A2 BA2/A4 DQ9 DQ17 FBD_D18 <48> FBD_MA3_BA3_H FBD_MA2_BA0_H BA1/A5 BA3/A3 DQ10 DQ18 FBD_D43
K10 T11 K11 T13
<48> FBD_MA5_BA1_L <48> FBD_MA2_BA0_H
2
FBD_CLK0# FBD_MA4_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBD_D19 FBD_MA5_BA1_H H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBD_D44
<48> FBD_MA4_BA2_L FBD_MA3_BA3_L BA2/A4 BA0/A2 DQ11 DQ19 FBD_D20 <48> FBD_MA5_BA1_H BA3/A3 BA1/A5 DQ12 DQ20 FBD_D45 BYTE5
H10 N11 BYTE2 N13
<48> FBD_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 FBD_D21 DQ13 DQ21 FBD_D46
4G@ N13 M11
DQ13 DQ21 M11 FBD_D22 FBD_MA0_MA10_H K4 DQ14 DQ22 M13 FBD_D47
ia
FBD_MA7_MA8_L DQ14 DQ22 FBD_D23 <48> FBD_MA0_MA10_H FBD_MA6_MA11_H A8/A7 A10/A0 DQ15 DQ23 FBD_D32
K4 M13 H5 U4
<48> FBD_MA7_MA8_L FBD_MA1_MA9_L A8/A7 A10/A0 DQ15 DQ23 FBD_D24 <48> FBD_MA6_MA11_H FBD_MA7_MA8_H A9/A1 A11/A6 DQ0 DQ24 FBD_D33
H5 U4 H4 U2
<48> FBD_MA1_MA9_L FBD_MA0_MA10_L A9/A1 A11/A6 DQ0 DQ24 FBD_D25 <48> FBD_MA7_MA8_H FBD_MA1_MA9_H A10/A0 A8/A7 DQ1 DQ25 FBD_D34
H4 U2 K5 T4
<48> FBD_MA0_MA10_L FBD_MA6_MA11_L A10/A0 A8/A7 DQ1 DQ25 FBD_D26 <48> FBD_MA1_MA9_H FBD_MA12_RFU_H A11/A6 A9/A1 DQ2 DQ26 FBD_D35
K5 T4 J5 T2 BYTE4
<48> FBD_MA6_MA11_L FBD_MA12_RFU_L A11/A6 A9/A1 DQ2 DQ26 FBD_D27 <48> FBD_MA12_RFU_H A12/RFU/NC DQ3 DQ27 FBD_D36
J5 T2 BYTE3 N4
<48> FBD_MA12_RFU_L A12/RFU/NC DQ3 DQ27 FBD_D28 DQ4 DQ28 FBD_D37
N4 A5 N2
t
A5 DQ4 DQ28 N2 FBD_D29 +1.35VS_VGA U5 VPP/NC DQ5 DQ29 M4 FBD_D38
U5 VPP/NC DQ5 DQ29 M4 FBD_D30 2 RV172 1 VPP/NC DQ6 DQ30 M2 FBD_D39
2 RV204 1 VPP/NC DQ6 DQ30 M2 FBD_D31 1K_0402_1% DQ7 DQ31
1K_0402_1% DQ7 DQ31 J1 +1.35VS_VGA
+1.35VS_VGA 4G@ MF
4G@ J1 2 RV188 1 J10
n
2 RV185 1 J10 MF 2 RV166 1 1K_0402_1% J13 SEN B1
121_0402_1% 4G@ ZQ VDDQ D1 VDDQ F1
VDDQ 4G@ FBD_ABI#_H VDDQ
4G@ F1 J4 M1
FBD_ABI#_L VDDQ <48> FBD_ABI#_H FBD_CAS#_H ABI# VDDQ
J4 M1 G3 P1
e
<48> FBD_ABI#_L FBD_RAS#_L ABI# VDDQ <48> FBD_CAS#_H FBD_WE#_H RAS# CAS# VDDQ
G3 P1 G12 T1
<48> FBD_RAS#_L FBD_CS#_L RAS# CAS# VDDQ <48> FBD_WE#_H FBD_RAS#_H CS# WE# VDDQ
G12 T1 L3 G2
<48> FBD_CS#_L FBD_CAS#_L CS# WE# VDDQ FBD_CLK1 <48> FBD_RAS#_H FBD_CS#_H CAS# RAS# VDDQ
L3 G2 L12 L2
<48> FBD_CAS#_L FBD_WE#_L CAS# RAS# VDDQ <48> FBD_CS#_H WE# CS# VDDQ
L12 L2 B3
<48> FBD_WE#_L WE# CS# VDDQ VDDQ
C B3 D3 C
1
VDDQ VDDQ
id
D3 F3
VDDQ F3 RV212 FBD_WCK3_N D5 VDDQ H3
FBD_WCK0_N VDDQ <48> FBD_WCK3_N FBD_WCK3 WCK01# WCK23# VDDQ
D5 H3 80.6_0402_1% D4 K3
<48> FBD_WCK0_N FBD_WCK0 WCK01# WCK23# VDDQ <48> FBD_WCK3 WCK01 WCK23 VDDQ
D4 K3 M3
<48> FBD_WCK0 WCK01 WCK23 VDDQ FBD_WCK2_N VDDQ
M3 P5 P3
<48> FBD_WCK2_N
2
FBD_WCK1_N P5 VDDQ P3 FBD_CLK1# FBD_WCK2 P4 WCK23# WCK01# VDDQ T3
<48> FBD_WCK1_N FBD_WCK1 WCK23# WCK01# VDDQ <48> FBD_WCK2 WCK23 WCK01 VDDQ
P4 T3 E5
f
<48> FBD_WCK1 WCK23 WCK01 VDDQ VDDQ
E5 4G@ N5
U10 VREFD VDDQ N10 +FBD_VREFC J14 VREFD VDDQ B12
+FBD_VREFC J14 VREFD VDDQ B12 VREFC VDDQ D12
VREFC VDDQ VDDQ
n
D12 F12
VDDQ F12 VDDQ H12
VDDQ H12 FBD_RST#_H J2 VDDQ K12
FBD_RST#_L VDDQ <48> FBD_RST#_H RESET# VDDQ
J2 K12 M12
<48> FBD_RST#_L RESET# VDDQ VDDQ
M12 P12
VDDQ P12 VDDQ T12
o
VDDQ T12 VDDQ G13
C
G10 VSS L10 VSS A1
K14 VSS VSSQ R1 +1.35VS_VGA VSS VSSQ U1
+1.35VS_VGA VSS VSSQ VSSQ
L
U1 H2
VSSQ H2 G1 VSSQ K2
L1 A3 G4 C3
G4 VDD VSSQ C3 L4 VDD VSSQ E3
L
R10 VDD VSSQ C4 D11 VDD VSSQ R4
+1.35VS_VGA D11 VDD VSSQ R4 G11 VDD VSSQ F5
L11 VDD VSSQ M5 P11 VDD VSSQ F10
VDD VSSQ VDD VSSQ
1
P11 F10 G14 M10
E
RV203 G14 VDD VSSQ M10 L14 VDD VSSQ C11
549_0402_1% L14 VDD VSSQ C11 VDD VSSQ R11
VDD VSSQ VSSQ
W=16mils
R11 A12
RV206 VSSQ VSSQ
A12 C12
2
1 2 +FBD_VREFC VSSQ C12 VSSQ E12

VSSQ VSSQ
820P_0402_25V7
820P_0402_25V7
931_0402_1% E12 N12

VSSQ VSSQ
1
CV309
CV311
4G@ 1 1 N12 R12

RV209 VSSQ R12 170-BALL VSSQ U12
D
4G@ 1.33K_0402_1% 170-BALL VSSQ U12 VSSQ H13
1
D VSSQ H13 SGRAM GDDR5 VSSQ K13

2 2 2 SGRAM GDDR5 VSSQ K13 VSSQ A14
<46,51,52,53> MEM_VREF
2
G VSSQ A14 VSSQ C14

S QV25 VSSQ C14 VSSQ E14
3
VSSQ VSSQ
L2N7002WT1G 1N SC-70-3 4G@
one Close to UV8 E14 N14
r
VSSQ N14 VSSQ R14
one Close to UV9 VSSQ R14 VSSQ U14
U14
VSSQ X76@
X76@
o
F
A A
CV292
CV293
CV296
CV191
CV190
CV194
CV313
CV297
CV295
CV314
CV193
CV189
CV188
CV192
CV294
CV298
CV286
CV285
CV288
CV187
CV182
CV186
CV284
CV289
CV287
CV184
CV185
CV181
CV315
CV180
CV291
CV290
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
4G@
CV339
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
1U_0402_6.3V
47U_0805_6.3V6M~D
Title
N15P_GDDR5_A Upper
5 4 3 2 1

5 4 3 2 1
+3.3V_GFX_AON
UV1 UV1 UV1 ZZZ ZZZ ZZZ
2
RV230 RV218 RV217 RV214 RV219 N16E-GS N16E-GT N16E-GX H5GC4H24MFR-T2C H5GC4H24MFR-T2C H5GC4H24MFR-T2C
49.9K_0402_1% 34.8K_0402_1% 4.99K_0402_1% 15K_0402_1% 20K_0402_1% GSR1@ GTR1@ GXR1@ H2GR3@ H3GR3@ H4GR3@
@ @ @ @ SA00008550L SA00008520L SA00008530L X7656331L23 X7656331L25 X7656331L27
1
STRAP0 UV1 UV1 UV1 ZZZ ZZZ ZZZ
<47> STRAP0 STRAP1
D <47> STRAP1 D
STRAP2
<47> STRAP2 STRAP3
<47> STRAP3 STRAP4
<47> STRAP4
2
N16E-GS N16E-GT N16E-GX H5GC4H24MFR-T2C H5GC4H24MFR-T2C H5GC4H24MFR-T2C
@ RV228 RV216 RV232 RV221 RV224 GSR3@ GTR3@ GXR3@ S2GR3@ S3GR3@ S4GR3@
45.3K_0402_1% 4.99K_0402_1% 15K_0402_1% 15K_0402_1% 45.3K_0402_1% SA00008551L SA00008521L SA00008531L X7656331L24 X7656331L26 X7656331L28
@ @ @ @
1
l
1
1
ia
+3.3V_GFX_AON
t
2
2 n
RV229 RV231 RV233
4.99K_0402_1% 4.99K_0402_1% 24.9K_0402_1%
Hyn@ @
ROM_SI @
e
1
1
<47> ROM_SI ROM_SO
<47> ROM_SO ROM_SCLK
<47> ROM_SCLK
RV215
id
2
2
RV215
15K_0402_1% RV223 RV226
@ 4.99K_0402_1% 15K_0402_1% UV6 UV7 UV8 UV9
1
C 20K_0402_1% 3/30 Change 15K, NV request. C
f
1
Sam@
SD034200280
H5GC4H24MFR-T2C H5GC4H24MFR-T2C H5GC4H24MFR-T2C H5GC4H24MFR-T2C

H2G@ H2G@ H2G@ H2G@
n
SA00006O40L SA00006O40L SA00006O40L SA00006O40L
R_pu
o
VRAM Strap ROM-SI UV6 UV7 UV8 UV9 UV12 UV13
Hynix H5GC4H24MFR-T2C 0x2 PL 15K

Samsung K4G41325FC-HC03 0x3 PL 20K
Hynix H5GC4H24AJR-R0C 0x8 PH 5K Set as Hynix H5GC4H24AJR-T2C @5G H5GC4H24MFR-T2C H5GC4H24MFR-T2C H5GC4H24MFR-T2C H5GC4H24MFR-T2C H5GC4H24MFR-T2C H5GC4H24MFR-T2C
C
H3G@ H3G@ H3G@ H3G@ H3G@ H3G@
SA00006O40L SA00006O40L SA00006O40L SA00006O40L SA00006O40L SA00006O40L
UV12 UV13 UV15 UV16

UV6 UV7 UV8 UV9
4.99K
PU to 3V3
1000
PD to GND
0000
L L
PCI_DEVID
SUB_VENDER
H5GC4H24MFR-T2C H5GC4H24MFR-T2C H5GC4H24MFR-T2C H5GC4H24MFR-T2C
H4G@
SA00006O40L
H4G@
SA00006O40L
H4G@
SA00006O40L
H4G@
SA00006O40L
H5GC4H24MFR-T2C H5GC4H24MFR-T2C
H4G@
SA00006O40L
H4G@
SA00006O40L
H5GC4H24MFR-T2C
H4G@
SA00006O40L
H5GC4H24MFR-T2C
H4G@
SA00006O40L
E
10K 1001 0001
0- w/o dGPU ROM
B B
15K 1010 0010 1-w/ dGPU ROM

20K 1011 0011
FB[1:0]
24.9K 1100 0100 0-Reserved
1-Reserved
D
30.1K 1101 0101 2-256M
34.8K 1110 0110 3-Reserved
45.3K 1111 0111 VGA_DEVICE
r
0- Non-permary 3D
1-
Physical Logical Logical Logical Logical
SMB_ALT_ADDR Strapping pin Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
o
0-0x9E
1-0x9C(Mult i - GP U) PCI_DEVID[4] SUB_VENDER PCI_DEVID[5] PEX_PLL_EN_TERM
ROM_SCLK
PEX_PLL_EN_TERM
0-Disable
F
ROM_SO RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
1-Enable
3GIO_PADCFG ROM_SI FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
0110-GEN1/GEN2
0000-GEN3 STRAP0 USER[3] USER[2] USER[1] USER[0]
STRAP1 3GIO_CFG[3] 3GIO_CFG[2] 3GIO_CFG[1] 3GIO_CFG[0]
PCIE_MAX_SPEED
0-boot i ng t o PCI E Gen1 STRAP2 PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
1-boot i ng t o PCI E Gen2/ Gen3
STRAP3 SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
PCIE_SPEED_CHNAGE_GEN3
A 0-Disable PCIE Gen3 RESERVED PCIE_SPEED PCIE_MAX_SPEED DP_PLL_VDD33V A
1-Enable PCIE Gen3 STRAP4 _CHNAGE_GEN3

C 0.1
5 4 3 2 1

5 4 3 2 1
[AAX06-PWR Sequence_SKL-H 4+4_DDR4_Volume_NON CS]
G3->S0 S0->S3/DS3 S0/ DS3 ->S0 S0->S5

+3VL_RTC +3VL_RTC
tPCH01_Min : 9 ms
D SOC_RTCRST# SOC_RTCRST# D
+19VB +19VB
+3VLP/+5VLP +3VLP/+5VLP
EC_ON EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW/+3VALW_DSW +5VALW/+3VALW/+3VALW_DSW
Pull-up to DSW well if not implemented.
PM_BATLOW# PM_BATLOW#
l
PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)
+3V_PRIM +3V_PRIM
ia
+1.8V_PRIM +1.8V_PRIM
EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#

gate may choose to completely ignore it
+1.0V_MPHYPLL +1.0V_MPHYPLL
t
+1.0V_PRIM_CORE +1.0V_PRIM_CORE
tPCH34_Max : 20 ms
+1.0V_PRIM tPCH06_Min : 200 us +1.0V_PRIM
n
SUSACK# SUSACK#
tPCH02_Min : 10 ms
e
PCH_DPWROK PCH_DPWROK
tPCH03_Min : 10 ms
EC_RSMRST# EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms
id
AC_PRESENT AC_PRESENT
C C
ON/OFF ON/OFF
tPCH43_Min : 95 ms
PBTN_OUT# PBTN_OUT#
f
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
PM_SLP_S5# PM_SLP_S5#
tPCH18_Min : 90 us
ESPI_RST# ESPI_RST#
n
SYSON SYSON
o
+1.0V_VCCST/+1.0V_VCCSFR +1.0V_VCCST/+1.0V_VCCSFR
+1.35V_VDDQ/+1.35V_VCCSFR_OC +1.35V_VDDQ/+1.35V_VCCSFR_OC
C
SUSP# SUSP#
tCPU04 Min : 100 ns
+1.0VS_VCCSTG +1.0VS_VCCSTG
tCPU10 Min : 1 ms
+1.0VS_VCCIO +1.0VS_VCCIO
L
T <=10msec
+5VS/+3VS/+1.5VS/+1.05VS
+5VS/+3VS/+1.5VS/+1.05VS
T = 10msec
B EC_VCCST_PG EC_VCCST_PG B
L
VR_ON VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL SM_PG_CTRL
tCPU18 Max : 35 us
E
+0.675VS_VTT +0.675VS_VTT
tCPU09 Min : 1 ms
+VCC_SA +VCC_SA
+VCC_CORE +VCC_CORE
D
+VCC_GT +VCC_GT
VR_PWRGD VR_PWRGD
tCPU16 Min : 0 ns
r
PCH_PWROK PCH_PWROK
H_CPUPWRGD H_CPUPWRGD
SYS_PWROK SYS_PWROK
o
SUS_STAT# SUS_STAT#
SOC_PLTRST#
SOC_PLTRST#
F Security Classification
Compal Secret Data
Deciphered Date 2016/12/31
Title
Title
Size Document
Size
Custom
Document
Power
Number
Number
Sequence
LA-C912P
Ree vv
R
0.1
A
Date:
Date: Wednesday, July 22, 2015 Sheet
Sheet 56 of 78
5 4 3 2 1

5 4 3 2 1
D D
ia l
n t
C
id e C
Empty page n f
C o
B
L L B
D E
o r
A
F A

Mini DP/Thunder Bolt power
5 4 3 2 1

5 4 3 2 1
UT1A
0.22U_0201_6.3V6M 2 1 TBT@ CT1 PCIE_PTX_C_DRX_P1 Y23 V23 PCIE_PRX_C_DTX_P1 0.22U_0201_6.3V6M 2 1 TBT@ CT12
<19> PCIE_PTX_DRX_P1 2 1 TBT@ CT13 PCIE_PTX_C_DRX_N1 Y22 PCIE_RX0_P PCIE_TX0_P V22 PCIE_PRX_C_DTX_N1 2 1 TBT@ CT2 PCIE_PRX_DTX_P1 <19>
0.22U_0201_6.3V6M 0.22U_0201_6.3V6M
<19> PCIE_PTX_DRX_N1 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_DTX_N1 <19>
0.22U_0201_6.3V6M 2 1 TBT@ CT3 PCIE_PTX_C_DRX_P2 T23 P23 PCIE_PRX_C_DTX_P2 0.22U_0201_6.3V6M 2 1 TBT@ CT14
PCIe GEN3
<19> PCIE_PTX_DRX_P2 PCIE_RX1_P PCIE_TX1_P PCIE_PRX_DTX_P2 <19>
0.22U_0201_6.3V6M 2 1 TBT@ CT15 PCIE_PTX_C_DRX_N2 T22 P22 PCIE_PRX_C_DTX_N2 0.22U_0201_6.3V6M 2 1 TBT@ CT16
PCIE X4 Bus 2 1 TBT@ CT4 PCIE_PTX_C_DRX_P3 PCIE_PRX_C_DTX_P3 2 1 TBT@ CT17
(Link to CPU Port 1~4) 0.22U_0201_6.3V6M M23 K23 0.22U_0201_6.3V6M
0.22U_0201_6.3V6M 2 1 TBT@ CT18 PCIE_PTX_C_DRX_N3 M22 K22 PCIE_PRX_C_DTX_N3 0.22U_0201_6.3V6M 2 1 TBT@ CT19
D D
+3.3V_LC 0.22U_0201_6.3V6M 2 1 TBT@ CT5 PCIE_PTX_C_DRX_P4 H23 F23 PCIE_PRX_C_DTX_P4 0.22U_0201_6.3V6M 2 1 TBT@ CT20
0.22U_0201_6.3V6M 2 1 TBT@ CT21 PCIE_PTX_C_DRX_N4 H22 F22 PCIE_PRX_C_DTX_N4 0.22U_0201_6.3V6M 2 1 TBT@ CT22
<19> PCIE_PTX_DRX_N4 PCIE_RX3_N PCIE_TX3_N PCIE_PRX_DTX_N4 <19> From CPU pin BB8
V19 L4 TBT_RST#_R RT1 1 @ 2 0_0201_5%
PCIE CLK <17> CLK_PCIE_P3 PCIE_REFCLK_100_IN_P PERST_N PLT_RST# <17,28,29,30,31,43>
(From PCH CLKOUT0) T19
<17> CLK_PCIE_N3 CLKREQ_PCIE#3_R PCIE_REFCLK_100_IN_N PCIE_RBIAS
RT2 1 @ 2 0_0402_5% AC5 N16 RT3 1 TBT@ 2 3.01K_0201_1%
<17> CLKREQ_PCIE#3
1
PCIE_CLKREQ_N PCIE_RBIAS
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
RT6 RT7 RT8 RT9

CPU_DP1_P0_C
l
CT6 TBT@ 1 2 0.1U_0201_6.3V6K AB7 R2
<7> CPU_DP1_P0 CPU_DP1_N0_C DPSNK0_ML0_P DPSRC_ML0_P
TBT@ TBT@ TBT@ TBT@ <7> CPU_DP1_N0 CT7 TBT@ 1 2 0.1U_0201_6.3V6K AC7 R1
+3.3V_LC DPSNK0_ML0_N DPSRC_ML0_N
JTAG1 CT8 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_P1_C AB9 N2
<7> CPU_DP1_P1
2
CPU_DP1_N1_C DPSNK0_ML1_P DPSRC_ML1_P
ia
1 CT9 TBT@ 1 2 0.1U_0201_6.3V6K AC9 N1
SOURCE PORT 0
TBT_TDI 1 <7> CPU_DP1_N1 DPSNK0_ML1_N DPSRC_ML1_N
2
SINK PORT 0
TBT_TMS 3 2 CT10 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_P2_C AB11 L2
TBT_TCK 3 <7> CPU_DP1_P2 CPU_DP1_N2_C DPSNK0_ML2_P DPSRC_ML2_P
4 CT23 TBT@ 1 2 0.1U_0201_6.3V6K AC11 L1
TBT_TDO 4 <7> CPU_DP1_N2 DPSNK0_ML2_N DPSRC_ML2_N
5
6 5 CT11 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_P3_C AB13 J2
t
6 CPU DDI1 <7> CPU_DP1_P3 CPU_DP1_N3_C DPSNK0_ML3_P DPSRC_ML3_P
CT24 TBT@ 1 2 0.1U_0201_6.3V6K AC13 J1
<7> CPU_DP1_N3 DPSNK0_ML3_N DPSRC_ML3_N
7
8 GND CT25 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_AUXP_C Y11 W19
GND <7> CPU_DP1_AUXP CPU_DP1_AUXN_C DPSNK0_AUX_P DPSRC_AUX_P
CT26 TBT@ 1 2 0.1U_0201_6.3V6K W11 Y19
<7> CPU_DP1_AUXN DPSNK0_AUX_N DPSRC_AUX_N
n
ACES_50228-0067N-001
AA2 G1 TBT_SRC_HPD RT4 1 TBT@ 2 1M_0201_1%
@ <16> DDI1_PCH_HPD DPSNK0_HPD DPSRC_HPD
DDI1_DDPB_CTRLCLK Y5 N6 DPSRC_RBIAS RT5 1 TBT@ 2 14K_0402_1%
DDC:3.3V <16> DDI1_DDPB_CTRLCLK DDI1_DDPB_CTRLDAT DPSNK0_DDC_CLK DPSRC_RBIAS
e
R4
<16> DDI1_DDPB_CTRLDAT DPSNK0_DDC_DATA
PU @ SOC side CPU_DP2_P0_C GPIO_0
U1 TBT_I2C_SDA <60>
CT27 TBT@ 1 2 0.1U_0201_6.3V6K AB15 U2
+3VS_TBT <7> CPU_DP2_P0 CPU_DP2_N0_C DPSNK1_ML0_P GPIO_1 TBT_EE_WP_N TBT_I2C_SCL <60>
CT28 TBT@ 1 2 0.1U_0201_6.3V6K AC15 V1
LC GPIO
<7> CPU_DP2_N0 DPSNK1_ML0_N GPIO_2 TBT_TMU_CLK_OUT
V2
id
CPU_DP1_AUXN CPU_DP2_P1_C GPIO_3 TBT_PCIE_WAKE_N @ T1
100K_0201_5% 2 @ 1 RT80 <7> CPU_DP2_P1 CT29 TBT@ 1 2 0.1U_0201_6.3V6K AB17 W1 RT10 1 @ 2 0_0201_5% TBT_PCIE_WAKE# <43>
To CPU pin BP9
CPU_DP2_AUXN 100K_0201_5% 2 @ 1 RT81 CT30 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP2_N1_C AC17 DPSNK1_ML1_P GPIO_4 W2 TBT_CIO_PLUG_EVENT# To CPU pin AW6
<7> CPU_DP2_N1 DPSNK1_ML1_N GPIO_5 TBT_HDMI_DDC_DATA TBT_CIO_PLUG_EVENT# <20>
Y1
CPU_DP2_P2_C GPIO_6 TBT_HDMI_DDC_CLK @ T7
CT31 TBT@ 1 2 0.1U_0201_6.3V6K AB19 Y2
SINK PORT 1
CPU_DP1_AUXP 100K_0201_5% <7> CPU_DP2_P2 CPU_DP2_N2_C DPSNK1_ML2_P GPIO_7 TBT_SRC_CFG1 @ T9
2 @ 1 RT79 CT32 TBT@ 1 2 0.1U_0201_6.3V6K AC19 AA1 RT11 1 TBT@ 2 1M_0201_1%
C CPU_DP2_AUXP 100K_0201_5% <7> CPU_DP2_N2 DPSNK1_ML2_N GPIO_8 TBTA_I2C_INT C
2 @ 1 RT78 J4
f
CPU DDI2 CPU_DP2_P3_C POC_GPIO_0 TBTB_I2C_INT TBTA_I2C_INT <60>
CT33 TBT@ 1 2 0.1U_0201_6.3V6K AB21 E2
POC GPIO
<7> CPU_DP2_P3 CPU_DP2_N3_C DPSNK1_ML3_P POC_GPIO_1 RTD3_USB_PWR_EN_R
CT34 TBT@ 1 2 0.1U_0201_6.3V6K AC21 D4 RT12 1 @ 2 0_0201_5% From CPU pin AW10
<7> CPU_DP2_N3 DPSNK1_ML3_N POC_GPIO_2 TBT_FORCE_PWR_R RTD3_USB_PWR_EN <20>
H4 RT13 1 @ 2 0_0201_5% TBT_FORCE_PWR <17>
From CPU pin G11
CT35 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP2_AUXP_C Y12 POC_GPIO_3 F2 BATLOW# RT14 1 @ 2 0_0201_5% From CPU pin BD16
<7> CPU_DP2_AUXP DPSNK1_AUX_P POC_GPIO_4 PCH_BATLOW# <18>
n
CT36 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP2_AUXN_C W12 D2 SLP_S3#_R From EC pin 116
<7> CPU_DP2_AUXN DPSNK1_AUX_N POC_GPIO_5 RTD3_CIO_PWR_EN_R
F1 RT16 1 @ 2 0_0201_5% From CPU pin BC3
POC_GPIO_6 RTD3_CIO_PWR_EN <20>
Y6
<16> DDI2_PCH_HPD DPSNK1_HPD TBT_TEST_EN
E1 RT17 1 TBT@ 2 100_0201_5%
+3VS_TBT DDI2_DDPC_CTRLCLK Y8 TEST_EN
Misc
o
<16> DDI2_DDPC_CTRLCLK DDI2_DDPC_CTRLDAT DPSNK1_DDC_CLK TBT_TEST_PWG
N4 AB5 RT18 1 TBT@ 2 100_0201_5%
<16> DDI2_DDPC_CTRLDAT DPSNK1_DDC_DATA TEST_PWR_GOOD YT1
2 TBT@ 1 DPSNK_RBIAS Y18 F4 TBT_RESET_N 25MHZ_12PF_7V25000012
CLKREQ_PCIE#3_R DPSNK_RBIAS RESET_N TBT_RESET_N <60>
RT20 2 TBT@ 1 10K_0201_5% RT19 14K_0402_1% RT23 1 @ 2 0_0201_5% TBT_RESET_N_EC <43>
TBT_TDI Y4 D22 TBT_XTAL_25_IN 1 3
TBT_TMS V4 TDI XTAL_25_IN D23 TBT_XTAL_25_OUT 1 3
1 1
C
TBT_TCK T4 TMS XTAL_25_OUT GND GND
TBT_TDO W4 TCK AB3 CT37 TBT@ CT38
TDO MISC EE_DI TBT_EE_DI <60> 2 4
AC4 TBT_EE_DO <60> 12P_0402_50V 12P_0402_50V
2 TBT@ 1 TBT_RBIAS H6 EE_DO AC3 2 2
TBT_RSENSE RBIAS EE_CS_N TBT_EE_CS_N <60> TBT@ TBT@
RT25 4.75K_0402_0.5% J6 AB4 TBT_EE_CLK <60>
+3.3V_TBT_SX RSENSE EE_CLK
A15 B7
TBT_I2C_SDA <60> USB3_A_TRX_DTX_P1 PA_RX1_P PB_RX1_P
RT26 2 TBT@ 1 3.3K_0201_5% <60> USB3_A_TRX_DTX_N1 B15 A7
L
TBT_I2C_SCL RT27 2 TBT@ 1 3.3K_0201_5% PA_RX1_N PB_RX1_N
TBT_PCIE_WAKE_N RT28 2 TBT@ 1 10K_0201_5% CT39 TBT@ 2 1 0.22U_0201_6.3V6M USB3_A_TTX_DRX_P1 A17 A9
TBT_CIO_PLUG_EVENT# <60> USB3_A_TTX_C_DRX_P1 USB3_A_TTX_DRX_N1 B17 PA_TX1_P PB_TX1_P
RT29 2 TBT@ 1 10K_0201_5% CT40 TBT@ 2 1 0.22U_0201_6.3V6M B9
SLP_S3#_R <60> USB3_A_TTX_C_DRX_N1 PA_TX1_N PB_TX1_N
RT30 2 @ 1 10K_0201_5%
BATLOW# RT31 2 TBT@ 1 10K_0201_5% CT41 TBT@ 2 1 0.22U_0201_6.3V6M USB3_A_TTX_DRX_P0 A19 A11
TBTA_I2C_INT <60> USB3_A_TTX_C_DRX_P0 USB3_A_TTX_DRX_N0 B19 PA_TX0_P PB_TX0_P 4/8 Fix Fan run and stop when Plug AC.
RT32 2 TBT@ 1 10K_0201_5% CT42 TBT@ 2 1 0.22U_0201_6.3V6M B11
L
TBTB_I2C_INT <60> USB3_A_TTX_C_DRX_N0 PA_TX0_N PB_TX0_N
RT33 2 TBT@ 1 10K_0201_5%
TBT PORTS
B21 A13 SLP_S3#_R 1 2
TBT_TMU_CLK_OUT <60> USB3_A_TRX_DTX_P0 PA_RX0_P PB_RX0_P SUSP# <43,45,64,74>
RT34 1 TBT@ 2 100K_0201_5% A21 B13
Port A
PORT B
TBT_FORCE_PWR_R <60> USB3_A_TRX_DTX_N0 PA_RX0_N PB_RX0_N
RT35 1 TBT@ 2 100K_0201_5% DT16 SDM10U45-7_SOD523-2
2
RTD3_CIO_PWR_EN_R RT36 1 TBT@ 2 100K_0201_5% CT43 TBT@ 2 1 0.1U_0201_6.3V6K TBT_A_AUX_P Y15 Y16
RTD3_USB_PWR_EN_R <60> TBT_A_AUX_P_C TBT_A_AUX_N PA_DPSRC_AUX_P PB_DPSRC_AUX_P
E
B RT37 1 TBT@ 2 100K_0201_5% <60> TBT_A_AUX_N_C CT44 TBT@ 2 1 0.1U_0201_6.3V6K W15 W16 RT105 B
DDI1_PCH_HPD RT38 1 TBT@ 2 100K_0201_5% PA_DPSRC_AUX_N PB_DPSRC_AUX_N
10K_0402_5%
DDI2_PCH_HPD RT39 1 TBT@ 2 100K_0201_5% E20 E19
TBTA_LSTX <60> TBT_A_USB20_P PA_USB2_D_P PB_USB2_D_P
RT40 1 TBT@ 2 1M_0201_1% <60> TBT_A_USB20_N D20 D19
1
TBTA_HPD RT41 1 TBT@ 2 100K_0201_5% PA_USB2_D_N PB_USB2_D_N
TBTA_LSRX RT42 1 TBT@ 2 1M_0201_1% A5 B4 NC_B4
<60> TBTA_LSTX PA_LSTX PB_LSTX NC_B5
POC
POC
A4 B5
D
<60> TBTA_LSRX PA_LSRX PB_LSRX NC_G2
M4 G2
<60> TBTA_HPD PA_DPSRC_HPD PB_DPSRC_HPD
2 TBT@ 1 PA_USB2_RBIAS H19 F19 PB_USB2_RBIAS 1 TBT@ 2
NC_B4 RT45 1 TBT@ 2 100K_0201_5% RT43 499_0201_1% PA_USB2_RBIAS PB_USB2_RBIAS RT44 499_0201_1%
NC_B5 RT46 1 TBT@ 2 100K_0201_5% AC23 D6
NC_G2 THERMDA MONDC_SVR
r
RT47 1 TBT@ 2 100K_0201_5% AB23
THERMDA A23
V18 ATEST_P B23
CLKREQ_PCIE#3 RT108 1 TBT@ 2 10K_0201_5% PCIE_ATEST ATEST_N
AC1 DEBUG E18
o
TEST_EDM USB2_ATEST +3.3V_FLASH
L15 W13
N15 FUSE_VQPS_64 MONDC_DPSNK_0
FUSE_VQPS_128 W18
C23 MONDC_DPSNK_1
1
F
1
1
MONDC_CIO_0
3.3K_0402_5%
C22 AB2
MONDC_CIO_1 MONDC_DPSRC RT48 RT49 RT50 CT45 RT51
AR4C_FC-CSP337 3.3K_0402_5% 3.3K_0402_5% 0.1U_0402_10V7K 3.3K_0402_5%
TBT_PD@ 2
TBT_PD@ TBT_PD@ UT2 TBT_PD@ TBT_PD@
2
TBT@ TBT_EE_CS_N 1 8
TBT_EE_DO 2 CS# VCC 7
TBT_EE_WP_N 3 DO(IO1) HOLD#(IO3) 6 TBT_EE_CLK
4 WP#(IO2) CLK 5 TBT_EE_DI
GND DI(IO0) 9
thermal pad
W25Q80DVZPIG_WSON8
TBT_PD@
A 1/21 A
Change to SA00003EW10
Same with ECL ROM.
2015/01/30
Compal Secret Data
2016/12/31 Title
NV(1/5)-PCIE
Custom
LA-C912P 0.1

5 4 3 2 1

5 4 3 2 1
+3.3V_TBT_SX +3VALW +3VS +3VS_TBT +3VALW +3VS_TBT_S0 +3VS_TBT_S0

+3VS_TBT
RT106 RT52 RT104 +3.3V_LC +3.3V_TBT_SX +3VS_TBT
1 2 1 2 1 2 LT4
@ @
1 2
0_0603_5% 0_0603_5% 0_0603_5%
0.1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
LQM18PN1R0MFHD_2P
47U_0603_6.3V6M
47U_0603_6.3V6M
1U_0201_6.3V6K
1 1 1 1 1 1 1 1
CT46 CT47 CT48 CT49 CT50 CT51 CT52 CT53 1 1 1
CT110 CT76 CT111
D
TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ D
2 2 2 2 2 2 2 2 TBT@ TBT@ TBT@
2 2 2
R13
+0.9V_DP
R6
H9
F8
UT1B
L8 A2
VCC3P3_LC
VCC3P3_S0
VCC3P3_SX
VCC3P3A
VCC0P9_DP VCC3P3_SVR
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
L11 A3
L12 VCC0P9_DP VCC3P3_SVR B3
1 1 1 1 1 1 1 VCC0P9_DP VCC3P3_SVR
l
CT54 CT57 CT58 CT59 CT60 CT61 CT62 M8
T11 VCC0P9_DP
TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ T12 VCC0P9_DP L9 +0.9V_SVR
2 2 2 2 2 2 2 VCC0P9_DP VCC0P9_SVR
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
L6 M9
VCC0P9_ANA_DPSRC VCC0P9_SVR
ia
M6 E12 1 1 1 1 1 1 1
V11 VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA E13 CT63 CT64 CT65 CT66 CT67 CT68 CT69
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11
+0.9V_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12 TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA F15
t
VCC0P9_PCIE VCC0P9_SVR_ANA
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
M15 J9
M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
1 1 1 1 VCC0P9_PCIE
CT55 CT70 CT71 CT72 L19 LT1 TBT@
N19 VCC0P9_ANA_PCIE_1 C1 +TBT_SVR_IND 1 2
VCC0P9_ANA_PCIE_1 SVR_IND
47U_0603_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
TBT@ TBT@ TBT@ TBT@ L18 C2 0.6UH_XFL4012-601MEC_20%
2 2 2 2 VCC0P9_ANA_PCIE_2 SVR_IND
+0.9V_USB
M18
N18 VCC0P9_ANA_PCIE_2 SVR_IND
D1 Change to SHI0000MD00 CT73
1
CT74
1
CT75
1
VCC
VCC0P9_ANA_PCIE_2
e
R15 A1 TBT@ TBT@ TBT@
1U_0201_6.3V6K VCC0P9_USB SVR_VSS 2 2 2
1U_0201_6.3V6K
R16 B1
+0.9V_CIO VCC0P9_USB SVR_VSS B2
1 1 SVR_VSS
CT77 CT56 R8
R9 VCC0P9_CIO
id
TBT@ TBT@ R11 VCC0P9_CIO
2 2 VCC0P9_CIO +0.9V_LVR_OUT
1U_0201_6.3V6K
1U_0201_6.3V6K
1U_0201_6.3V6K
R12 F18
VCC0P9_CIO VCC0P9_LVR
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6K
1U_0201_6.3V6K
1 1 1 H18
CT78 CT79 CT80 +3.3V_ANA_PCIE L16 VCC0P9_LVR J11
+3.3V_ANA_USB2 VCC3P3_ANA_PCIE VCC0P9_LVR 1 1 1 1
J16 H11 CT81 CT82 CT83 CT84
C TBT@ TBT@ TBT@ VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE C
f
2 2 2
1U_0201_6.3V6K
1U_0201_6.3V6K
A6 V5 TBT@ TBT@ TBT@ TBT@
A8 VSS_ANA VSS_ANA V6 2 2 2 2
1 1 VSS_ANA VSS_ANA
CT85 CT86 A10 V8
A12 VSS_ANA VSS_ANA V9
VSS_ANA VSS_ANA
n
TBT@ TBT@ A14 V15
2 2 A16 VSS_ANA VSS_ANA V16
A18 VSS_ANA VSS_ANA V20
A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
o
B6 VSS_ANA VSS_ANA W8
B16 VSS_ANA VSS_ANA Y9
C
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
L
GND
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
L
F9 VSS_ANA VSS_ANA AC16
VSS_ANA VSS_ANA
E
B F16 AC18 B
F20 VSS_ANA VSS_ANA AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
H12 VSS_ANA VSS E6
D
H13 VSS_ANA VSS F5
H15 VSS_ANA VSS F6
H16 VSS_ANA VSS H5
H20 VSS_ANA VSS H8
J5 VSS_ANA VSS J8
VSS_ANA VSS
r
J18 J12
J19 VSS_ANA VSS J13
J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
o
K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
F
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
N20 VSS_ANA VSS T18

N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
AR4C_FC-CSP337
P1
P2
R18
R19
R20
R22
R23
T20
R5
T1
T2
T5
U22
U23
A A
TBT@
2015/01/30
Compal Secret Data
2016/12/31 Title
NV(2/5)-IFP_ABCDEF_DAC_XTAL
Custom
LA-C912P 0.1

5 4 3 2 1

5 4 3 2 1
@EMI@
RT82 1 2 0_0402_5%~D
+3VALW_PD +3VALW +3VALW_PD MCM1012B900F06BP_4P
0_0603_5% TBT_A_USB20_PT 4 3 TBT_A_USB20_L_PT
1 @ 2
TBT_A_USB20_NT TBT_A_USB20_L_NT
1
RT53 1 2
RT103
0_0402_5% LT2 EMI@
+3VALW +3VS_TBT
UT3 @ RT83 1 2 0_0402_5%~D
@ @EMI@
2
2 1 1 7 +3VS_PD_R 1 @ 2 @EMI@
VIN VOUT 1
CT87 1U_0402_6.3V6K 2 8 RT54 0_0402_5% RT84 1 2 0_0402_5%~D
VIN VOUT CT88 +5VALW +5VALW_PD
3 6 0.1U_0402_10V6K MCM1012B900F06BP_4P
<20,43> PD_PWR_EN ON CT 2 TBT_A_USB20_NB TBT_A_USB20_L_NB
1 1 PD@ RT56 4 3
CT109 CT108 1 @ 2
1
+5VALW
4 4.7U_0402_6.3V6M 0.1U_0402_10V6K
RT55 VBIAS 5 @ PD@ 0_0805_5% TBT_A_USB20_PB 1 2 TBT_A_USB20_L_PB
100K_0402_5% CT89
1 GND 9 2 2 120mil 3A 120mil 3A
@ 1U_0402_6.3V6K GND LT3 EMI@
D D
@ RT85 1 2 0_0402_5%~D
2
2 APE8937GN2_DFN8_2X2 @EMI@
@
+5VALW_PD
120mil 3A
4.7U_0603_6.3V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1
CT90 CT91 CT92 CT93
+TBTA_VBUS
l
2 2 2 2
120mil 3A
+TBTA_VBUS +TBTA_VBUS
1
SMD Type
AZ4024-02S_SOT23-3
SDM10U45-7_SOD523-2
DT1 ESD@
DT15 ESD@
ia
+TBTA_LDO_BMC
3
CT107
+1.8VD_TBTA_LDO
1
+1.8VA_TBTA_LDO 1U_0402_6.3V6K
2
PD@
1 1 1 JUSBCx
A1 B12
CT98 CT99 CT100 GND GND
1
CT106 A2 B11
t
2.2U_0402_16V6K 2.2U_0402_16V6K 2.2U_0402_16V6K <58> USB3_A_TTX_C_DRX_P0 SSTXP1 SSRXP1 USB3_A_TRX_DTX_P0 <58>
2 2 2 1U_0402_6.3V6K A3 B10
PD@ PD@ PD@ +3VALW_PD <58> USB3_A_TTX_C_DRX_N0 SSTXN1 SSRXN1 USB3_A_TRX_DTX_N0 <58>
PD@
0.47U_0402_25V6K 2 1 CT94 A4 B9 CT96 1 2 0.47U_0402_25V6K
VBUS VBUS
1 1 TBTA_CC1 TBTA_SBU2
PD@ CT101 A5 B8
CC1 RFU2
n
+3VS 10U_0402_6.3V6M 0.6A TBT_A_USB20_L_PT A6 B7 TBT_A_USB20_L_NB
2 2 TBT_A_USB20_L_NT A7 DP1 DN2 B6 TBT_A_USB20_L_PB
DN1 DP2
Bottom
C11
D11
H10
A11
B11
A10
B10
TBTA_SBU1 A8 B5 TBTA_CC2
H1
A6
A7
A8
B7
B9
A9
A2
B1
K1
E1
UT4 RFU1 CC2
TOP
e
1
@ @ RT89 1 @ 2 0_0402_5% F1 0.47U_0402_25V6K 2 1 CT97 A9 B4 CT95 1 2 0.47U_0402_25V6K
PP_HV
PP_HV
PP_HV
PP_HV
SENSEN
LDO_1V8D
LDO_BMC
PP_CABLE
SENSEP
LDO_1V8A
PP_5V0
PP_5V0
PP_5V0
PP_5V0
HV_GATE1
HV_GATE2
VIN_3V3
VDDIO
RT107 RT57 RT58 I2C_ADDR VBUS VBUS
10K_0402_5% 10K_0402_5% 10K_0402_5% D1 +3.3V_TBT_SX_R +3.3V_TBT_SX A10 B3
<58> TBT_I2C_SDA I2C_SDA1 <58> USB3_A_TRX_DTX_N1 SSRXN2 SSTXN2 USB3_A_TTX_C_DRX_N1 <58>
<58> TBT_I2C_SCL
D2 <58> USB3_A_TRX_DTX_P1
A11 B2 USB3_A_TTX_C_DRX_P1 <58>
I2C_SCL1 RT61 SSRXP2 SSTXP2
<58> TBTA_I2C_INT
C1
2
PD_IRQ# I2C_IRQ1_N 1 2 A12 B1
id
GND GND
RT59 1 @ 2 0_0402_5% TBTA_I2C_SDA1 A5
<18,41,42,43,46> EC_SMB_DA2 TBTA_I2C_SCL1 I2C_SDA2 0_0402_5% +3.3V_FLASH
<18,41,42,43,46> EC_SMB_CK2 RT60 1 @ 2 0_0402_5% B5 H11 1 4
B6 I2C_SCL2 VBUS J10 @ GND GND 6
<43> PD_IRQ# I2C_IRQ2_N VBUS GND
PD_IRQ# PU at EC side J11 2 3
@ PAD~D T11 B2 VBUS K11 5 GND GND
C C
@ PAD~D T12 C2 GPIO0 VBUS GND
1
f
@ PAD~D T13 D10 GPIO1 JAE_DX07S024JJ2
GPIO2 1
@ PAD~D T14 G11 CT102 Conn@
C10 GPIO3 CT103
<58> TBTA_HPD GPIO4 1U_0402_6.3V6K
@ PAD~D T15 E10 H2 2
PD@ 10U_0603_10V6M
@ PAD~D T16 G10 GPIO5 VOUT_3V3 2
GPIO6 PD@
@ PAD~D T23 D7
n
@ PAD~D T22 H6 GPIO7
GPIO8 G1
RT76 1 @ 2 0_0402_5% PD_EE_CLK A3 LDO_3V3
<58> TBT_EE_CLK PD_EE_DI SPI_CLK
<58> TBT_EE_DI RT77 1 @ 2 0_0402_5% B4
RT86 1 @ 2 0_0402_5% PD_EE_DO A4 SPI_MOSI
<58> TBT_EE_DO PD_EE_CS_N SPI_MISO TBT_A_USB20_PT
<58> TBT_EE_CS_N RT88 1 @ 2 0_0402_5% B3 K6
o
SPI_SS_N C_USB_TP L6 TBT_A_USB20_NT
L5 C_USB_TN
<58> TBT_A_USB20_P USB_RP_P
<58> TBT_A_USB20_N
K5
USB_RP_N
RT62 2 PD@ 1 100K_0402_5% PD_UART E2 K7 TBT_A_USB20_PB
F2 UART_TX C_USB_BP L7 TBT_A_USB20_NB USB3_A_TTX_C_DRX_P0 DT2 1 ESD@ 2
UART_RX C_USB_BN
@ PAD~D T25 F4 +3.3V_FLASH ESD101-B1-02ELS_TSSLP-2-4-2
C
@ PAD~D T24 G4 SWD_DATA
SWD_CLK L9 TBTA_CC1 USB3_A_TTX_C_DRX_N0 DT3 1 ESD@ 2
C_CC1 L10 TBTA_CC2
C_CC2
1
ESD101-B1-02ELS_TSSLP-2-4-2
RT63 2 PD@ 1 100K_0402_5% TBTA_MRESET E11 RT66 RT67
MRESET USB3_A_TRX_DTX_P0 DT4 1 ESD@ 2
RPD_G1 10K_0402_5% 10K_0402_5%
K9 RT64 1 PD@ 2 10K_0402_5%
PD@ PD@
TBTA_LSTX L4 RPD_G1 K10 RPD_G2 RT65 1 PD@ 2 10K_0402_5% ESD101-B1-02ELS_TSSLP-2-4-2
<58> TBTA_LSTX
2
TBTA_LSRX K4 TBT_LSTX/R2P RPD_G2 TI's Requirement
<58> TBTA_LSRX TBT_LSRX/P2R USB3_A_TRX_DTX_N0 DT5 1 ESD@ 2
L
+3.3V_TBT_SX RT68 2 PD@ 1 100K_0402_5% TBTA_DIG_AUD_P L3 E4 DEBUG_CTL1 ESD101-B1-02ELS_TSSLP-2-4-2
RT69 2 PD@ 1 100K_0402_5% TBTA_DIG_AUD_N K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 DEBUG_CTL2
DIG_AUD_N/DEBUG4 DEBUG_CTL2 USB3_A_TTX_C_DRX_P1 DT6 1 ESD@ 2
1
RT70 RT71 2 PD@ 1 100K_0402_5% TBTA_DEBUG1 L2 ESD101-B1-02ELS_TSSLP-2-4-2

100K_0402_5% RT72 2 PD@ 1 100K_0402_5% TBTA_DEBUG2 K2 DEBUG1
DEBUG2 USB3_A_TTX_C_DRX_N1
L
TBT@ DT7 1 ESD@ 2
K8 TBTA_SBU1
2
J1 C_SBU1 ESD101-B1-02ELS_TSSLP-2-4-2
<58> TBT_A_AUX_P_C AUX_P TBTA_SBU2
<58> TBT_A_AUX_N_C
J2 L8
+3.3V_FLASH AUX_N C_SBU2 USB3_A_TRX_DTX_P1 DT8 1 ESD@ 2
1
0_0201_5%
B RT73 1 @ 2 BUSPOWER# F10 RT100 ESD101-B1-02ELS_TSSLP-2-4-2 B
RT74 0_0402_5% BUSPOWER_N F11 1 2
E
100K_0402_5% TBT_RESET_N <58> USB3_A_TRX_DTX_N1
RESET_N @ DT9 1 ESD@ 2
TBT@ TBTA_ROSC G2
2
R_OSC ESD101-B1-02ELS_TSSLP-2-4-2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DT10
1
TBT_A_USB20_L_PT 1 1 TBT_A_USB20_L_PT
10 9
RT75 PD@
A1
D6
E5
E6
E7
F5
H4
H5
B8
D8
E8
F6
F7
F8
H7
H8
L1
G5
G6
G7
G8
L11
TBT_A_USB20_L_NT 2 2 TBT_A_USB20_L_NT
2/12 Add for TBT debug. 15K_0402_0.1%
PD@
TPS65982_BGA96 9 8
TBT_A_USB20_L_NB TBT_A_USB20_L_NB
D
4 4 7 7
2
TBTA_CC1 DT11 1 ESD@ 2

TBTA_DIG_AUD_P TBTA_LSTX TBT_A_USB20_L_PB 5 TBT_A_USB20_L_PB
0_0402_5% 1 @ 2 RT94 1 5 6 6
ESD8011MUT5G X3DFN2 ESD
TBTA_DIG_AUD_N 0_0402_5% 1 @ 2 RT95 TBTA_LSRX CT104 3 3
TBTA_CC2 DT12 1 ESD@ 2
0.22U_0402_10V4Z
2 8
PD@
r
AZ1045-04F_DFN2510P10E-10-9 TBTA_SBU1 DT13 1 ESD@ 2
ESD@
o
TBTA_SBU2 DT14 1 ESD@ 2
+3.3V_FLASH +3.3V_FLASH
A
F 1
RT92 PD@
1
RT87 PD@
1
RT91 PD@
2
2
3.3K_0402_5%
PD_EE_DI
PD_EE_CLK
PD_EE_CS_N
PD_HOLD_N
3.3K_0402_5%
PD_EE_WP_N
3.3K_0402_5%
5
8
UT5
DI
CLK
CS
HOLD
WP
VCC
SO
VSS
W25Q80DVSSIG_SO8
PD@
2
4
PD_EE_DO
3.3K_0402_5%
1
PD@
2
RT93
1
2
CT105
0.1U_0402_10V7K
PD@

Title
NV(3/5)-POWER
Custom
LA-C912P 0.1

5 4 3 2 1

A B C D
EMI@ PL1
SMB3025500YA_2P
VIN
1 2 +3VALW
ADPIN EMI@ PL3
SMB3025500YA_2P
PJPDC1 @ 1 2
1
1000P_0402_50V7K
1000P_0402_50V7K
1 2
2.2K_0402_5%
100P_0402_50V8J
100P_0402_50V8J
2 3
1
3 4
2
EMI@ PC1
EMI@ PC2
EMI@ PC3
EMI@ PC4
4 5
2
5 6
PR3
6 7 PR4
7 8 33_0402_5%
1
8 9 1 3 PSID-3 1 2 PS_ID <43>
S
1
9 10 PQ7
1
10 11 FDV301N_G 1N SOT23-3
11
G
2
100K_0402_1%
ACES_50293-0117N-001
2
EMI@ PL2
PR8
PR6
BLM15HG601SN1D_2P
PSID 2 1 PSID-2 2 1
Adapter 240W
l
+5VALW
240W/19.5V=12.3A Adapter connector:
1
10K_0402_1%
1
1. X
C
2
ia
PSID-1 PQ2
2.AD P I N
15K_0402_1%
B MMST3904-7-F_SOT323~D
3.AD P I N
2
E PR2
3
4.AD P I N
PR9
@ 1K_0402_1%
5.AD P I N
1
BATT+ PD1 @ JRTC1 PD5
6.G N D SM24_SOT23 1 2 1 JRTC1 2
1
1
BATT++ 7.G N D 2
2 1
+RTC_CELL
BATT+
3
8.G N D
EMI@ PL4 3
+3VLP
n
SMB3025500YA_2P G1 4
1 2 9.G N D G2 BAS40CW_SOT323-3
10.PSI D
EMI@ PL5
11.X ACES_50271-00201-001
e
SMB3025500YA_2P
1 2 BATT++
100P_0402_50V8J
RTC
1
1
1000P_0402_50V7K
0.022U_0402_25V7K
id
0.01UF_0402_25V7K
1
PC7
EMI@ PC8
EMI@ PC9
EMI@ PC6
2
2
1
PQ3 6
EMI@
2
PD2 PD3 SI3457CDV-T1-GE3_TSOP6 5 2
f
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3 2
EMI@ EMI@ 4 1
D
B+ B+_BIAS
100K_0402_1%
0.1U_0402_25V6
0.22U_0603_25V7K
n
2
G
1
1
PR12
PC10
PC11
3
o
2
PBATT1
@
2
1
1
2 BATT_TEMP <43,61,62>
+5VALW PR13
2 3 100K_0402_1%
3 4 1 2 VSB_N_001
2
4 CLK_SMB 1
1VSB_N_003
5 2 PR16
C
5 6 DAT_SMB 1 PR19 2 100_0402_1% 10K_0402_1% PR14
6 7 BATT_PRS 1 PR21 2 100_0402_1% 1 2 100K_0402_1%
7 8 SYS_PRES PR22 100_0402_1% +3VALW
8 9 BAT_ALERT
1
9 10 @ PR17 D
10 11 1 2 VSB_N_002 2 PQ4
11 12 <63> POK L2N7002WT1G 1N SC-70-3
L
G
12 13 0_0402_5%
.1U_0402_16V7K
EC_SMB_CK1 <43,62> S
3
13
PC12
Battery 92W
ACES_51481-01371-P01 92W/12V=7.7A @
2
Battery connector:
L
EC_SMB_DA1 <43,62>
1.BATT++
2.BATT++
3.BATT++
4.BATT++ VIN
E
3
For PROCHOT CPU thermal protection 3
<43,62> ADP_I
5.CLK_SMB VCIN0_PH
6.DAT_SMB Erp lot 6 circuit
7.BATT_PRS <9,43,62> H_PROCHOT#
Trig = 1V
8.SYS_PRES
PR732
93 +/- 3 degree C
1
D
3.3K_0402_1%
9.BAT_ALERT 240W Recover = 2.28V +3VALW +3VLP
10.GN D
2
VCIN1_PH= 1.26V 50 +/- 3 degree C
11.GN D PR729
14.7K_0402_1%
12.1K_0402_1%
2
2
PC14 1M_0402_1%
12.GN D reset = 1.17V
3 2
r
PR24
PR25
1U_0603_25V6K
13.GN D
1
D
180W
PQ710B
1 2 2 PQ8 PR23
VCIN1_PH=0.97V
S TR 2N7002KDW 2N SOT-363-6
<43,61,62> BATT_TEMP G L2N7002WT1G 1N SC-70-3 <18,37,43,46,62>
110K_0402_1% ACIN @
1
o 1
5
100K_0402_1%
S reset = 0.88V
3
2
PR731
<43> VCIN0_PH
1
2
PR28
200K_0402_1%
4
PQ710A
1
1M_0402_1%
F 2
S TR 2N7002KDW 2N SOT-363-6
2 PR730
1
1
1
<43> VCIN1_PH
1
0.1U_0402_25V6 PH1
2
PC724 2 100K_0402_1%_TSM0B104F4251RZ
2
PR26 PC13 @
<43> ECAGND
100K_0402_1% .1U_0402_16V7K
1
1
4 4

PWR-DCIN / BATT CONN / OTP
A B C D

A B C D
PQ700
CC = 5.5A
1
D L2N7002WT1G 1N SC-70-3
2
VIN S PR701
G
PR700 CV = 17.7V
3
3M_0402_5% 1M_0402_1%
2 1 2 1
PQ707 P1 P2
MDU1512RH 1N POWERDFN56-8
1 Iada=0~12.3A(240W)
2
5 3 Iada=0~9.23A(180W)
1000P_0402_50V7K
PR726
1 2 ADP_I = 40*Iadapter*Rsense
4
PC722
4.7_0402_5%
1
1 2 PQ702 1
PQ701 MDU1512RH 1N POWERDFN56-8 PR702

B+ PQ703
MDU1512RH 1N POWERDFN56-8
MDU1512RH 1N POWERDFN56-8 1 0.005_1206_1% 1
1 2 2
2 3 5 1 4 5 3
PQ703_S
0.1U_0402_25V6
5 3
2 3
1 CSSN_1
1 CSSP_1
PC701
4
l
4
CHG_B+
2
EMI@ PL701
4.7_0402_5% PD700
0_0402_5%
0_0402_5%
1UH_6.6A_20%_5X5X3_M
PR725 2 1 2 PC725
ia
PC723 BATT++
PR703
PR704
1 2
10U_0805_25V6K
10U_0805_25V6K
2
1 2 1
2200P_0402_50V7K
1
PC705
PC706
PC702
0.1U_0402_25V6
0.022U_0603_25V7K
1
EMI@ PC703
3 0.047U_0402_25V7K
EMI@ PC704
VIN
2
1000P_0402_50V7K PC707 PC708 1 2 PR733 PR734
2
PC709
t
0.1U_0603_25V7K 0.1U_0402_25V6 10K_0402_1% 10_0402_1%
2
4.12K_0603_1%
1
4.12K_0603_1%
1
1 2 1 2 1 2 BAT54CW-7-F SOT-323
PR706
10_1206_1%
PR705
BATDRV_CHG 2
2
1
1
2.2_0603_5%
0.01UF_0402_25V7K
PR707
PR708
MDU1516URH_POWERDFN56-8-5
n
2
+3VALW
2
BATSRC_CHG
PC710
2.2U_0603_16V6K
REGN_CHG 1
PQ704
5
e
BTST_CHG
1 2
20K_0402_1%
1
DH_CHG
DL_CHG
LX_CHG
2
PC711 PR710
PR709
1U_0603_25V6K 4.99K_0402_1%
DH_CHG 4
id
1 2
PU700 PQ705
26
22
25
23
28
24
27
1
D
L2N7002WT1G 1N SC-70-3
2TB_STAT#_CHG
HIDRV
LODRV
GND
PHASE
BTST
REGN
VCC
G PR712
3
2
1
29 PL700 0.01_1206_1%
CSSP_2
CSSN_2
2 S 2
3
PWPD
f
5.6UH_PCMB104T-5R6MS_8A_20%
PR711 LX_CHG 1 2 1 4
BATT+
1 21 1 2
ACN ILIM 2 3
1
2K_0402_1% PQ706
5
2 20 PR713
CSON_1
CSOP_1
MDV1525URH_PDFN33-8-5
ACP SRP 4.7_1206_5%
EMI@
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
CMSRC_CHG 3 19
2
CMSRC SRN
1
SNUB_CHG
PC712
PC713
PC714
o
DL_CHG 4
1
ACDRV_CHG 4 18 BATDRV_CHG PC715
2
ACDRV BQ24780SRUYR_QFN28_4X4 BATDRV 680P_0402_50V7K
EMI@
2
5 17 BATSRC_CHG
<18,37,43,46,61> ACIN
3
2
1
ACOK BATSRC
PR714
C
REGN_CHG 1 2 ACDET_CHG 6 16 TB_STAT#_CHG
120K_0402_5%
VIN ACDET TB_STAT#

324K_0402_1%
100K_0402_1%
1
PC716 PC717 PC721

1
PR715
1 2 7 15 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6

IADP BATPRES#
1
<43,61> ADP_I
PR716
1 2 1 2 1 2
PROCHOT#
PR717 @ PR718
CMPOUT
0_0402_5% PR727
0_0402_5%
100P_0402_50V8J
10K_0402_1%
IDCHG
CMPIN
2
2
PMON
SDA
L
2
SCL
2
AC Det
PC718
PR722
2
10_0402_1%
Max:18.16V 1 2
Typ :17.98V
1
10
11
12
13
14
1
Min :17.8V +3VALW PR723
1
10_0402_1%
L
1
PR719
1 2 1 2
49.9K_0402_1%
@
PC719
0_0402_5% PR720
0_0402_5% PR721
0.01UF_0402_25V7K PC720
2
2
100P_0402_50V8J
2
0_0402_5% PR724
<43,61> BATT_TEMP
E
3
ADPI = 0.005*40*IADP = 0.2 * IADP 3
2
0_0402_5%
1
PR728
Adapter = 240W @ @
CP = 240W/19.5V*0.9 = 11.07A @
1
@
ADPI = 2.21V
D
Hybrid trigger = CP*107% = 11.85A
ADPI = 2.37V
<43,61>
<43,61>
EC_SMB_DA1
EC_SMB_CK1
IPCC= 240W/19.5V*0.95 = 11.69A

<71>
<9,43,61>
I_SYS
H_PROCHOT#
r
ADPI = 2.32V
IPCC(hybrid mode)= 240W/19.5V = 12.3A
ADPI = 2.46V
o
PROCHOT = 240W/19.5V+1 = 13.3A
ADPI = 2.66V
Adapter = 180W
F
CP = 180W/19.5V*0.9 = 8.30A
APDI = 1.66V
Hybrid trigger = CP*107% = 8.88A
ADPI = 1.77V
IPCC = 180W/19.5V*(1*0.95) = 8.77A
ADPI = 1.75V
IPCC(hybrid mode)= 180W/19.5V = 9.23A
ADPI = 1.85V
PROCHOT = 180W/19.5V+1 = 10.23A
4
ADPI = 2.04V 4

P62-PWR_CHARGER
A B C D

A B C D E
Input Current: 7.5A

3.3V*10A/0.85/12V=2.23
5V*10A/0.85/12V=5.27
+3VLP
PC101
4.7U_0603_6.3V6K
1 2
1 1
Output capacitor ESR need follow
below equation to make sure feed back
loop stability
ESR=20mV*L*fsw/2V
PR101 PR102
8.06K_0402_1% 15.4K_0402_1%
l
1 2 1 2
VFB=2V VFB=2V
ia
PR103 PR104
11.8K_0402_1% 10.2K_0402_1%
1 2 1 2
1
3/5V_B+
PR105 PR106
n
32.4K_0402_1% 33.2K_0402_1%
EMI@ PL100 POK need pull high, it
1UH_6.6A_20%_5X5X3_M
B+ will pull high on VS
2
3/5V_B+
10U_0805_25V6K
10U_0805_25V6K
1 2
e
transfer circuit
1
PC114
PC102
FB_3V
FB_5V
2200P_0402_50V7K
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
CS2
CS1
id
2
1
5
PC104
EMI@ PC100
EMI@ PC103
PC113
5
PQ100
<61> POK
2
2
3
5
1
PU100
2 2
VFB2
VFB1
CS2
VREG3
CS1
f
PQ102
4 21
3V_EN 6 PAD
EN2 20 5V_EN 4
EN1 @ PR107
n
7 200_0402_1%
DCR = 18mohm
1
2
3
PGOOD 19 1 2
VCLK
DCR = 6mohm
3
2
1
PL101 LX_3V 8 TPS51225CRUKR_QFN20_3X3
SW2 LX_5V
o
PC105 PR108 18 PL102
1 2 LX_3V 0.1U_0402_25V6 0_0603_5% SW1 PR109 PC106 2.2UH_PCMB104T-2R2MS_12A_20%
+3VALWP 1 2 1 2 BST_3V 9 0_0603_5% LX_5V 1 2
VBST2 BST_5V +5VALWP
S COIL 2.2UH +-20% 7.8A 7X7X3 17 1 2 1 2
MDU1511RH_POWERDFN56-8-5
VBST1
220U_D2_6.3VY_R15M
220U_D2_6.3VY_R15M
MDU1511RH_POWERDFN56-8-5
1 1
1
5
UG_3V
4.7_1206_5%
680P_0603_50V8J 4.7_1206_5%
10
C
DRVH2
1
UG_5V
EMI@ PR110
EMI@ PR111
PC108
PC115
16 + +
VREG5
DRVL2
DRVL1
DRVH1
PQ101
0.1U_0402_25V6
ESR = 18mohm
VO1
PQ103
VIN
2 2
1
2
4 4
2
11
12
13
14
15
+ PC107
LG_3V LG_5V
680P_0603_50V8J
220U_6.3V_M
L
1
1
2
EMI@ PC109
EMI@ PC110
1
2
3
3
2
1
ESR = 15mohm
+5VALWP
2
2
3/5V_B+
3.3VALWP
L
TDC=10.01A VL
Peak Current 14.31A
1
3
OCP current 17.17A PC111
3
5VALWP
E
4.7U_0603_6.3V6K
FSW=355kHz
2
TYP MAX OVP=Vout*(112.5%~117.5%) TDC=10.77A (8.77A+2A)
H/S Rds(on) : 11.5mohm 14mohm Peak Current 15.38A
L/S Rds(on) : 2.7mohm 3.3mohm OCP=Vtrip/Rdson+Iripple/2 OCP current 18.45A
D
Vtrip=Ics(min)*Rcs/8+1mV FSW=300kHz
Vcs=Ics*vcs should be in the range of 0.2~2V TYP MAX
EN
Rising=1.6~0.3V H/S Rds(on) : 11.5mohm 14mohm
L/S Rds(on) : 2.7mohm 3.3mohm
r
Vout=VFB*(1+Rtop/Rbot)
PR100 0_0402_5% VFB=2V
3V_EN 1 2
4
<43> EC_ON
<35> USBCHG_DET_D
<43> VCOUT0_PH#
2
3
PD100
BAS40CW_SOT323-3
@ PD101
1
5V_EN
@ PR115
PR113
2.2K_0402_5%
2
PR114F 2
1
0_0402_5%
PR112
o 2
0_0402_5%
+5VALWP 1
1
1
1
PJP100
PJP101
2
JUMP_43X118
2
JUMP_43X118 @
2
2
@
+5VALW +3VALWP 1
1
PJP102
JUMP_43X118
2
2
@
+3VALW
LL4148_LL34-2 1M_0402_1%
2 1 1 2
VIN
200K_0402_1%
4.7U_0603_6.3V6K
1
PR116
PC112

2
PWR-3.3VALWP/5VALWP
2
A B C D E

5 4 3 2 1
Input Current: 1A
1.2V*8.88A/0.85/12V=1
D D
Pin19 need pull separate from +1.2VP.

If you have +1.2V and +0.6V sequence question,
ia l 0.6VSP
t
you can change from +1.2VP to +1.2VS. TDC 1.05A
PJP203@
B+ 1 2 1.2V_B+ PR200 Peak Current 1.5A
1 2 2.2_0603_5%
2200P_0402_50V7K
0.1U_0402_25V6
n
JUMP_43X39 BST_1.2V 1 2 BOOT_1.2V
10U_0805_25V6K
10U_0805_25V6K
+1.2VP
1
1
EMI@ PC201
@EMI@ PC200
PC202
PC203
e
2
2
DH_1.2V +0.6VSP
id
SW_1.2V
10U_0805_6.3V6K
10U_0805_6.3V6K
1
1
PC204
PC205
PC206
5
MDV1528URH 1N PDFN33-8
0.1U_0603_25V7K
17
19
20
16
18
2
PQ200
C PU200 C
2
UGATE
VLDOIN
VTT
PHASE
BOOT
21
PAD
4 DL_1.2V 15 1
n
LGATE VTTGND
14 2
PGND VTTSNS
o
PL201 PR201
1
2
3
1UH_11A_20%_7X7X3_M 21K_0402_1%
1 2 1 2 CS_1.2V 13 3
+1.2VP PC207 CS RT8207MZQW_WQFN20_3X3 GND
1
1U_0603_10V6K
5
VTTREF_1.2V
C
1 2 12 4
220U_B2_2.5VM_R15M
220U_B2_2.5VM_R15M
VDDP VTTREF
MDV1526URH 1N PDFN33-8
PQ201
1 1 @EMI@ PR202 PR203

4.7_1206_5% 5.1_0603_5%
+ + 1 2 VDD_1.2V 11 5
PC209
PC215
1 2
+5VALW VDD VDDQ +1.2VP
1
PGOOD
4 PC210
2.2_0603_5%
TON
1
2
2 2 @EMI@ PC211 0.033U_0402_16V7K
1.2VP
FB
S5
S3
L
2
PR204
680P_0402_50V7K PC212
TDC=8.88A (7.41+1.47)
2
1U_0603_10V6K
10
6
Ipeak=12.68A
1
2
3
OCP=15.21A
1
L
Switching Frequency: 285kHz
FB_1.2V
EN_0.6VSP
PR205
EN_1.2V
@ 12K_0402_1%
PR210
TON_1.2V
1 2 +1.2VP
1 2
+3VALW
E
B PR206 B
OVP: 110%~120%
100K_0402_1% 887K_0402_1%
VFB=0.75V, Vout=1.2V
1
1.2V_B+ 1 2
TYP MAX
H/S Rds(on) : 23.2mohm 27.8mohm PR207
@ PR208 20K_0402_1%
D
L/S Rds(on) : 13.7mohm 16.4mohm 1 2
<43,45> SYSON
2
@ PJP201
0_0402_5% 1 2
1
@ PC213 1 2
Mode Level +0.6VSP VTTREF_1.2V
r
0.1U_0402_10V7K JUMP_43X118
S5 L off off @ PJP200
2
S3 L off on +1.2VP 1 2 +1.2V_DDR
1 2
S0 H on on
o
@ PR209 JUMP_43X118
0_0402_5%
Note: S3 - sleep ; S5 - power off 1 2
<43,45,58,74> SUSP#
F
@ PR211
1 2
<9> SM_PG_CTRL
0_0402_5%
1
@ PC214
0.1U_0402_10V7K
2
PJP202 @
1 2
+0.6VSP 1 2 +0.6VS
JUMP_43X39
A A

PWR-1.2VP/0.6VSP
5 4 3 2 1

A B C D
1 1
ia l
+2.5V_MEMP
1
@ PJP1300
1 2
2
+2.5V_MEM
n t
e
JUMP_43X79
+3VALW PR1301
0_0402_5%
id
+2.5VSP_ON 1 2 PM_SLP_S4# <18,43,45>
PC1301
0.1U_0402_16V7K
1
2 @ PR1300 2
1
f
100K_0402_1% PR1302
@ 1M_0402_1%
Note:Iload(max)=2.5A
2
n
2
PU1300
9
1 PGND 8
FB SGND
o
@ PJP1301 2 7 PL1300
PG EN 1UH_2.8A_30%_4X4X2_F
+5VALW 1 2 3 6 LX_2.5V 1 2
1 2 IN LX +2.5V_MEMP
4 5
68P_0402_50V8J
C
1
JUMP_43X79 PGND NC
1
@EMI@PR1303
4.7_0603_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
1
PC1306
PC1300
PC1302
PR1304
1
SY8003DFC_DFN8_2X2
Rup
22U_0603_6.3V6M
22U_0603_6.3V6M
36.5K_0402_1%
2
PC1304
PC1303
2
2
2
2
FB_2.5V
L
1
1
FB=0.6V
@EMI@PC1305
680P_0402_50V7K
L
Note:Iload(max)=3A PR1305
11.5K_0402_1%
Rdown
2
+2.5V_MEM
2
TDC 0.63A
E
3 3
Peak Current 0.9A

OCP Current 3.5A
Note:
D
When design Vin=5V, please stuff snubber
to prevent Vin damage
r
Vout=0.6V* (1+Rup/Rdown)
4
F o 4

PWR_+2.5V_MEM
A B C D

5 4 3 2 1
PJP301 @
+1VALWP_B+ 1 2
1 2 B+
JUMP_43X39
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0402_25V6
1
1
@EMI@ PC301
EMI@ PC302
PC303
PC304
+3VS
2
@
Input Current: 0.9A
5
1
1V*9.41A/0.85/12V=0.9
PR301
D 100K_0402_1% D
PQ300
<43> +1VALWP_PGOOD
4
2
PR302 PC305
PU300 2.2_0603_5% 0.1U_0603_25V7K
PR303 1 10 BST_+1VALWP 1 2 1 2
3
2
1
86.6K_0402_1% PGOOD VBST
PR300 1 2 TRIP_+1VALWP 2 9 UG_+1VALWP PL300
0_0402_5% TRIP DRVH 1UH_11A_20%_7X7X3_M
ia
1 2 EN_+1VALWP 3 8 SW_+1VALWP 1 2
<43,45> PCH_PWR_EN
FB_+1VALWP 4
EN SW +1VALWP
7
VFB V5IN +5VALW
1
0.1U_0402_16V7K
t
RF_+1VALWP 5 6 LG_+1VALWP
220U_B2_2.5VM_R15M
220U_B2_2.5VM_R15M
TST DRVL
1
@ PC300
PR305 @EMI@ 1 1
1
11 4.7_1206_5%
TP +1VALW
1
+ +
PQ301
PC307
PC306
2
2
PR306 TPS51212DSCR_SON10_3X3 PC308
1U_0603_6.3V6M
4 TDC 9.41A
470K_0402_1%
Peak Current 13.45A
1
PC309 @EMI@ 2 2
2
e
680P_0402_50V7K OCP current 16.14A
FSW=290kHz
3
2
1
2
id
Switching Frequency: 290kHz
C PR307 C
f
4.42K_0402_1%
OVP: 120%-130%
1 2 VFB=0.7V
TYP MAX
n
H/S Rds(on) : 11.5mohm 14mohm
1
L/S Rds(on) : 5.7mohm 6.8mohm

PR308
o
10K_0402_1%
2
L C +1VALWP 1
@ PJP300
1
JUMP_43X118
1
2
@ PJP302
1
JUMP_43X118
2
2
2
+1VALW
E L B
r D
A
F o A

PWR-1.05VSP
5 4 3 2 1

5 4 3 2 1
PC806
D 22U_0603_6.3V6M D
1 2
PC800
22U_0603_6.3V6M
l
1 2 PL800
Output Voltage = 1.07V for HW
ia
PJ800 @
+5VALW 1 2 4 3 LX_1.05VS_VGAP 1 2
1 2 IN LX +1.05VS_VGAP
JUMP_43X39 5 2 1UH_MAMK2520T1R0M_3.1A_20%
68P_0402_50V8J
PG GND +1.05VS_VGAP
1
6 1 TDC 2A
PC803
22U_0603_6.3V6M
22U_0603_6.3V6M
FB EN
1
PC804
PC805
@EMI@ PR803
4.7_0603_5% Peak Current 2.9A
2
@ PR801 PR804 OCP current 3.5A
2
0_0402_5% 11.8K_0402_1%
FSW=1MHz
2
1 2 EN_1.05VS_VGAP
<46,68> GPU_PGOOD
2
SNB_1.05VS_VGAP
e
PU800
Rup
0.1U_0402_16V7K
1
PC801
SY8032ABC_SOT23-6
1
PR802 FB_1.05VS_VGAP
id
1M_0402_1%
1
@
2
@EMI@ PC802
C 680P_0402_50V7K PR805 C
f
2
15K_0402_1%
Rdown
2
n
Note: PJ801 @
When design Vin=5V, please stuff snubber
o
+1.05VS_VGAP 1 2 +1.05VS_VGA
to prevent Vin damage 1 2
Vout=0.6V* (1+Rup/Rdown) JUMP_43X79
L C
B
E L B
r D
A
F o A

TH

Schematic - Aap21 La-C921p Rev 1.0 A00

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Schematic - Aap21 La-C921p Rev 1.0 A00

Uploaded by

Copyright:

Available Formats

For DELL Confidential

PCB 18F LA-B752P REV0 M/B 8

PCB 18F LA-B752P REV0 M/B 8

Issued Date 2015/01/30 Deciphered Date 2016/12/31 Title

For DELL Confidential

SKL+NV Block Diagram

DP 1.2 (DDI1) KXCNL-1010

Caldera USB3.0 port5 USB2.0 port4

Page30 PCI-E port5 USB2.0 port7

ENE KC3810 Page43

For DELL Confidential

Security Classification Compal Secret Data Compal Electronics, Inc.

For DELL Confidential

Port5 Touch screen

Right side 2 Left side 2

NV AMD PCI EXPRESS

CLOCK SIGNAL Lane 5 PCIE 4x MUX

CLKOUT_PCIE4 dGPU (N16) SATA2 NGFF SSD

CLKOUT_PCIE5 DGPU (Caldera) SATA3

: means Digital Ground

: means Analog Ground

For DELL Confidential

AW44 PCH_SMBCLK 253 DIMMA SMBUS Address [A0]

For DELL Confidential

Security Classification Compal Secret Data Compal Electronics, Inc.

For DELL Confidential

E25 B25 PEG_GTX_HRX_P[0..7] <46>

PEG Lane Reversed

Security Classification Compal Secret Data Compal Electronics, Inc.

For DELL Confidential

DDR CHANNEL A 2 121_0402_1% DDR_RCOMP0 G1

Security Classification Compal Secret Data

For DELL Confidential

CFG Straps for Processor

@ PAD~D T47 H24 RSVD BJ16 T73 PAD~D @

@ PAD~D T57 F30 BJ34 T81 PAD~D @

@ PAD~D T59 B30

Security Classification Compal Secret Data Compal Electronics, Inc.

For DELL Confidential

N37 V14 AY13

Security Classification Compal Secret Data

For DELL Confidential

+VCCIO +VCCSTG +VCCST

Size Document Number

Date: Wednesday, July 22, 2015 Sheet 11 of 78

For DELL Confidential

For DELL Confidential

Security Classification Compal Secret Data Compal Electronics, Inc.

For DELL Confidential

220U_D7_2VM_R6M 131 132

RD35 193 DQ44 VSS65 194 DDR_A_D45

DDR_A_D43 203 VSS69 VSS70 204 DDR_A_D47

DDR_A_D48 211 VSS73 VSS74 212 DDR_A_D50

RD28 RD29 RD30 213 214

DDR_A_DQS6 221 DQS6_c DM6_n/DBI6_n 222

DDR_A_D58 245 VSS89 VSS90 246 DDR_A_D59

255 SCL SDA 256 DIMM_CHA_SA0

Security Classification Compal Secret Data Compal Electronics, Inc.

For DELL Confidential

220U_D7_2VM_R6M 145 146

DDR_B_D43 207 208 DDR_B_D46

217 DQ49 DQ48 218

DDR_B_D50 225 VSS80 DQ54 226