TDA7449

Digital tone control audio processor

Datasheet - production data

Description
The TDA7449 is a volume tone (bass and treble)
balance (left/right) processor for quality audio
SO20
applications in TV systems. Selectable input gain
s )
is provided. A serial bus controls all functions.
The AC signal setting is obtained by resistor c t(
Features networks and switches combined with operational
d u
 Input multiplexer
amplifiers.
r o
– Two stereo inputs

e P
Bipolar/CMOS technology used allows obtaining
low distortion, low noise and DC stepping.
– Selectable input gain for optimal adaptation
to different sources
le t Table 1. Device summary
 One stereo output
 Treble and bass control in 2.0 db steps
b so
Order code
TDA7449D13TR
Package
SO20
Packing
Tape and reel
 Volume control in 1.0 db steps
- O
 Two speaker attenuators:
s )
t(
– Two independent speaker controls in
1.0 db steps to facilitate balance
– Independent mute function
u c
o d
 All functions are programmable via serial bus

P r Figure 1. Block diagram

t e
le
MUXOUTL TREBLE(L) BIN(L) BOUT(L)
10 16 15 14

so
8 RB
L-IN1

Ob
100K

9
L-IN2 SPKR ATT 5
G VOLUME TREBLE BASS LOUT
100K LEFT

19
0/30dB SCL
7 2dB STEP I2CBUS DECODER + LATCHES 20
R-IN1 SDA
18
100K DIG_GND

6
R-IN2 SPKR ATT 4
G VOLUME TREBLE BASS ROUT
100K RIGHT

VREF

2
VS
SUPPLY 3
INPUT MULTIPLEXER RB AGND
+ GAIN

11 17 12 13 1
MUXOUTR TREBLE(R) BIN(R) BOUT(R) CREF D98AU847A

September 2014 DocID006317 Rev 5 1/21

This is information on a product in full production. www.st.com
 Contents TDA7449

Contents

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics and test circuit . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Application recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Bass, stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 )
Treble stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
s
3.3 t(
CREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
c
d u
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
r o
4.1
P
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
e
4.2
4.3 le t
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
s o
4.4
4.5 O b
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

) -
5
( s
Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
t
5.1 c
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
u
o d
6
6.1 P r
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
No incremental bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

e te
o l 6.2 Incremental bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7
b s Data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
O8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/21 DocID006317 Rev 5

TDA7449 Overview

1 Overview

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

VS Operating supply voltage 10.5 V

Tamb Operating ambient temperature 0 to 70 C
Tstg Storage temperature range -55 to 150 C

Figure 2. Pin connections

s )
CREF 1 20 SDA

c t(
PGND
VS 2
3
19
18
SCL
DIG_GND
d u
ROUT 4 17 TREBLE(R)
r o
LOUT 5 16 TREBLE(L)

e P
R_IN2
R_IN1
6
7
15

le
14 tBIN(L)
BOUT(L)
L_IN1 8
s o 13 BOUT(R)
L_IN2 9
b 12 BIN(R)

-O
MUXOUT(L) 10 11 MUXOUT(R)

)
D98AU848

( s
ct
Table 3. Thermal data

du
Symbol Parameter Value Unit

ro
Rth j-pin Thermal resistance junction pins 85 °C/W

e P Table 4. Quick reference data

ol et
Symbol Parameter Min. Typ. Max. Unit

bs
VS Supply voltage 6 9 10.2 V
VCL Max input signal handling 2 VRMS
O THD Total harmonic distortion V = 0.1 Vrms f = 1 kHz 0.01 0.1 %
S/N Signal-to-noise ratio Vout = 1 Vrms (mode = OFF) 106 dB
SC Channel separation f = 1 KHz 90 dB
Input gain (2 dB step) 0 30 dB
Volume control (1 dB step) -47 0 dB
Treble control (2 dB step) -14 14 dB
Bass control (2 dB step) -14 14 dB
Balance control 1 dB step -79 0 dB
Mute attenuation 100 dB

DocID006317 Rev 5 3/21

21
 Electrical characteristics and test circuit TDA7449

2 Electrical characteristics and test circuit

Table 5. Electrical characteristics (refer to the test circuit Tamb = 25 °C, VS = 9 V,

RL= 10 k, RG = 600 , all controls flat (G = 0 dB), unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit

Supply

VS Supply voltage 6 9 10.2 V

IS Supply current 7 mA
SVR Ripple rejection 60 90
s )
dB

Input stage
c t(
RIN Input resistance 100
d u k
VCL Clipping level THD = 0.3%
The selected input is
P
2
ro2.5 Vrms

SIN Input separation grounded through a 2.2 μ

capacitor
et e 80 100 dB

Ginmin Minimum input gain

o l -1 0 1 dB

s
Ob
Ginman Maximum input gain 30 dB
Gstep Step resolution 2 dB

Volume control
) -
CRANGE Control range

ct(s 45 47 49 dB

du
AVMAX Max. attenuation 45 47 49 dB
ASTEP Step resolution 0.5 1 1.5 dB

r o AV = 0 to -24 dB -1.0 0 1.0 dB

EA

e P
Attenuation set error
AV = -24 to -47 dB -1.5 0 1.5 dB

e t AV = 0 to -24 dB 0 1 dB

s ol
ET Tracking error
AV = -24 to -47 dB 0 2 dB

O b VDC DC step
adjacent attenuation steps
from 0 dB to AV max 0.5
0 3 mV
mV
Amute Mute attenuation 80 100 dB

Bass control (1)

Gb Control range Max. boost/cut +12.0 +14.0 +16.0 dB

BSTEP Step resolution 1 2 3 dB
RB Internal feedback resistance 18.75 25 31.25 K

Treble control (1)

Gt Control range Max. boost/cut +13.0 +14.0 +15.0 dB

TSTEP Step resolution 1 2 3 dB

4/21 DocID006317 Rev 5

TDA7449 Electrical characteristics and test circuit

Table 5. Electrical characteristics (refer to the test circuit Tamb = 25 °C, VS = 9 V,

RL= 10 k, RG = 600 , all controls flat (G = 0 dB), unless otherwise specified) (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit

Speaker attenuators

CRANGE Control range 76 dB

SSTEP Step resolution 0.5 1 1.5 dB
AV = 0 to -20 dB -1.5 0 1.5 dB
EA Attenuation set error
AV = -20 to -56 dB -2 0 2 dB
VDC DC Step adjacent attenuation steps 0 3 mV

s )
t(
Amute Mute attenuation 80 100 dB

Audio outputs
u c
VCLIP Clipping level d = 0.3% 2.1
o d
2.6 VRMS
RL
RO
Output load resistance
Output impedance P
2
10
r 40 70
k
W
VDC DC voltage level
e t e 3.8 V

General
o l
b s
All gains = 0dB;
ENO Output noise
O
BW = 20Hz to 20KHz flat
-
5 15 μV

Et Total tracking error

( s ) AV = 0 to -24dB
AV = -24 to -47dB
0
0
1
2
dB
dB
S/N Signal-to-Noise ratio
u ct All gains 0dB; VO = 1VRMS ; 106 dB
SC
o d
Channel separation left/right 80 100 dB

Pr
d Distortion AV = 0; VI = 1VRMS ; 0.01 0.08 %

Bus input
t e
VIL
le Input low voltage 1 V

so VIH Input high voltage 3 V

Ob
IIN Input current VIN = 0.4 V -5 5 μA
Output voltage SDA
VO IO = 1.6 mA 0.4 0.8 V
acknowledge

Note: 1. The device is functionally good at Vs = 5 V. A step down on Vs to 4 V doesn’t reset the
device.
2. Bass and treble response: the center frequency and the response quality can be chosen
by the external circuitry.

DocID006317 Rev 5 5/21

21
Electrical characteristics and test circuit TDA7449

Figure 3. Test circuit

R2 2K
C9
5.6nF 150nF 330nF

J5
C7 C8
J8
IN1L MUXOUTL TREBLE(L) BIN(L) BOUT(L) OUT_R
J3 10 16 15 14
J9
RCA GND OUT_L
1 RB
IN1L L-IN1 8
2 1
GND OUT_L
J4 3 C3 0.47μF 100K 2
IN2L 5 J10
4 3
GND L-IN2 9 LOUT OUT_ R
5 SPKR ATT 4
G VOLUME TREBLE BASS
CON3 C4 0.47μF 100K LEFT CON4

IN1R +9 V
JP1
J2 JUMPER
1
RCA 18 DIG_GND
0/30dB 2
2dB STEP I2CBUS DECODER + LATCHES 19 SCL J6
3

)
20 SDA
4

J1
1
2
IN2R
GND
IN1R
R-IN2

C1 0.47μF
6

100K
G VOLUME TREBLE BASS
SPKR ATT 4
s
CON4

t(
c
3 RIGHT ROUT
GND R-IN1 7

u
4 VREF
CON C2 0.47μF 100K

d
C13 C12
3 R3 30
100nF 22μF

ro
SUPPLY 2 AGND
INPUT MULTIPLEXER RB 1
+ GAIN VS +V8 J7
2

P
GND
MOUTL 11 17 12 13 1 +9V CON2
1
GND MUXOUTR TREBLE(R) BOUT(R) CREF

BIN(R)
2

e
J5 MOUTR C5 C6

et
3
GND
4
C10 150nF 330nF C11

ol
CON4 5.6nF R1 2K 10μF
D98AU849A

b s
- O
(s )
c t
d u
r o
e P
o l et
s
Ob

6/21 DocID006317 Rev 5

TDA7449 Application recommendations

3 Application recommendations

The first and the last stages are volume control blocks. The control range is 0 to -47 dB
(mute) for the first one and 0 to -79 dB (mute) for the last one. Both of them have 1 dB step
resolution. The very high resolution allows the implementation of systems free from any
noisy acoustical effect. The TDA7449 audio processor provides dual-band tone control.
Typical responses are shown in Figure 5 through 9.

3.1 Bass stage

The bass cell has an internal resistor Ri = 25 k typical. Several filter types can be
s )
implemented, connecting external components to the bass IN and OUT pins. Figure 4 refers
to a basic T-type bandpass filter. The filter component values R1 internal FC, the gain AV at
ct(
max. boost and the filter Q factor are calculated as given below.
d u
Figure 4. T bandpass filter
r o
Ri internal

e P
IN
C1
OUT
C2

le t
s o R2

O b D95AU313

- 1
F C = -----------------------------------------------------------------
) 2    R1  R2  C1  C2

t ( s
u c R2C2 + R2C1 + RiC1
A V = ------------------------------------------------------------

o d R2C1 + R2C2

P r R1  R2  C1  C2
Q = -------------------------------------------------
R2C1 + R2C2

e te
o l Once the FC, AV, and Ri internal values are fixed, the external component values will be:

bs
AV – 1 2
Q  C1
C1 = -----------------------------------------
- C2 = ------------------------------
2    Fc  Ri  Q AV – 1 – Q
2

O AV – 1 – Q
2
R2 = ---------------------------------------------------------------------
-
2    C1  Fc   A V – 1   Q

3.2 Treble stage

The treble stage is a high-pass filter whose time constant is fixed by an internal resistor
(25 k typical) and an external capacitor connected between the treble pins and ground.

3.3 CREF
The recommended 10 μF reference capacitor (CREF) value can be reduced to 4.7 μF if the
application requires faster power ON.

DocID006317 Rev 5 7/21

21
 Application recommendations TDA7449

Figure 5. THD vs. frequency Figure 6. Bass response

s )
c t(
d u
Figure 7. THD vs. RLOAD
o
Figure 8. Treble response
r
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e te
Figure 9. Channel separation vs. frequency

o l
b s
O

8/21 DocID006317 Rev 5

 TDA7449 I2C bus interface

4 I2C bus interface

Data transmission from the microprocessor to the TDA7449 and vice versa takes place
through the 2-wire I2C bus interface, consisting of the two lines SDA and SCL (pull-up
resistors to the positive supply voltage must be connected).

4.1 Data validity

As shown in Figure 10, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
s )
c t(
4.2 Start and stop conditions
d u
r o
As shown in Figure 11, a start condition is a HIGH-to-LOW transition of the SDA line while

HIGH.
e P
SCL is HIGH. The stop condition is a LOW-to-HIGH transition of the SDA line while SCL is

le t
4.3 Byte format
s o
O b
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by

-
an acknowledge bit. The MSB is transferred first.
)
4.4 Acknowledge t ( s
u c
d
The master (μP) puts a resistive HIGH level on the SDA line during the acknowledge clock
o
P r
pulse (see Figure 12). The peripheral (audio processor) that acknowledges has to pull down
(LOW) the SDA line during this clock pulse.

te
The audio processor which has been addressed has to generate an acknowledge after the

e
reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth

o l clock pulse time. In this case the master transmitter can generate the STOP information in

b s order to abort the transfer.

O4.5 Transmission without acknowledge

Instead of detecting the acknowledge from the audio processor, the μP can use a simpler
transmission which is to simply wait one clock pulse without checking the slave
acknowledge and send the new data.
This is of course a riskier approach.

DocID006317 Rev 5 9/21

21
 I2C bus interface TDA7449

Figure 10. Data validity on the I2C bus

SDA

SCL

DATA LINE CHANGE

STABLE, DATA DATA
VALID ALLOWED D99AU1031

Figure 11. Timing diagram of I2C bus

s )
t(
SCL

u c I2CBUS

SDA

o d
START
D99AU1032

P r STOP

t e
le
Figure 12. Acknowledge on the I2C bus
o
SCL 1 2
b s 3 7 8 9

- O
SDA
MSB
( s )
START
c t D99AU1033
ACKNOWLEDGMENT

d u FROM RECEIVER

r o
e P
l e t
s o
O b

10/21 DocID006317 Rev 5

 TDA7449 Software specifications

5 Software specifications

5.1 Interface protocol

The interface protocol comprises:
 A start condition (S)
 A chip address byte, containing the TDA7449 address
 A subaddress byte
 A sequence of data (N byte + acknowledge)
 A stop condition (P)

s )
Figure 13. Interface protocol
c t(
CHIP ADDRESS SUBADDRESS DATA 1 to DATA n

d u
o
MSB LSB MSB LSB MSB LSB
S 1 0 0 0
D96AU420
1 0 0 0 ACK X X X B DATA ACK

P r
DATA ACK P

ACK = Acknowledge
t e
S = Start
o le
P = Stop
b s
A = Address
B = Auto-increment - O
( s )
c t
d u
r o
e P
l e t
s o
O b

DocID006317 Rev 5 11/21

21
 Examples TDA7449

6 Examples

6.1 No incremental bus

The TDA7449 receives a start condition, the correct chip address, a subaddress with B = 0
(no incremental bus), N-data (all these data concern the subaddress selected), a stop
condition.

Figure 14. No incremental bus (B = 0)

CHIP ADDRESS SUBADDRESS DATA

MSB LSB MSB LSB MSB LSB

s )
t(
S 1 0 0 0 1 0 0 0 ACK X X X 0 D3 D2 D1 D0 ACK DATA ACK P
D96AU421

u c
6.2 Incremental bus o d
The TDA7449 receives a start condition, the correct chip address, a subaddress with B = 1 P r
t e
(incremental bus): now it is in a loop condition with an autoincrease of the subaddress
whereas SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored.
o le
in the loop etc, and at the end it receives the stop condition.
b s
DATA 1 concern the subaddress sent, and DATA 2 concerns the subaddress sent plus one

- O
Figure 15. Incremental bus (B=1)
)
t(s
CHIP ADDRESS SUBADDRESS DATA 1 to DATA n

uc
MSB LSB MSB LSB MSB LSB
S 1 0 0 0 1 0 0 0 ACK X X X 1 D3 D2 D1 D0 ACK DATA ACK P
D96AU422

o d
r
eP
Table 6. Power-on reset condition
Input selection IN2

l e t Input gain 28 dB

s o Volume Mute

O b Bass
Treble
0 dB
2 dB
Speaker Mute

12/21 DocID006317 Rev 5

TDA7449 Data bytes

7 Data bytes

Address = 88 hex (Addr: OPEN)

Table 7. Function selection: first byte (subaddress)

MSB LSB
Subaddress
D7 D6 D5 D4 D3 D2 D1 D0

X X X B 0 0 0 0 Input select
X X X B 0 0 0 1 Input gain

s )
X
X
X
X
X
X
B
B
0
0
0
0
1
1
0
1
Volume

c
Not allowed
t(
X X X B 0 1 0 0
d uBass
X X X B 0 1 0 1 r o Treble
X X X B 0 1 1
e 0 P Speaker attenuate "R"
X X X B 0 1 1
l e t 1 Speaker attenuate "L"

s o
B = 1: incremental bus active
B = 0: no incremental bus O b
X = don’t care
) -
t( s
uc
Table 8. Input selection

od
MSB LSB

Pr
Input multiplexer
D7 D6 D5 D4 D3 D2 D1 D0

e tX
e X X X X X 0 0 Not allowed

ol
X X X X X X 0 1 Not allowed

bs
X X X X X X 1 0 IN2
X X X X X X 1 1 IN1
O

DocID006317 Rev 5 13/21

21
Data bytes TDA7449

Table 9. Input gain selection

MSB LSB Input gain
D7 D6 D5 D4 D3 D2 D1 D0 2 dB steps

0 0 0 0 0 dB
0 0 0 1 2 dB
0 0 1 0 4 dB
0 0 1 1 6 dB
0 1 0 0 8 dB
0 1 0 1 10 dB
0 1 1 0 12 dB

s )
t(
0 1 1 1 14 dB

uc
1 0 0 0 16 dB
1 0 0 1 18 dB
1 0 1 0
o d 20 dB
1
1
0
1
1
0 P r
1
0
22 dB
24 dB
1 1
et e
0 1 26 dB
1
o
1 l 1 0 28 dB
1
b s 1 1 1 30 dB

Gain = 0 to 30 dB
- O
s )
t(
Table 10. Volume selection

uc
MSB LSB Volume

od
D7 D6 D5 D4 D3 D2 D1 D0 1 dB steps

Pr
0 0 0 0 dB
0 0 1 -1 dB

t e 0 1 0 -2 dB

le 0 1 1 -3 dB

so 1 0 0 -4 dB

Ob
1 0 1 -5 dB
1 1 0 -6 dB
1 1 1 -7 dB
0 0 0 0 0 dB
0 0 0 1 -8 dB
0 0 1 0 -16 dB
0 0 1 1 -24 dB
0 1 0 0 -32 dB
0 1 0 1 -40 dB
X 1 1 1 X X X Mute

Volume = 0 to 47dB/mute

14/21 DocID006317 Rev 5

TDA7449 Data bytes

Table 11. Bass selection

MSB LSB Bass
D7 D6 D5 D4 D3 D2 D1 D0 2 dB steps

0 0 0 0 -14 dB
0 0 0 1 -12 dB
0 0 1 0 -10 dB
0 0 1 1 -8 dB
0 1 0 0 -6 dB
0 1 0 1 -4 dB
0 1 1 0
s
-2 dB )
0 1 1 1
ct(
0 dB
1
1
1
1
1
1
1
0
d u 0 dB
2 dB
1 1 0 r
1 o 4 dB
1 1 0
e P 0 6 dB
1 0
l e t 1 1 8 dB
1
1
s o
0
0
1
0
0
1
10 dB
12 dB

O b
1 0 0 0 14 dB

) -
t( sTable 12. Treble selection

uc
MSB LSB Treble
2 dB steps

od
D7 D6 D5 D4 D3 D2 D1 D0

Pr
0 0 0 0 -14 dB
0 0 0 1 -12 dB

t e 0 0 1 0 -10 dB

o le 0 0 1 1 -8 dB

b s 0
0
1
1
0
0
0
1
-6 dB
-4 dB
O 0
0
1
1
1
1
0
1
-2 dB
0 dB
1 1 1 1 0 dB
1 1 1 0 2 dB
1 1 0 1 4 dB
1 1 0 0 6 dB
1 0 1 1 8 dB
1 0 1 0 10 dB
1 0 0 1 12 dB
1 0 0 0 14 dB

DocID006317 Rev 5 15/21

21
Data bytes TDA7449

Table 13. Speaker attenuation selection

MSB LSB Speaker attenuation
D7 D6 D5 D4 D3 D2 D1 D0 1 dB

0 0 0 0 dB
0 0 1 -1 dB
0 1 0 -2 dB
0 1 1 -3 dB
1 0 0 -4 dB
1 0 1 -5 dB
s )
1 1 0
c
-6 dB t(
1 1 1
d u -7 dB

r o
0 0 0 0

e P 0 dB
0
0
0
0
0
1
1
0 le t -8 dB
-16 dB
0 0 1 1
b so -24 dB
0
0
1
1
0
0
0

-
1
O -32 dB
-40 dB
0 1
(1
s ) 0 -48 dB
0 1
c t 1 1 -56 dB

u
od
1 0 0 0 -64 dB

Pr
1 0 0 1 -72 dB
1 1 1 1 X X X Mute

t e
le
so
Speaker attenuation = 0 to -79dB/mute

Ob

16/21 DocID006317 Rev 5

TDA7449 Data bytes

Figure 16. Pin 1 Figure 17. Pins 10, 11

VS VS VS VS

20K 20μA

CREF MUXOUT

20K
s )
GND
c t(
D96AU430
d u D96AU491

Figure 18. Pins 4, 5 r o

Figure 19. Pins 12, 15

e P
VS

le t
VS

s o
ROUT 24
O b 20μA

LOUT

) -
t ( s
20μA

u c
o d 25K

Pr
BIN(L)
D96AU434 BIN(R) D98AU850

t e
Figure 20. Pins 6, 7, 8, 9 Figure 21. Pins 13, 14

o le
b s VS

O VS

20μA 20μA

IN

100K 44K
BOUT(L)
VREF D96AU425
BOUT(R) D96AU429

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Data bytes TDA7449

Figure 22. Pins 16, 17 Figure 23. Pin 20

VS

20μA
20μA

TREBLE(L) SDA
TREBLE(R)
50K

s )
t(
uc
D96AU433 D96AU423

Figure 24. Pin 19

o d
P r
et e
20μA o l
b s
SCL
- O
s )
c t(
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e P
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 TDA7449 Package information

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 25. SO20 mechanical data & package dimensions

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
s )
A

A1
2.35

0.10
2.65

0.30
0.093

0.004
0.104

0.012
c t(
B 0.33 0.51 0.013 0.200
d u
C 0.23 0.32 0.009 0.013
r o
D (1) 12.60 13.00 0.496 0.512

e P
E 7.40 7.60 0.291 0.299

le t
o
e 1.27 0.050

H 10.0 10.65 0.394 0.419

b s
O
h 0.25 0.75 0.010 0.030

L 0.40 1.27 0.016

) - 0.050

ddd
t s
0˚ (min.), 8˚ (max.)

(
0.10 0.004

u c
(1) “D” dimension does not include mold flash, protusions or gate
SO20

d
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.

r o
e P
l e t
s o
O b

0016022 D

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 Revision history TDA7449

9 Revision history

Table 14. Document revision history

Date Revision Changes

Removed DIP20 package option

Updated Table 1: Device summary
03-Sep-2014 5
Revised document presentation along with minor textual
updates and modification of title

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 TDA7449

s )
c t(
d u
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t ( s
u c
o d IMPORTANT NOTICE – PLEASE READ CAREFULLY

P r
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

t e
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order

e
l
acknowledgement.

o
b s
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.

ONo license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2014 STMicroelectronics – All rights reserved

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