Assignment-2

Q1. Write a Verilog code to implement the following FSM. Write a test bench
using the figure given below to verify the functionality of FSM.
Module:
module fsm_eg(clk, reset, a);

input clk, reset;

input a;

parameter idle = 1'b00;

parameter s1 = 1'b01;

parameter final=2'b10;

reg [1:0]present_state;

reg [1:0]next_state;

always @ (posedge clk or reset or a)

begin

if (reset == 1'b1)

begin

$display ("Reset Low, Present State is idle \n");

present_state = idle;

end

else

begin

$display ("Reset High");

case (present_state)

idle:

begin
 $display ("Present state is Idle");

if (a == 1'b0)

begin

next_state = idle;

$display ("a= %b, Next state is Idle, \n", a);

end

else if (a == 1'b1)

begin

next_state = s1;

$display ("a = %b, Next state is S1 \n", a);

end

end

s1:

begin

$display ("Present state is s1");

if (a == 1'b0)

begin

next_state = idle;

$display ("a= %b, Next state is Idle, \n", a);

end

else if (a == 1'b1)

begin

next_state = final;
 $display ("a = %b, Next state is final \n", a);

end

end

final:

begin

$display ("Present state is final");

if (a == 1'b0)

begin

next_state = idle;

$display ("a= %b, Next state is Idle, \n", a);

end

else if (a == 1'b1)

begin

next_state = final;

$display ("a = %b, Next state is final \n", a);

end

end

endcase

present_state = next_state;

end

end

endmodule
Test bench:
module test_fsm1;

// Inputs

reg clk;

reg reset;

reg a;

// Instantiate the Unit Under Test (UUT)

fsm_eg uut (

.clk(clk),

.reset(reset),

.a(a));

initial begin

// Initialize Inputs

clk = 1'b0;

reset = 1'b1;

a =1'b0;

#40 a=1'b1;reset=1'b0;

#120 a=1'b0;

end

always #20 clk=~clk;

endmodule
Results: