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Half Adder Using Different Design Styles: A Review on Comparative Study

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 Journal of Advancements in Robotics
ISSN: 2455-1872
Volume 7, Issue 3
www.stmjournals.com

Half Adder Using Different Design Styles: A Review on

Comparative Study
Anju Rajput1,*, Tripti Dua2, Renu Kumawat3, Avireni Srinivasulu4
1,2
Assistant Professor, Department of Electronics and Communication Engineering, Jaipur
Engineering College and Research Center, Jaipur, Rajasthan, India
3
Associate Professor, Department of Electronics and Communication Engineering, Manipal
University, Jaipur, Rajasthan, India
4
Professor, Department of Electronics and Communication Engineering, Jaipur Engineering College
and Research Center, Jaipur, Rajasthan, India

Abstract
A half adder is a digital logic circuit that performs addition of two single bit binary numbers.
Generally, in various types of processors, adders are used to perform arithmetic and logical
operations .In this paper, working of half adder is analysed by designing it by using three
different logic styles, i.e., CMOS logic, Transmission Gate Logic (TGL) and Pass Transistor
Logic (PTL). The comparison has been made between the circuits on the basis of their power
consumption and transistor count. Simulation of the circuits is carried out using HSPICE tool
at 45 nm, 32 nm and 16 nm technologies at 1V power supply. After simulation it is observed
that power consumption is lowest when the adder is implemented by transmission gate as
compared to CMOS and PTL design styles whereas transistor count is minimum in case of
PTL design style. It is also inferred that CMOS gives the best performance out of the three
design styles.

Keywords: Power dissipation, CMOS, pass transistor, transmission gate, transistor count

*Author for Correspondence E-mail: anju.rajput1409@gmail.com

INTRODUCTION Adder circuits are of two types: Half adder ad

In recent years, there have been many
developments in the field of portable
equipment, in which batteries plays the major
role. With increase in the design complexity,
the power requirements of such devices also
get increased. So, in order to combat these
requirements, it becomes necessary to
investigate the new techniques to design low
power, high performance and reduced area
circuits. Now days there are different logic
styles available to design any circuit [1–5].
In digital electronics, adder is a combinational
circuit, which is used for adding two binary
numbers. An adder has two outputs i.e. a sum
bit (denoted by S) and a carry bit (denoted by
C).An ALU (arithmetic logic circuitry) which
is the integral of a computer uses half adder to
compute the binary addition operation on two
bits. The applications of adder circuit are
address decoding, table index calculation etc.
Full adder. In this paper half adder, circuit is
realized using three different logic styles i.e.
transmission gate, pass transistor and CMOS
logic with three different technologies. Their
analysis is done to obtain minimum power
dissipation as well as they are compared in
terms of transistor count [6–12].
Half adder is a digital combinational circuit
that executes addition of two single bit binary
numbers and generates two outputs i.e., a sum
bit (S) and carry bit (C). If A and B are taken
as primary input bits, then sum bit (S) is
obtained by X-ORing of input bits A and B
and the carry bit (C) is obtained by ANDing of
input bits A and B. Half adder is the simplest
adder circuit and used in many applications
such as to design full adders and calculators, in
ALU of various processors, to calculate the
addresses and many more. Block diagram,
logic diagram and truth table of half adder are

JoARB (2020) 26-32 © STM Journals 2020. All Rights Reserved Page 26
Half Adder Using Different Design Styles: A Review on Comparative Study
shown in Figure 1, Figure 2 Table 1
respectively. The Boolean expression of half
adder is given by:
S= A⊕ B and C=A.B
Fig. 1: Block Diagram of Half Adder.
Fig. 2: Logic Diagram of Half Adder
Table 1: Truth Table of Half Adder.
Input Output
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
According to truth table of Half Adder, the
sum output is replica of input B when input A
is at low logic whereas it is complement of
input B when input A is at high logic. The
carry output is logic ‘0’when control input is at
low logic and it is same as input B when
control input A is at high logic.
TRANSMISSION GATE LOGIC
BASED HALF ADDER
Transmission gate is designed by connecting
PMOS and NMOS devices together in parallel.
Transmission gate is symmetrical from input
and output both ends as input and output
terminals can be interchanged. Transmission
gate is a digitally controlled switch as control
signal applied at gate terminals of the
transistors decides the switching state of the
gate. Pass transistor logic designed by nMOS
transistors has a disadvantage that it is weak
‘0’ device, which is removed by Transmission
JoARB (2020) 26-32 © STM Journals 2020. All Rights Reserved
Rajput et al.
Gate Logic since it utilizes both NMOS and
PMOS transistors. The circuit diagram of half
adder using TGL is shown in Figure 3.
Fig. 3: Half Adder using Transmission Gates.
When control signal A is at low logic, then
gates P2 and P4 are in cut off mode and
behave as open switches whereas transistors
P1 and P3 are triggered on and behave as
closed switches. Conducting paths are
available between data input B and sum output
and 0 volts (GND) and Carry output only.
Thus, Sum output is obtained as replica of
input B and low logic is obtained at Carry
output in this case. When control signal A is at
high logic then gates P1 and P3 are in off state
and do not conduct while gates P2 and P4 are
in on state and conduct to produce desired
outputs. Hence, sum output is obtained as
complement of data input B and carry output is
produced as replica of input B. The input-
output waveforms obtained after simulation of
the circuit is shown in (Figure 4).
HALF ADDER USING PASS
TRANSISTOR LOGIC
Pass transistor Logic is implemented by
nMOS FET. It acts as an electrical switch
Page 27
Journal of Advancements in Robotics
Volume 7, Issue 3
ISSN: 2455-1872
Fig. 4: Simulation Waveform of Half Adder Using Transmission Gate.
which passes or blocks the signal which
depends on the value of control signal. PTL is
used because it requires fewer transistors to
implement any logic gate. Primary inputs can
be used to drive gate as well as source of
nMOS which leads to reduction in number of
transistors required to implement a logic gate.
Half adder implemented using pass transistor
logic is shown in Figure 5.
Fig. 5: Circuit Diagram of Half Adder Using
Pass Transistor.
In this circuit, primary input A is treated as
control input. When control input A is applied
as logic ‘0’then transistors N1 and N3 are
switched on and behave like short circuits
whereas transistors N2 and N4 are switched
off and behave like open circuits. Thus, input
JoARB (2020) 26-32 © STM Journals 2020. All Rights Reserved
B is passed to the output line representing sum
‘S’ and carry output ‘Ç’ is obtained as 0 volts,
i.e., logic ‘0’. When control input A is applied
as logic ‘1’, then transistors N1 and N3 are
turned off and behave like open switches
whereas transistors N2 and N4 are turned on
and behave like closed switches. Thus, sum
output, S is obtained as complement of data
input B and carry output, C is obtained as
replica of data input B. The input-output
waveforms obtained after simulation of the
circuit is shown below in Figure 6.
HALF ADDER USING CMOS LOGIC
Complementary Metal Oxide Semiconductor
(CMOS) logic deploys symmetric number of
both types of MOSFETs, i.e., pMOS and
nMOS. This leads to better performance of any
logic circuit since nMOS is strong ‘0’ device
and pMOS is strong ‘1’device. Thus, CMOS
provides complete ‘1’ and complete ‘0’ logics
at the output without any distortion. Half
Adder using CMOS modeled using 12
transistors as shown in Figure 7.
The circuit is simulated using HSPICE tool
and the waveforms obtained for inputs and
outputs are displayed in Figure 8.
COMPARATIVE ANALYSIS
Half adder is implemented using
Transmission Gate Logic, Pass transistor
Logic and CMOS logic. Half adder designed
by PTL utilizes minimum number of
transistors and thus it is most area efficient
out of the three design styles. All the circuits
Page 28
Half Adder Using Different Design Styles: A Review on Comparative Study Rajput et al.

Fig. 6: Simulation Waveform of Half Adder using Pass Transistors.

Fig. 7: Half Adder Using CMOS Logic.

Table 2: Comparison Table of HA Different Design Styles.

Name of Circuit No. of Technology Supply Power
transistors Used voltage consumption (in
used watts)
(i) Half Adder using 8 45nm 1v 9.8765E-09
transmission gate 32nm 6.3361E-09
16nm 7.6242E-10
(ii) Half Adder using 4 45nm 1v 1.8693E-05
pass transistors 32nm 1.8031E-05
only 16nm 2.8715E-05
(iii) Half Adder using 12 45nm 1v 9.7266E-09
CMOS only 32nm 6.6220E-09
16nm 1.5063E-09

are simulated using Synopsys HSPICE tool at power supply. Power dissipation consumed by
45nm, 32nm and 16 nm technologies at 1V all the circuits are found out and tabulated

JoARB (2020) 26-32 © STM Journals 2020. All Rights Reserved Page 29
Journal of Advancements in Robotics
Volume 7, Issue 3
ISSN: 2455-1872

below in Table 2. After comparison it can be CONCLUSION

inferred that power consumed by the circuits
designed using TGL and CMOS design styles
is comparable, but the circuit implemented by
PTL consumes much higher power.
The comparison of power consumption by
half adder designed by using different design
styles at different technologies is also
compared with the help of bar graphs and
shown in figures.
In this paper, comparison of half adder
implemented using Pass Transistor Logic,
Transmission Gate Logic and CMOS logic has
been reviewed on the basis of power
consumption and transistor count. The circuits
are simulated using Synopsys HSPICE tool at
45nm, 32nm and 16 nm technologies at 1V
power supply. It is concluded that circuit
designed by PTL is area efficient as it deploys
minimum number of transistors as compared
to TGL and CMOS design styles. The power

Fig. 8: (a) Simulation Waveform of Half Adder using CMOS Logic.

Comparison in 45 nm

2.0000E-05 1.8693E-05
Power Consumption

1.6000E-05

1.2000E-05

8.0000E-06

9.8765E-09
4.0000E-06 9.7266E-09

0.0000E+00
Transmission
Pass Transistor CMOS
Gate
Power 9.8765E-09 1.8693E-05 9.7266E-09

Design Style

Fig. 8: (b) Simulation Waveform of Half Adder Using CMOS Logic.

JoARB (2020) 26-32 © STM Journals 2020. All Rights Reserved Page 30
Half Adder Using Different Design Styles: A Review on Comparative Study Rajput et al.

Comparison in 32 nm
1.8031E-05
2.0000E-05

1.6000E-05
Power Consumption

1.2000E-05

8.0000E-06
6.3361E-09 6.6220E-09
4.0000E-06

0.0000E+00
Transmission
Pass Transistor CMOS
Gate
Power 6.3361E-09 1.8031E-05 6.6220E-09

Design Style
Fig. 8: (c) Simulation Waveform of Half Adder Using CMOS Logic.

Comparison in 16 nm

3.6000E-05
2.8715E-05
Power Consumption

3.0000E-05

2.4000E-05

1.8000E-05

1.2000E-05

7.6242E-10 1.5063E-09
6.0000E-06

0.0000E+00
Transmission
Pass Transistor CMOS
Gate
Power 7.6242E-10 2.8715E-05 1.5063E-09

Design Style
Fig. 8: (d) Simulation Waveform of Half Adder Using CMOS Logic.

consumed by half adder designed by TGL and
CMOS logic is in range of nanowatts whereas
that implemented by PTL consumes power in
the range of microwatts. So, it can be said that
TGL is power efficient design style, but
CMOS design style gives best performance out
of the three design styles.
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Cite this Article
Anju Rajput, Tripti Dua, Renu Kumawat,
Avireni Srinivasulu. Half Adder Using
Different Design Styles: A Review on
Comparative Study. Journal of
Advancements in Robotics. 2020; 7(3):
25–32p.
Page 32