Term Paper Report of Digital IC Design

on

Electronic Voting Machine

Submitted By
Name: J. Ramadevi
RegNo: 21266006

MASTER OF TECHNOLOGY

in

Electronics & Communication Engineering

(Specialization: VLSI Design & Embedded System)

Submitted to
Dr. Ajay Kumar Mahato Mtech., ph.D

Department of Electronics & Communication Engineering

National Institute of Technology Raipur

Raipur-492010 (C.G.), India

2021

i
 CONTENTS

Contents……………………………………………………………………………………………2
1. Introduction & History ……………………………………………………………..3
1.1 Introduction ……………………………………………………………..……….3

2. Literature survey ……………………………………………………………………4-5

3. Project Work………………………………………………………………………….6

3.1 EVM………………………………………………………………………………6-7

3.2Description of Signals used in EVM………………………………………………8

3.3 EVM working……………………………………………………………………..9

3.4 EVM code………………………………………………………………………...9-18

3.5 Project settings……………………………………………………………………18

4. Results and discussions……………………………………………………………19-22

5. Conclusion…………………….………………………………………………………23

6. Future Scope…………………………………………………………………………..23

7. References…………….…………………………………………………………….23-25

2
1. INTRODUCTION & HISTORY:
1.1 Introduction:
In earlier days elections are conducted by ballot papers. In this ballot papers method voter used
to cast their votes by making the stamp against their favorite party/candidate and then fold the
paper according to the instructions given by the election examiner. In this process if they fold it
incorrectly or marking the stamp in two sections makes their vote invalid. This process takes lots
of time and less efficient as the population increases, we require huge amount of ballot papers
needs to be printed, large number of ballot boxes had to be used, transported, and a large amount
of manpower required for counting those ballot papers. It takes lots of time and energy to
complete the election procedure. So to overcome the problems arises with this ballot voting
technique, The Electronics Corporation of India Ltd. (ECIL), Hyderabad, and Bharat Electronics
Ltd. (BEL), Bangalore, developed the electronic voting machine in 1981.

Advantages of EVM:

The Electronic voting machine has following advantages:

1. Easy to conduct election when compared to traditional ballot paper method.

2. Easy transportation and maintenance of voting machine, reduces the transportation of
large ballot boxes.
3. Storage capacity is more in EVM.
4. Easy to cast the votes safe and securely without any confusion.
5. No chance of invalid votes easy to identify and cast the votes.
6. Requires less time compared to traditional method.
7. Less chances for fake votes.
8. Eco-friendly device.
9. Accurate counting when compared to manual counting. In manual counting there may be
the chance of human errors.
10. Reduces the expenditure for election process.
11. Voting machines capable to store the data for a period of three years. If there is any
ambiguity we can reduce it easily.
12. A vote once recorded cannot be removed or tampered.
13. One can cast their vote only once.
14. Reduces manpower requirement.
15. There is less chance for fake votes.
16. We can add additional features like biometrics to check the eligibility of voter to cast
their vote.
17. We can also link the biometrics of the voter to their corresponding Voter-id. So once the
vote is polled by the voter, It deny the any additional votes by same voter.

3
 18. It gives the conformation that the corresponding vote is polled by blinking led or by any
beep sound.
19. We can add security features to existing evm like password, autolocking etc.

2. LITERATURE SURVEY:

S. Name of Author’s Title of Article Remark Published In

No
.
1 1.TIMARDEEPKAURARNEJ Implementation Of In this they International
A, 2. JASLEENKAURBASSI, Electronic Voting Implemented Journal of
3.DAMANJEETKAUR Machine Through electronic Soft
FPGA 1 voting machine Computing
IMPLEMENTATIO in VHDL using and Artificial
N OF ELECTRONIC XILINX ISE Intelligence,
VOTING MACHINE 9.2i which is ISSN: 2321-
THROUGH FPGA implemented on 404X,
SPARTAN 3E Volume-2,
FPGA board Issue-1, May-
2014
2 1. Sudharsan B, Secured Electronic In this paper NA
2. Nidhish Krishna M P Voting System Using they used block
3. Boopathi Raj J,4. Dr. M. the Concepts of chain model to
Alagappan Blockchain develop the
electronic
voting machine
to have more
security
3 1.Mr. Sharan Kumar Tamper Proof In this paper it International
2.Ms. Rama C. Mane. Electronic Voting is introduces Journal of
3. Ms.R. R. Naik. Machine GSM and RFID Engineering
Implementation on smart card gto Research &
FPGA enhance the Technology
security of (IJERT) 2013
existing ISSN: 2278-
Electronic 0181, Vol. 2
voting machine. Issue 2,
February-
4 1.Rahil Rezwan Biometrically In this paper, 2017 IEEE
2. Huzaifa Ahmed, Secured Electronic they developed Region 10
3.M. R. N. Biplob, Voting Machine evm using Humanitarian
4.S. M. Shuvo, Arduino and Technology
5.Md. Abdur Rahman finger print Conference
scanner to 2017, Dhaka,

4
 identify the Bangladesh
each voter
eligibility to
conduct secured
voting .
5 1.Tushar Puri Prototyping of Indian In this paper the International
2. Jaspreet Singh Electronic Voting ASIC design Journal of
3. Hemant Kaushal Machine -A step implementation Engineering
towards ASIC in is used. Voter- Research and
voting verified paper Development
audit trail e-ISSN:
(VVPAT) 2278-
system is 067X,Volum
interfaced with e 13, Issue 5 ,
the ASIC based (May 2017),
design, which
makes the
EVM machine
more reliable.
Xilinx ISE used
for simulation.
6 1.K. Gurucharan, Xilinx Based In this proposed International
2.B. Kiranmai, Electronic Voting EVm was Journal of
3.S. S. Kiran, Machine implemented on Engineering
4.M. Ravindra Kumar Xilinx ISE and
using verilog Advanced
HDL and also Technology
implemented on (IJEAT)
FPGA board ISSN: 2249 –
for real time. 8958,
This can be Volume-9
reprogrammabl Issue-1,
e according to October 2019
the application
which reduces
expenditure.
7 1 A. BalaMurali, Smart and Secure In this paper International
2 Potru Sarada Sravanthi, Voting Machine they proposed Conference
3 B. Rupa, using Biometrics additional on Inventive
feature to the Systems and
existing EVM Control IEEE
to identify and Xplore Part
to verify the Number:
register ISBN: 978-1-
candidate to 7281-2813-
poll their votes. 9(ICISC -

5
 So the Security 2020)
increases when
compared t
existing EVM.

3. PROJECT WORK:
3.1 Electronic Voting Machine (EVM):
The EVM consists of two units-(a) Control unit,

(b) Balloting unit.

A balloting unit can capable to cater votes for 16candidates.4 balloting units are linked together for
catering all to 64 candidates and controlled by one control unit. The control unit is kept under the
observation of Election conducting officer. Balloting unit is used by the voters to cast their votes to
corresponding candidate. They simply recognize the name and symbol for the corresponding candidate
and press the button corresponding candidate. A led is provided in ballot box corresponding to each
candidate.

To implement this Electronic voting machine we have to undergo the following phases: design flow,
algorithm and verilog code is developed to implement the design logic. In this project EVM is designed
on Xilinx Ise14.7 using verilog HDL and implemented on Sprtan6 Field programmable Gate array (FPGA)
board. As this is implemented on the FPGA board it can be reprogrammable according to the
requirement or application, which reduces the additional expenditure to design new system. The design
flow of electronic voting machine is shown in fig3.1.

The proposed EVM has implemented by using the design flow logic shown in below fig 3.1.Initaially all
party votes are set to zero and all displays shows zero on the corresponding seven segment boards.
Once the clock edge arises, system has to check whether reset is high or low, if reset is high then all the
registers and counters are set zero. This reset is useful to make sure that there are no previous values in
counter to start fresh polling. Once the reset made to Zero Then it check for System enable signal it is
controlled by the control unit once the enable is high evm starts counting the votes polled by the voters.
The enable is high till the completion of polling procedure, once the time permitted to polling is
completed controlling officer has to disable the enable input ,once it is disable no further polling takes
place al the counters stores the votes polled by the voters. Seven segment displays shows the count
Initial sate
values of corresponding party/candidate.

Clock posedge
clock
6
 yes
If rst
Reset all counters
to zero go to
initial state
no

Sel&v-
stop en=1

Sel=00 Sel=01 Sel=1

0

Party 0 counter Party 1 counter Party 2 counter

counts counts counts

Corresponding led Corresponding led

Corresponding led
glows glows
glows

Corresponding
Corresponding Corresponding
display shows
display shows display shows

All polled votes are are added

Fig3.1 EVM design flow

Don’t count invalid
3.2 Description of signals used in EVM design:
stop
The following table describes the input, output and intermediate signals used in this project:

7
 S.no Signal Signal type Signal description
1 clk input Clock signal for system operation
2 Voting _ enable input Control signal to start and stop of voting
process
3 select party input Input signal to select party by voter
4 opled output Output led shows which party vote is
polled
5 Count_Party0 output Number of voter polled by votrs for party0
6 Count_Party1 output Number of voter polled by votrs for party1
7 Count_Party2 output Number of voter polled by votrs for party2
8 dout output Total votes polled by voters
9 An0 intermidiate Control signal to enable sevensegement
display 0
10 An1 intermidiate Control signal to enable sevensegement
display 1
11 An2 intermidiate Control signal to enable sevensegement
display 2
12 bcd02 intermidiate MSB Bcd representation of counter0
13 bcd01 intermidiate lSB Bcd representation of counter0
14 bcd12 intermidiate MSB Bcd representation of counter1
15 bcd11 intermidiate lSB Bcd representation of counter0
16 bcd 22 intermidiate MSB Bcd representation of counter2
17 bcd21 intermidiate lSB Bcd representation of counter0
18 Count0 intermidiate Intermediate counter to store party 0 votes
19 Count1 intermidiate Intermediate counter to store party 1 votes
20 Count2 intermidiate Intermediate counter to store party 2votes
21 seg02 output Sevensegment display to show bcd msb of
party0 value
22 seg01 output Sevensegment display to show bcd lsb of
party0 value
23 seg12 output Sevensegment display to show bcd msb of
party1value
24 seg11 output Sevensegment display to show bcd lsb of
party1 value
25 seg22 output Sevensegment display to show bcd msb of
party2 value
26 seg21 output Sevensegment display to show bcd lsb of
party2 value
27 Reset,ivalid Input,output Reset input to rest all values to zero, for
next polling. invalid is indicates nota.
Table.1 The input, output and intermediate signals used in this project

3.3 EVM working:

8
To start the polling by the evm it has to be reset. After reset all the counter values reset to zero
now we start new polling. If positive edge of clock occurs then system checks whether voting
enable is high or low if voting enable is high it has to count the votes polled by the voters. Once
the voting enable is high the voters can select the party of their interest. The corresponding party
counter increments its values and stored in counter party0.Whevenever party is selected
corresponding led glows and the votes polled to the corresponding party is displayed by seven
segment display used in this implementation. This process continues till the voting enable is low
once the voting enable is low the voting process is terminated, corresponding party votes and
total votes polled by voter displayed by the seven segment displays. The simulation results are
shown in results and discussion sections.

3.4 EVM CODE:

Module:

module Electronic Voting Machine

(clk,voting__enable,rst,selectparty,dout,opled,count__party0,count__party1,count__party2,seg02
,seg01,seg12,seg11,seg22,seg21,invalid);

input clk;

input voting_enable;

input rst;

input [1:0]selectparty;

output reg [4:0]dout; // total votes polled,maxium votes are 255

output reg[3:0]count_party0=4'd0;

output reg[3:0]count_party1=4'd0;

output reg[3:0]count_party2=4'd0; //couners of correspong paty

output reg [2:0]opled; //corresponding party led glows to represent that vote is
polled

output reg invalid;

reg [3:0]count0=4'd0;

reg [3:0]count1=4'd0;

9
reg [3:0]count2=4'd0; ///registers to store intemidiate votes

reg an0=1'b0;

reg an1=1'b0;

reg an2=1'b0; //signals used to activate correspong 7segmentdisplays of partys

reg [3:0]bcd02;

reg [3:0]bcd01; //bcd conversion of party0 votes

reg [3:0]bcd12;

reg [3:0]bcd11; // bcd conversion of party1 votes

reg [3:0]bcd22;

reg [3:0]bcd21; // bcd conversion of party2 votes

output reg [6:0]seg02=7'd1;

output reg [6:0]seg01=7'd1;

output reg [6:0]seg12=7'd1;

output reg [6:0]seg11=7'd1;

output reg [6:0]seg22=7'd1;

output reg [6:0]seg21=7'd1;

parameter whiteparty=2'b00; //party0

parameter redparty=2'b01; //party1

parameter pinkparty=2'b10; //party2

10
parameter nota=2'b11; // invalid party

//Counting for party0 votes

always @(posedge clk)

begin

if(rst==1'b1)

begin

count_party0=4'd0; count_party1=4'd0; count_party2=4'd0;

count0=4'd0; count1=4'd0; count2=4'd0;seg21=7'd1;seg22=7'd1;

seg11=7'd1;seg12=7'd1;seg01=7'd1;seg02=7'd1;

end

else

case(selectparty)

whiteparty:

begin

opled=3'b001;invalid=1'b0;

end

redparty:

begin

opled=3'b010;invalid=1'b0;

end

pinkparty:

begin

opled=3'b100;invalid=1'b0;

end

11
 nota:

begin

invalid=1'b1;opled=3'b111;

end

default :

begin

opled = 3'b000;invalid = 1'b0;

end

endcase

if(selectparty == 2'b00 && voting_enable == 1'b1)

begin

count_party0 = count0;

an0=1'b1;

binarytobcd(count0,bcd02,bcd01); ////////converting party0 votes to bcd

sevensegmentdisplay(an0,bcd02,seg02); ///sevensegment display fpr displying

part01 votes

sevensegmentdisplay(an0,bcd01,seg01);

end

if(selectparty== 2'b01 && voting_enable == 1'b1)

begin

count_party1 = count1;

an1=1'b1;

binarytobcd(count1,bcd12,bcd11); ////converting party1 votes to bcd

12
 sevensegmentdisplay(an1,bcd12,seg12); ///sevensegment display for displying
party1 votes

sevensegmentdisplay(an1,bcd11,seg11);

end

if(selectparty == 2'b10 && voting_enable == 1'b1)

begin

count_party2 = count2;

an2=1'b1;

binarytobcd(count2,bcd22,bcd21); /////////converting party12 votes to bcd

);

sevensegmentdisplay(an2,bcd22,seg22); ///////sevensegment
display fpr displying party2 votes

sevensegmentdisplay(an2,bcd21,seg21);

end

count0 = count_party0+ 4'd1;

count1 = count_party1+ 4'd1;

count2 = count_party2+ 4'd1;

dout = count_party0 + count_party1 + count_party2; ///total votes polled

end

task binarytobcd;

input [3:0]a;

output reg [3:0]out2;

output reg [3:0]out1;

13
begin

out2[3]=1'b0;

out2[2]=1'b0;

out2[1]=1'b0;

out2[0]=(a[3]& a[2])|(a[3]& a[1]);

out1[3]=(a[3]&(~a[2])&(~a[1]));

out1[2]=(~a[3]&a[2])|(a[2]&a[1]);

out1[1]=(a[3]&a[2]&(~a[1]))|((~a[3]&a[1]));

out1[0]=a[0];

end

endtask

////sevensegment display code using task

task sevensegmentdisplay;

input seg_enable;

input [3:0]sel;

output reg [6:0]seg;

//always @(sel)

begin

if(seg_enable==1'b1)

begin

case (sel) //case statement

0 : seg = 7'b1111110;

1 : seg = 7'b0110000;

14
 2 : seg = 7'b1101101;

3 : seg = 7'b1111001;

4 : seg = 7'b0110011;

5 : seg = 7'b1011011;

6 : seg = 7'b1011111;

7 : seg = 7'b1110000;

8 : seg = 7'b1111111;

9 : seg = 7'b1111011;

default : seg = 7'b0000_0000;

endcase

end

end

endtask

endmodule

Testbench:

module test_evm;

// Inputs

reg clk;

reg voting_enable;

reg rst;

reg [1:0] selectparty;

// Outputs

wire [4:0] dout;

wire [2:0] opled;

15
wire [3:0] count_party0;

wire [3:0] count_party1;

wire [3:0] count_party2;

wire [6:0] seg02;

wire [6:0] seg01;

wire [6:0] seg12;

wire [6:0] seg11;

wire [6:0] seg22;

wire [6:0] seg21;

wire invalid;

// Instantiate the Unit Under Test (UUT)

EVM uut (

.clk(clk),

.voting_enable(voting_enable),

.rst(rst),

.selectparty(selectparty),

.dout(dout),

.opled(opled),

.count_party0(count_party0),

.count_party1(count_party1),

.count_party2(count_party2),

.seg02(seg02),

.seg01(seg01),

.seg12(seg12),

16
 .seg11(seg11),

.seg22(seg22),

.seg21(seg21),

.invalid(invalid)

);

initial begin

// Initialize Inputs

$dumpfile("powerfile_EVM.vcd");

$dumpvars(1,test_evm.uut);

//$monitor("clk=%b,rst=%b,voting_enable=%b,selectparty=%b,counter_party0=
%d,counter_party1=%d,counter_party2=
%d,dout=d",clk,rst,voting_enable,selectparty,count_party0,count_party1,count_party2,dout);

voting_enable = 1'b0;

rst =1'b 0;

selectparty =2'b11 ;

clk = 1'b0;

rst = 1'b1;voting_enable =1'b 0;selectparty = 2'b11;

#20 rst = 1'b0;voting_enable =1'b 1;selectparty = 2'b11;

#40 rst = 1'b0;voting_enable =1'b 1;selectparty = 2'b00;

#40 rst = 1'b0;voting_enable =1'b 1;selectparty = 2'b10;

#40 rst = 1'b0;voting_enable =1'b 1;selectparty = 2'b01;

#20 rst = 1'b0;voting_enable =1'b 1;selectparty = 2'b00;

#40 rst = 1'b0;voting_enable =1'b 1;selectparty = 2'b00;

17
#40 rst = 1'b0;voting_enable =1'b 1;selectparty = 2'b10;

#40 voting_enable =1'b 0;

end

always #20 clk=~clk;

endmodule

3.5 Project settings:

Fig 3.5 project settings for EVM

4. RESULTS AND DISCUSSIONS:

18
Here electronic voting machine is designed in Xilinx ISE14.7 using verilog HDL the simulation
result obtained from the simulator shown in this section.

Fig 4.1 EVM RTL schematic view

The above Fig 4.1 shows RTL view of Electronic Voting Machine (EVM).It shows input and
output signals of evm. The inputs to the module are select party, clk, voting enable ,resetsand the
outputs of the module are dout, output led, countparty0, countparty1, and countparty2, invalid, seg02,
seg02, seg11 , seg12, seg22and seg21.Technology schematic contains LUTs used in EVM and all the
blocks used in the design of evm shown in fig 4.2

19
 Fig 4.2 EVM Technology schematic view

Fig 4.3 Output waveform when for first vote is polled

The above Fig4.3 shows the output of EVM when the first vote is polled by the voter. From the
fig4.3 we can clearly observe that the when the voting enable high voting is started. At positive
clock edge user selects party0, so the corresponding vote is shown in party0 counter and

20
displayed by corresponding 7segmant display. Opled is 001 so the corresponding led of party0 is
glows.

Fig 4.4: Output waveform when for second vote is polled

The above Fig4.4 shows the output of EVM when the second vote is polled by the voter. From
the fig4.4 we can clearly observe that the when the voting enable high voting is started. At 2 nd
positive clock edge user selects party1, so the corresponding vote is shown in party1 counter is
incremented and displayed by corresponding 7segmant display. Opled is 010 so the
corresponding led of party1 is glows. At same time first vote polled to party0 is remains same as
previous value.

Fig 4.5: Output waveform at the end of voting procedure

21
The above Fig4.5 shows the output of EVM when the voting is completed. From the fig4.5 we
can clearly observe that the when the voting enable high voting is started and continues till
voting enable is low. Here total 7 votes polled by the voters dout shows total valid votes polled
by voters, voters polled to party0=3, voters polled to party0=2, voters polled to party0=1, total
valid votes are 6. So dout shows 6.Remaing one vote is invalid selection party means other than
available options are selected by the user so it is considered as invalid. In this way total polling is
conducted by using EVM. The polled votes are displayed by the corresponding seven segment
displays. By comparing the votes we can easily decide the winner in the election process.

Fig 4.6 output printed statements

Slice Logic Used Available Utilization

Utilization

Number of bonded 68 102 66%

IOBs

    Number of fully 41 55 74%

used LUT-FF pairs

Table.2 Area

The above table shows the Area utilized to implement Electronic Voting Machine(EVM).It uses
total 68 input output boards,41 Look up tables present in SPARTEN6 board.

Logic delay Route delay Total delay

22
 2.142ns 3.912ns 6.054ns

Table.3 Area

The above table shows the delay in EVM it has logic delay of 2.142ns, Route delay of 3.912ns,
Total delay of 6.054ns.

Dynamic power Quiescent power Total power

0.006W 0.014W 0.020W

Table.4 power

The above table.4 shows the power dissipated by the EVM. It dissipates total power of 20mW,It
that maximum power is Leakage or static or quiescent power of 14mW.Remaing 6mW power is
Dynamic power.

5. CONCLUSION:
The Xilinx based electronic voting machine met the requirements of the election process such as
enrolling the total no. of voters & contestants. Allowing the voter to cast his vote to a particular
party of his choice which in turn is confirmed by the led. In the final stage it compares all the
valid votes polled to different parties and confirm the winner of the election. We can also add
additional features like biometrics. Here EVM is implemented on FPGA board in future if we
want add additional features, we can reprogram this EVM.

6. FUTURE SCOPE:
Here EVM is implemented on FPGA board in future if we want add additional features, we can
reprogram this EVM. We can add additional features like finger print scanner, facial recognition,
and password based systems to avoid rigging or tampering of EVM. This FPGA based
implementation can also be extend to ASIC based design by interfacing additional modules like
GSM module, RFID for better security purpose. As the technology develops day by day we need
to protect this voting process by upgrading the EVM with new features to avoid tampering.

7. REFERENCES:
[1]. Xilinx Based Electronic Voting Machine K. Gurucharan, B. Kiranmai, S. S. Kiran, M.
Ravindra Kumar International Journal of Engineering and Advanced Technology (IJEAT) ISSN:
2249 – 8958, Volume-9 Issue-1, October 2019.

23
[2]. Tamper Proof Electronic Voting Machine Implementation on FPGA Mr. Sharan Kumar
Electronics Department T.K.I.E.T Warananagar Ms. Rama C. Mane. Electronics Department
T.K.I.E.T Warananagar Ms.R. R. Naik. Electronics Department T.K.I.E.T Warananagar
International Journal of Engineering Research & Technology (IJERT) Vol. 2 Issue 2, February-
2013

[3]. Biometrically Secured Electronic Voting Machine Rahil Rezwan, Huzaifa Ahmed, M. R. N.
Biplob, S. M. Shuvo, Md. Abdur Rahman Department of Electrical and Electronic Engineering
American International University-Bangladesh rahil.sh18@gmail.com 2017 IEEE Region 10
Humanitarian Technology Conference (R10-HTC) 21 - 23 Dec 2017, Dhaka, Bangladesh.

[4]. Electronic Voting Machine with Enhanced Security Shashank S Kadam BE, Electronics,
Datta Meghe College of Engineering, Mumbai University, India. Telephone:(+91)-9152761969..
Sujay Dandekar Proceedings of the International Conference on Communication and Electronics
Systems (ICCES 2018) IEEE Xplore Part Number:CFP18AWO-ART; ISBN:978-1-5386-4765-
3.

[5]. IMPLEMENTATION OF ELECTRONIC VOTING MACHINE THROUGH

FPGA ,1TIMARDEEPKAURARNEJA, 2 JASLEENKAURBASSI, 3DAMANJEETKAUR,
International Journal of Soft Computing and Artificial Intelligence, May-2014

[6]. Secured Electronic Voting System Using the Concepts of Blockchain, Sudharsan B, Rishi
Tharun V.

[7]. Micro-Controller Based Smart Electronic Voting Machine System 1 Sahibzada Muhammad
Ali, 1 Chaudhary Arshad Mehmood, 5 Ahsan Khawja, 3 Rahat Nasim

[8]. Prototyping of Indian Electronic Voting Machine -A step towards ASIC in voting Tushar
Puri1 Jaspreet Singh2 Hemant Kaushal 3 International Journal of Engineering Research and
Development Volume 13, Issue 5 (May 2017), PP.44-51

[9]. A Critical Study of Electronic Voting Machine (EVM) Utilization in Election Procedure Dr.
A. V. Nikam1, Dr. P. C. Shetiye2, Dr. S. D. Bhoite3 International Journal of Trend in Scientific
Research and Development (IJTSRD) Conference Issue | March 2019 Available Online:
www.ijtsrd.com e-ISSN: 2456 - 6470

[10]. Smart and Secure Voting Machine using Biometrics 1 A. BalaMurali, 2 Potru Sarada
Sravanthi, 3 B. Rupa, Proceedings of the Fourth International Conference on Inventive Systems
and Control (ICISC 2020) IEEE Xplore Part Number: CFP20J06-ART; ISBN: 978-1-7281-
2813-9

[11]. Jeremy Clark, Aleks Essex and Carlisle Adams “Secure and Observable Auditing of
Electronic Voting Systems using Stock Indices” 0840-7789/07/$25.00 ©2007 IEEE

24
[12]. Leyou Zhang, Yupu Hu, Xu’an Tian and Yang Yang “Novel Identitybased Blind Signature
for ElectronicVoting System” 978-0- 7695-3987-4/10 $26.00 © 2010 IEEE DOI
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