DD-II

EXPERIMENT 11

Name : Abdelrahman Date :11/4/2022

Roll No.: 2k20/EC/004

1- Aim: To write Verilog code for ALU(74381) using the behavioral model.

2- Theory :

ALUs comprise the combinational logic that implements logic operations such
as AND, OR, NOT gate, and arithmetic operations, such as Adder, and
Subtractor.

Functionally, the operation of a typical ALU is represented as shown in the

diagram below.
The 74381 performs three arithmetic and three logic operations on two 4-bit
words, A and B. Two additional select input codes force the function outputs to
LOW or HIGH. Carry propagate and generate outputs are provided for use with
the 74182 carry-lookahead generators for high-speed expansion to longer
word lengths. For ripple expansion,

- Logic symbols :

- Connection diagram :
 - Functional description :

Signals applied to the Select inputs S0–S2 determine the mode of operation, as
indicated in the Function Select Table. An extensive listing of input and output
levels is shown in the Truth Table. The circuit performs the arithmetic functions
for either active HIGH or active LOW operands, with output levels in the same
convention. In the Subtract operating modes, it is necessary to force a carry
(HIGH for active HIGH operands, LOW for active LOW operands) into the Cn
input of the least significant package. The Carry Generate (G) and Carry
Propagate (P) outputs supply input signals to the 74182 carry-lookahead
generators for expansion to longer word length, as shown in Figure 2. Note
that a 74381 ALU is used for the most significant package. Typical delays for
Figure 2 are given in Figure 1.

Figure1: 16-bit delay tabulation

 - Function select table :

3- Verilog code :

module alu_74381(out,A,B,S,cin);

input [3:0] A,B;

input [2:0] S;

input cin;

output[3:0] out;

reg [3:0] out;

always @(S or A or B or cin)

begin

case (S)
3'b000 : out = 4'b0000;

3'b001 : out = B - A - cin;

3'b010 : out = A - B - cin;

3'b011 : out = A + B + cin;

3'b100 : out = A ^ B;

3'b101 : out = A | B;

3'b110 : out = A & B;

3'b111 : out = 4'b1111;

endcase

end

endmodule

4- Simulation result : (for A = 1101 & B = 0111) :

5- Synthesis result :

- Schematic :
 RTL schematic :

 Synthesized schematic :
- Utilization report :

- Delay summary :

 SETUP :
 HOLD :