IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 18, NO.

10, OCTOBER 2008 695

CMOS Quadrature VCO Implemented With Two

First-Harmonic Injection-Locked Oscillators
Sheng-Lyang Jang, Senior Member, IEEE, S. -S. Huang, Chien-Feng Lee, and M. -H. Juang

Abstract—This letter presents a new quadrature voltage- con-

trolled oscillator (QVCO). The LC-tank QVCO consists of two
first-harmonic injection-locked oscillators (ILOs). The outputs
of one ILO are injected to the gates of the tail transistors on the
other ILO and vice versa so as to force the two ILOs operate in
quadrature. The proposed CMOS QVCO has been implemented
with the TSMC 0.18 m CMOS technology and the die area is
0.582 0.972 mm2 . At the supply voltage of 1.0 V, the total power
consumption is 8.0 mW. The free-running frequency of the QVCO
is tunable from 5.31 GHz to 5.75 GHz as the tuning voltage is
varied from 0.0 V to 1.0 V. The measured phase noise at 1 MHz
offset is 120.01 dBc/Hz at the oscillation frequency of 5.31 GHz
and the figure of merit (FOM) of the proposed QVCO is about
185.48 dBc/Hz.
Index Terms—Complementary metal–oxide semiconductor
(CMOS), first-harmonic injection locked oscillators, quadrature Fig. 1. (a) Standard 4 2 ILFD. (b) First-harmonic injection-locked oscillator.
voltage-controlled oscillator-s (QVCO).

I. INTRODUCTION uses switched tail to reduce the phase noise contribution due to
the tail and it also uses the VCO outputs as the injection signal

Q UADRATURE voltage-controlled oscillators (QVCO)

play a key role in many fully integrated radio-frequency
transceivers with zero-IF architectures requiring I/Q
for coupling so that reliable QVCO can be obtained.

modulation-demodulation. One popular design for QVCO is II. CIRCUIT DESIGN

using two differential VCOs with coupling networks to couple
the two VCOs, and these QVCOs can be classified into several
categories differing in the coupling mechanism. One popular
method is based on many coupling transistors either in parallel
to or in series with the resonator [1], [2], and the other is based
on synchronization of second harmonic signals [3]–[5] through
a transformer [3] or second-harmonic injection to the common
source of switching cross-coupled transistors [4], [5]. The
coupling network in the latter method enforces an anti-phase
relationship between the second-order harmonics of the two
differential VCOs.
In one QVCO [5], tail transistors are biased at a fixed gate
bias; however, the low-frequency device noise of the tail can be
up-converted to the phase noise of oscillator, and this must be
minimized. In the other QVCO [4], the second-harmonic at the
drain node of one the tail is injected to the gate of the tail in
the other VCO, and the efficiency of injection locking relies on
the swing of the second-harmonics. This letter proposes a new
QVCO circuit implemented in the TSMC 0.18 m CMOS tech-
nology and operated in the 5 GHz band. The proposed QVCO
Manuscript received April 10, 2008; revised May 21, 2008. Current version
published October 8, 2008. This work was supported by the National Science
Council under Contract NSC96-2221-E-011-146.
The authors are with the Department of Electronic Engineering, National
Taiwan University of Science and Technology, Taipei 10617, Taiwan. (e-mail:
sljjj@mail.ntust.edu.tw).
Digital Object Identifier 10.1109/LMWC.2008.2003476
1531-1309/$25.00 © 2008 IEEE
Fig. 1(a) shows one standard injection-locked frequency di-
viders (ILFD) [6] with the tail injection method. The two out-
puts of the oscillator have the frequency component at the ra-
dian frequency , while the common source of the switching
transistors oscillates at . If an injection signal oscillating
at is applied to the gate of the tail transistor serving as a
voltage-current converter, the oscillator’s output locks to the in-
jection frequency within a locking range. Fig. 1(b) shows the
circuit topology of a first-harmonic injection locked oscillator
(ILO). A differential injection signal with the frequency gen-
erates an output signal oscillating at at the common source
of switching transistors, and the outputs of oscillator oscillate at
the frequency . The proposed QVCO shown in Fig. 2 is based
on two of the first-harmonic ILO circuits shown in Fig. 1(b), by
injecting the differential outputs of one ILO to the gates of tail
transistors in the other ILO and vice versa, so that the two ILOs
are coupled in quadrature phase. Part of the oscillator output
power injects to the current source directly rather than going
through the circulator. Based on the SpertreRF simulation re-
sults, the power is coupled 7.21 dBm from the VCO core at
vtune V, and GHz. Fig. 2 shows the proposed
QVCO, which is based on the mechanisms described for the cir-
cuit shown in Fig. 1(b). The cross-coupled MOSFET pairs (
and , and ) are used to provide negative differential
resistance to compensate for the loss of the LC tanks, which con-
sist of , , . The inductors ( and ,
696
Fig. 2. Proposed quadrature VCO using the differential tail injection technique.
Fig. 3. Chip photograph of the proposed QVCO.
and ) are configured as transformers. The tails are dc biased
at the voltage Vbias.
There are two mechanisms inherent in the QVCO used to
reduce the phase noise from the single-stage VCO shown in
Fig. 1(b). The low-frequency device noise in the tail transistor
can be up-converted to the high-frequency oscillator’s phase
noise. The low-frequency flicker noise is related to the long oc-
cupation time constants of the traps close to the Si SiO inter-
face of MOSFET channel. As a switched transistor will force
a trap to release its captured electron so that the transistor be-
comes memory-less, the flicker noise will be reduced. By mod-
ulating the bias voltage of the tail, the low-frequency device
noise due to the tail transistor is reduced [7], and therefore the
phase noise degradation due to the tail transistor can be min-
imized. Compared with the QVCO[5] with tail transistor at a
fixed dc bias, this QVCO automatically reduces the drawback of
tail transistor. Secondly, the QVCO uses two LC-tank band-pass
filters which symmetrically filter side-band noise around a res-
onance frequency. The noise-filtering effect becomes greater in
two-bandpass-filters architecture than the single bandpass ar-
chitecture, and the injection locking mechanism increases the
signal/noise ratio. It has been shown [8] that phase noise in mu-
tually synchronized oscillators is lower than that of a single os-
cillator provided the coupling network is reciprocal.
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 18, NO. 10, OCTOBER 2008
Fig. 4. Measured tuning range of the QVCO. V = 1:0 V, and V bias =
0:8 V.
Fig. 5. Measured spectrum of the quadrature oscillator at 5.31 GHz. The output
0
power is 3:117 dB. V = 1:0 V, V bias = 0:8 V, and V c = 0:0 V.
III. RESULTS AND DISCUSSION
The QVCO was designed and fabricated in the TSMC
0.18 m CMOS technology. Fig. 3 shows the micrograph of
the proposed QVCO with a chip area of 0.582 0.972 mm
including the pads. Accumulation-mode NMOSFETs are used
as varactors for frequency tuning. The standard FR4 material
is used to build the test board for the QVCO measurement.
The die was glued directly onto the PC board with conductive
materials, and aluminum wire-bonds were used to connect all
input and output pads.
The output spectrum was measured using the Agilent E4407B
spectrum analyzer. The oscillating frequency can be tuned from
5.31 GHz to 5.75 GHz as shown in Fig. 4. As the control voltage
is increased, the varactor’s capacitance decreases; therefore, the
output frequency increases. The power consumption of QVCO
core is 8.0 mW at the supply voltage of 1.0 V. Fig. 5 shows the
measured frequency spectrum of the proposed QVCO. Fig. 6
shows the measured phase noise at the oscillation frequency
of 5.31 GHz, the QVCO was biased at V and
V. The phase noise shows the trend of at
offset frequency between 10 kHz to 10 MHz. The phase noise is
120.01 dBc/Hz at 1 MHz offset frequency. Fig. 6 also shows
the simulated phase noises, obtained by SpectreRF simulations,
of the QVCO and a single-stage VCO shown in Fig. 1(b). The
phase noise of the single-stage VCO is larger than the QVCO.
JANG et al.: CMOS QUADRATURE VCO
Fig. 6. Simulated phase noise of a single-stage VCO, the proposed quadrature
VCO and measured phase noise of the proposed quadrature VCO. V = 1:0 V,
V bias = 0:8 V, and V c = 0:0 V.
Fig. 7. Measured output waveforms of the I and Q channels. V = 1:0 and
V c = 0:0 V.
The figure of merit (FOM) of this proposed QVCO is about
185.48 dBc/Hz, and it is defined as
FOM (1)
mW
where is the oscillating frequency, is the offset fre-
quency, is the phase noise at , is the dc power
consumption of the measured QVCOs.
Fig. 7 shows the measured time-domain output waveforms
of two quadrature VCO output buffers by using the Agilent
54855A Infiniium oscilloscope. The average output phase error
is about 0.33 introduced partly by cables and connectors.
Table I lists the comparison of QVCO performance.
IV. CONCLUSION
A new QVCO circuit has been proposed, it consists of two
differential cross-coupled first-harmonic ILOs, and it uses the
concept of mutually injection-locking of two ILOs. The differ-
ential outputs of one ILO are used as the injection source for
the other ILO. This mutually injection-locked mechanism en-
forces the two ILOs runs in quadrature phase and reduces the
phase noise. The advantages of the circuit over the prior works
are easier implementation because of no complicated coupling
697
TABLE I
COMPARISON OF QVCO PERFORMANCE
network, and improved phase accuracy because no requirement
of resonant network as in superharmonic coupling QVCO. The
prototype QVCO has been designed and implemented in the
0.18 m CMOS technology, and it is designed to operate in the
5.5 GHz frequency band. The figure of merit for the proposed
QVCO is 185.48 dBc/Hz. The QVCO shows phase noise of
120.01 dBc/Hz at 1 MHz offset from the oscillation frequency
of 5.31 GHz while dissipating 8 mW for the whole QVCO from
the supply voltage of 1.0 V.
ACKNOWLEDGMENT
The authors would like to thank the Staff of the CIC for the
chip fabrication and technical supports.
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