DD-||

Experiment-6

Name : Abdelrahman Date : 19/2/22

Roll : 2k20/EC/004

1- Aim: to implement a 3-bit Binary to Gray code converter using dataflow

modeling in Verilog.
2- Theory :

The logical circuit which converts the binary code to equivalent gray
code is known as binary to gray code converter. An n-bit Gray code
can be obtained by reflecting an n-1 bit code about an axis after 2n-1
rows and putting the MSB (Most Significant Bit) of 0 above the axis
and the MSB of 1 below the axis. The reflection of Gray codes is
shown below:

The binary to gray code converter circuit is shown below:

Formulae:-
Let b2 b1 b0 be the 3-bit binary number and g2 g1 g0 be its equivalent gray
code.
Then,
g2 = b2
g1 = b2 ⊕ b1
g0 = b1 ⊕ b0
Example:-
If b2 b1 b0 = 1 0 0, then
g2 = b2 = 1
g1 = b2 ⊕ b1 = 1 ⊕ 0 = 1
g0 = b1 ⊕ b0 = 0 ⊕ 0 = 0
Hence, g2 g1 g0 = 1 1 0

3- Verilog Code :

module binaryto_Gray(

input b0,

input b1,

input b2,
output g0,

output g1,

output g2

);

assign g0 = b0^b1;

assign g1 = b1^b2;

assign g2 = b2;
endmodule;

4- Simulation Results :

5- Synthesis Result :
- Schematics :

- Utilization summary :
- Delay :