CMOS-Based Physically Unclonable Functions:

A Review and Tutorial

Kamal Y. Kamal, Radu Muresan, and Arafat Al-Dweik

ABSTRACT This article reviews complementary metal-oxide-semiconductor (CMOS) based physically

unclonable functions (PUFs) in terms of types, structures, metrics, and challenges. The article reviews and
classifies the most basic PUF types. The article reviews the basic variations originated during a metal–oxide–
semiconductor field-effect transistor (MOSFET) fabrication process. Random variations at transistor level
lead to acquiring unique properties for electronic chips. These variations help a PUF system to generate a
unique response. This article discusses various concepts which allow for more variations at CMOS
technology, layout, masking, and design levels. It also discusses various PUF related topics.

INDEX TERMS Hardware security, IoT, PUF, RFID, smart card.

I. INTRODUCTION against counterfeiting [8], [28]–[32]. The mobility of objects

Hardware authentication is getting rising importance to cope
with the growing security concerns. Counterfeiting is among
the significant threats to supervisory control and data
acquisition (SCADA) and the internet of things (IoT) [1]–[5].
Counterfeiting an object such as sensor, radio-frequency
identification (RFID) tag, machine-readable document, or
RFID-tagged product involves various security and safety
aspects [6], [7]. This urge to adopt a verification approach that
enables an authorized organization to remotely check a
device’s authenticity [8]–[18]. Furthermore, there is a rapid
growth of contactless machine-readable passports, persons
mobility monitoring tags, vehicle mobility monitoring tags
[19], public transportation smart tickets [20], shipped goods
mobility monitoring tags [21], physical access smart cards
[22], banking smart cards, and near field communication
(NFC) in smartphones [23]. Many of those devices have been
vulnerable to security attacks [24]–[26].
On-chip hardware security for intellectual property (IP)
copyright protection of integrated circuits and other objects
sometimes requires authenticity solutions. Storing on-chip
secret key is not a secure approach against invasive and side-
channel attacks. Cloning an identification number (ID) stored
on a non-volatile memory (NVM) of some smart cards is easy,
instant, and costs only tens of US dollars for the reader/writer
equipment and tens of cents for a blank smart card [27].
Embedding a physically unclonable function (PUF) within an
electronic chip helps secure a smart card or an RFID tag
adds more security threats; for example, a smart card would
sometimes operate in untrusted environments where an
attacker may have time and tools to breach it[33], [34].
The main contributions of this article are as follows:
- Review PUFs types, applications, and challenges.
- Classify PUF into various categories.
- Present simplified mathematical representation for a PUF
basic metrics.
- Review the sources of MOSFET variations and help draw
a road map for complementary metal-oxide-
semiconductor (CMOS) based PUF design and
manufacturing, toward acquiring unique devices.
II. PRELIMINARIES
This section presents a PUF’s basic concepts, properties, and
terms. It also reviews the origins of a MOSFET-based chip
uniqueness. It then discusses various guidelines to acquire
such unique properties during a PUF chip fabrication process.
A. Notations and Definitions
In this article, random variables are denoted in upper-case
symbols; for example, X represents the input challenge bits to
the PUF system; while, Y represents the noisy output response
bits of the system. When a response is considered a reference,
it is denoted as R. If Y is a random vector, then its length

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(the number of the string bits) is denoted as ‖Y‖ . Hamming
distance, D (Y1 ; Y2 ) between two vectors (or strings) Y1 and
Y2 with an equivalent number of bits, represents the number
of bits that have the same position within a vector but with
different values, i.e., D( Y1 ; Y2 ) ≜ { j: Y1, j ≠ Y2, j }, where (j)
indexes the position of the compared bits within the two
vectors, Y1 and Y2 .
Defining a PUF requires to identify the random function.
FIGURE 1. PUF authenticity cause and effect block diagram.
Definition 1: A random function is a function for which
knowing some inputs and outputs does not enable guessing
the output against the other non-observed inputs [35].
A PUF can then be defined as:
Definition 2: A PUF is an unclonable physical function
whose output is hard to determine theoretically but can be
measured experientially. In other words, a PUF is a unique
physical function that is easy to evaluate, yet impossible to
clone physically and hard to model mathematically. A PUF
security is hereditary, so any device equipped with an
inseparable PUF becomes unique and unclonable. [35]–[38].
A string of bits inputted to a random physical function is
called a challenge word, and the output is called a response
word. Utilizing PUFs for authentication purposes does not
require a unique challenge word but a unique response word FIGURE 2. Similar PUFs generate different responses.
against each challenge word, i.e., the uniqueness of an
concentrations [42]. These random fabrication variations
individual PUF instance is attributed to its challenge-
unintentionally form unique properties for each chip entity,
response pair (CRP) uniqueness.
which makes it possible to authenticate each chip. It is
There have been several attempts to authenticate physical
common to consider security systems equipped with PUFs
objects; however, most researchers consider the dawn of
as physical disorder security-based systems [43].
PUFs was when Ravikanth introduced the concept of a one-
way physical function [37], [38], which was initially
B. PUF Properties
proposed for low-cost physical tokens.
There are several basic properties required for identification
Variations throughout a manufacturing process create
and authentication, and some additional properties are
distinct properties for the manufactured object, and since
specifically required for authentication applications [44].
those variations happened out of control, replicating them is
not possible, which makes such an object physically • Defining Properties for PUFs
unclonable. An object with distinct properties, if cha llenged, The following points highlight the most fundamental
would generate a response that forms a unique CRP. This properties for PUFs whether it is meant for
presents an authentication method for that object, among its authentication or identification applications:
peers, as shown in Fig. 1. If a PUF device is used for - A PUF should be physically unclonable.
authentication purposes (and not as a key generator), it does
not have to generate a unique response per se, but the CRP A PUF should be identifiable among other instances. 1
should be unique compared to other PUF devices. Such a - Robustness (or reproducibility), i.e., a PUF repeatedly
physical ID is considered to be a dynamic ID. gives the same output response against the same input
Various sources of random variations usually accompany challenge.
what presumably considered as similarly manufactured PUF
- The defining properties of a PUF should be unique
devices [39]. Such PUFs form a PUF class (Pclass ) [40]. When
among other instances.2
applying an input challenge (C) to such PUFs, each PUF
would generate a distinct response (R), as shown in Fig. 2. - A response should be evaluable; otherwise, the physical
[41] system cannot be considered as a feasible PUF.
For example, similar MOSFETs among different PUF Although there is no standard evaluability measure, the
chips within a Pclass can have distinctive properties due to average time to obtain a response has been considered
fabrication variations in: 1) size, due to etching and coating as a metric in many research articles.
processes; 2) gate insulator thickness (t ox ); and 3) doping - A PUF should be feasible to construct.

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• Other Properties
There are other extra qualities which a PUF should
have to be secure for authentication purposes:
- Truly Unclonable: A secure PUF system would better
have mathematical unclonability, i.e., a secure PUF
system would not be modellable. True unclonability of
a PUF implies both physical unclonability and
mathematical unclonability.
- One-way Function: A PUF is considered as a one-way
function if observing its response does not help to
discern the input challenge; otherwise, the PUF is then
mathematically modelable and thereby insecure.
- Temper Evident: A PUF has such a quality if its
response changes after an invasive attack. This is an
essential property for physically securing the PUF and
accrediting remote authentication.
It is important to note:
1) As marked by 1 and 2 , many researchers try to make PUFs
do both identification and authentication tasks, using a
PUF’s response as an ID [45], [44], and some systems
utilize the response as an encryption key [46].
2) Mathematical unclonability and the one-wayness are both
be elements of the unpredictability.
3) A PUF’s properties and formulations can take various
forms [47]–[50], [31]. Using PUFs for identification
and/or key generation eliminates the tolerance for errors.
A PUF is considered weak or strong, based on its security
level, as follows:
1) WEAK PUF:
A weak PUF may have no or a few input challenges and
usually used to generate an ID. In such PUFs, the number of
CRPs is mostly linearly related to the logical units of the
PUF, such as the PUF ring oscillator. Weak PUFs are
vulnerable to modeling attacks, whether they have a small
number of CRPs [51] or a large number of CRPs [52]. Beside
extending the number of CRP words, longer challenge words
also can slow but cannot stop modeling attacks [53]. It is
clear that digital-based PUFs, whether delay-based or
memory-based, are vulnerable to modeling attacks [51]–
[59].
Examples of weak PUFs: power-up flip-flop PUF [60],
[61], shift register delay PUF [62], buskeeper PUF [63],
power-up static random-access memory (SRAM) PUF [64]–
[79], data retention voltage (DRV) SRAM PUF [80],
destabilized SRAM PUF [81]–[83], SRAM failure PUF [84],
SRAM transformed PUF [85], [86], and memory cell-based
chip authentication (MECCA) PUF [87], latch PUF [88]–
[93], artificial fingerprint device (AFD) PUF [94], [95],
dynamic random-access memory (DRAM) latency PUF
VOLUME XX, 2017
[96]–[105], coating PUF [106], connect PUF [107], [108],
and printed differential circuit (DiffC) PUF [109]. An
extreme case of a weak PUF is a construction that only has a
single challenge word. Such a construction is called
physically obfuscated key (POK) [44], [31], [110].
Chen et al. [111] considered that a strong PUF can serve
in challenge-response authentications, whereas a weak PUF
generates a physically obfuscated key that can be used for
encryption. If the verifier side can decrypt the message with
the archived key (public or private), then the PUF is
authenticated. In general, it is not safe to send a response
from a weak PUF device unless it is encrypted or hashed;
therefore, communications are usually done through an
algorithm that is physically linked to the PUF, like an
application program interface (API). Such PUFs are known
as controlled PUFs (CPUFs) [35], [112], [113].
2) STRONG PUF:
A strong PUF is an ideal concept, and yet no known PUF
has been considered as one. All the proposed PUFs are just
candidates. The distinction between a strong and weak PUF
was first introduced by Guajardo et al. [65] and discussed
further by Rührmair et al. [114], then by Konigsmark et al.
[115]. Strong PUFs are sometimes called physical random
functions [116], [45] or physical one-way functions [37],
[38]. A PUF is considered strong if even when tested by an
attacker for a long time, it sustains its unpredictability for the
non-observed CRP sets [43], [44]. From easier to harder,
Rührmair et al. [54] attacked arbiter PUF [116], XOR arbiter
PUF [117], feed-forward arbiter PUF [118], and lightweight ,
secure PUF [119]. Rührmair et al. considered that a PUF’s
strength depends on number of the CRPs, which implies the
numbers of the challenge and response bits. However, this
was not enough to prevent modeling attacks by machine
learning (ML) methods, such as support vector machines or
perceptrons.[54], [120]. Rührmair et al. [114] concluded that
the more analog components within an electronic PUF
system, the more resilient it would be to ML attacks; thus the
authors nominated PUF power grid. power grid PUF [121],
cellular nonlinear networks (CNN) PUF [122], [123],
crossbar PUF [124]–[126] as possible candidates for the
strong PUF title.
This article adopts strict conditions for a strong PUF, as it
should meets all the following security aspects:
• Physical Unclonability
Statistical and random disorders of manufacturing make
it infeasible to produce identical PUFs even by the same
manufacturing process. That is why such physical entities
are considered physically unclonable.
• Mathematical Unclonability (Unpredictability)
A strong PUF concept implies high unpredictability, i.e.,
mathematical modeling is difficult. A mathematical
unclonability of a PUF depends on:
- Anti-Modeling Complexity: The interactions of
challenge bits within a strong PUF should be
 complicated enough to make it infeasible for a computer
program to predict the response with high probability
(Pr), and with a reasonable time, even if many previous
CRPs were observed [127]. The term high probability
refers here to (1− negligible). Many modeling attacks
have succeeded in modeling various digital-based PUFs;
both memory and delay-based PUFs [51]–[59], [128],
[129], while that is not the case for mixed-signal PUFs.
This can be attributed to the difficulty of modeling
mixed-signal PUFs.
- Number of CRPs: A strong PUF should have many
CRPs, so the verifier may not have to reuse the same
challenge twice. Although, that did not help protect the
arbiter PUF [116], XOR arbiter PUF [117], feed-
forward arbiter PUF [118], and lightweight, secure PUF
[119] from modeling attacks [52], but it can make such
attacks less feasible within a reasonable time frame
[130], [131]. Some research papers suggested 30-bit
CRP sets (one billion CRPs) or higher immunize a
strong PUF for modeling attacks [132], [133]. Others
have recommended at least 64-bit CRPs [134].
• Accessibility
Another condition which a strong PUF must fulfill is
that even when an attacker can observe the input
challenges and read out their corresponding response
without restriction, it remains immune to modeling attacks
(to predict the unobserved responses). In other words, a
strong PUF does not need to restrict the access to its input
nor its output with a secure communication protocol. The
non-restricted accessibility can enable an attacker to test
several CRPs; however, having so many probable CRP
sets makes it infeasible for an attacker to test them all with
a reasonable time. Encrypting or hashing the responses is
usually done on-chip before sending it to the verifier side;
however, for strong PUFs, encrypting and/or hashing is
just recommended rather than essential [135].
• Anti-Tamper Sensitivity
A strong PUF should have a self-distracting quality
when an invasive attack is applied to its physical
components, in other words, the PUF responses after an
invasive attack should not be the same as before the attack.
III. EVALUATION METRICS OF PUFs
There are many metrics to evaluate PUFs in terms of
identifiability, reliability, and security [136], [137], [32].
Maiti grouped the parameters into three dimensions: device,
space, and time [138]. The device dimension includes
uniqueness, bit-aliasing, and probability of misidentification;
the space dimension includes uniformity and diffuseness (or
randomness); and the time dimension includes relia bility,
correctness, and steadiness. However, some metrics have
similar mathematical representations, like the uniformity
with randomness, and reliability with correctness [139]. Gao
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et al. [140] considered that the basic PUF metrics are
randomness, uniqueness.
• Randomness
The randomness of a response bit means that there is no
bias toward a logic ‘1’ or ‘0’, and the ideal case is when
the probability to obtain each value is 50%.
• Uniqueness
The uniqueness of a Pclass represents the average
distinctness of a PUF instance among others; it is usually
measured by the average of the inter-Hamming distance
(inter-HD) among response words of the tested PUF
instances aginst a challenge word. The ideal average inter-
HD is 50%, which simply means when a challenge is
applied to two different PUF instances, half of the
response word bits will be different.
• Reliability
The reliability represents the ability to reproduce the
same response against a challenge. Some researchers
measure a PUF reliability by bit error rate (BER), while
others measure it by intra -Hamming distance (intra -HD).
Intra-HD is the number of the flipped response bits when
re-applying the same challenge to the same PUF instance.
The intra -HD is sometimes measured under similar or
different ambient environments, such as temperature and
power supply conditions [140]. More intra -HD details are
in Section B.
This article tends to more detailed evaluation metrics that
are close to those of Maes [141], [142], based on inter-HD
and intra -HD.
A.Inter-Hamming Distance
Hamming distance between two responses (Y1,i,α , and Y2,i,α )
of two individual instances of a PUF construction against a
challenge Xi under the same environmental conditions (α) is
called the inter-distance between the two PUF individuals
(Dinter (X i )), or (Dinter ), for short, and at standard
1-2, α 1-2,i, α
conditions, it can be denoted as (Dinter
1-2, i
) or (Dinter
1-2
).
Noting that whenever the inter-distance is discussed, α
should be identical for both of the compared PUF instances;
therefore, the notation α although it usually appears within
the measured response as Y1,i,α , but it does not usually appear
within the inter-distance notation as (Dinter 1-2 ), as both Y1 and
Y2 are supposed to be performed at the two PUF chips under
the same environmental conditions α.
It is common to evaluate the inter-distance among several
non-repeated pairs (Npair) of PUF individuals within the same
Pclass . The inter-distance parameter characterizes the
uniqueness of a PUF instance among the other tested PUFs
within a Pclass .The average inter-distance (Dinter ave,i ) is based on
comparing the differences among responses of all tested PUF
pairing combinations within a Pclass . Thereby, Dinter ave,i
indicates the average uniqueness of the Pclass , which refers to
the relative uniqueness of any PUF individual among the
other individuals within that class. The sources of uniqueness
are not attributed to the uniqueness of the response, as the
response by itself is not necessarily unique. Still, the CRP is
supposed to be unique within the tested Pclass [49]. It is
important to emphasize that whenever determining the
average uniqueness of a Pclass , it is simpler to assume that any
change in α would affect all the PUF individuals equally,
thereby (Dinter
ave,i ) remains the same; however, this assumption
might not be precise and implies a margin of tolerance. The
average inter-distance (Dinter
ave,i
). The formulation is detailed in
Appendix A.
Definition 3: An evaluable (Pclass ) shows a high
probability of uniqueness if Dinter
ave,i is high, i.e.,
Pr( large Dinter
ave,i
) is high.
Noting that the qualifiers ‘large’ and ‘high’ are context-
specific [44], [49]. In general, a high probability refers to (1−
negligible). Such uniqueness is usually tested at normal
working conditions α. Based on Dinter ave,i , it is also common to
determine the average inter-distance distribution (μinter ) of a
Pclass , as detailed in Appendix B.
Alternatively, through simulation, it is also possible to
determine μinter by using only one PUF chip by randomly
varying some properties of its physical components. This is
commonly applied through Monte-Carlo randomness
simulation. The optimum value for μinter to achieve the most
randomness of the responses within a Pclass is 50%. This
means:
1) Among the tested PUF individuals within a Pclass against
a challenge, on average, half of the responses’ bits are
not correlated.
2) The (μinter = 50%) represents an unbiased uniqueness
and identifiability of the PUF individuals within the Pclass
[143]–[145].
3) For a single individual instance of a PUF construction,
the distance between two separately measured responses
against the same challenge is zero. A PUF designer
usually aims to attain such an optimal value as an
indication of reliability.
B. Intra-Hamming Distance
For an individual PUF chip, the reproducibility of a
response against a challenge can be measured by re-applying
the same challenge, under the same environmental
conditions (α) . Hamming distance D (Y1 ; Y2 ), in this case,
it represents the intra-distance. The distance notation
between the two noisy responses may refer to ironmental
conditions (α1 ) and (α2 ), then the distance notation
becomes D (Y1,α1 ; Y2, α2 ). Some of the faulty bits can be
ignored if the authentication is designed in a way that permits
VOLUME XX, 2017
a degree of tolerance, or an ECC unit is to be used to correct
such bits. In general, regardless of the differences in the
environmental conditions, the rate of the correct bits to the
total response bits is referred to as
reproducibility/steadiness/stability/ or robustness of the
Pclass . The average intra -distance distribution ( μintra ) is
determined by re-challenging the same PUF individual many
times to measure multiple D values at various environmental
conditions regarding Y1,α1 , which is measured at standard
conditions. The ideal value of D is zero, so as for its average
distribution, μintra .
C. Identifiability
Identifying a PUF chip instance among its siblings is
attributed to a CRP combination uniqueness. Neither the
applied challenge sets nor the generated response sets are
required to be unique.
Definition 4: An evaluable Pclass shows identifiability if a
response of a PUF of each tested instance is reproducible,
unique, and Pr (D intra
i
< Dinter
ave,i ) is high.
In other words, when applying the same challenge X i ,
under the same environmental conditions α to various PUF
individuals within a Pclass , and the measured noisy response
Yi,α of that PUF individual (for example, PUF 1 ) is distinct
among the responses of other PUF individuals within that
Pclass , then that PUF1 is considered identifiable among its
peers [44], [49]. Such a response can be an identity and
would usually have a CRP would have a high probability of
being unique within that Pclass . Noting that the identifiability
of a Pclass is usually tested at normal working conditions, then
α here refers to normal working conditions (voltage,
temperature, etc.). The term ‘normal’ working conditions
here may carry different indications depending on the PUF
targeted application and the used technology to construct the
PUF. For MOSFET-based PUFs, it may refer to a supply
voltage of 1 V, for example, and a temperature of 25 o C to
27 o C.
The assumption here is that the environmental effects on a
PUF unit when it generates its response against a randomly
chosen challenge Xi is the same against any other challenge,
then Dintraave,i,α remains the same for any Xi . The other
assumption is considering any change in α would equally
affect all the individuals within a Pclass , and therefore Dinter
ave,i
remains the same.
D Reproducibility and Authentication Tolerance
For a single PUF construction such as a PUF chip, the
uncertainty about the expected response to a challenge
should be significant when an attacker does not have access
to that PUF instance. For a single individual PUF instance,
the distance between two separately measured responses
(repeatedly) against the same Xi , under the same α, should
ideally be zero or should be small. This can be denoted as:
Dintra
i = D (Y1,α1 ; Y'1,α1 ).
Definition 5: An evaluable Pclass shows reproducibility if:
Pr ( small Dintra
i
) is high
Amid added noise and random errors, a PUF usage relies on
measuring the response, which implies a degree of error
tolerance [49], [44]. In some cases, an error-correcting code
can be omitted. In such a case, only a predefined number of
bit errors is accepted; i.e., if the allowable Hamming distance
as a predetermined error threshold (∆) is not exceeded, then
the PUF authentication is declared as ‘pass’. If ||Yi −Ri || ≤ ∆,
then the authentication is considered successful. This implies
ignoring the errors if their value is less than the
predetermined threshold (∆), without needing to use any
helping data (Wi ) to correct those errors; where (i) is the CRP
index.
The permitted tolerance threshold (∆) is related to the
following four parameters [50], [146], [147]:
1) BIT REJECTION RATE (BRR)
The ratio of the non-reliable bits to the total number of
response bits. Such non-reliable bits are usually ignored.
2) BIT ERROR RATE (BER)
The ratio of the fa ulty bits to the total number of response
bits.
3) FALSE ACCEPTANCE RATE (FAR):
The probability for a biometric security system to incorrectly
accept an access attempt by an unauthorized user.
4) FALSE RECOGNITION RATE (FRR)
The probability that a biometric security system will
incorrectly reject an access attempt by an authorized user. It
is determined by dividing the number of false acceptances by
the number of authentication attempts.
E. PUF Physical Unclonability
The physical unclonability of a PUF system within its class
can be defined as:
Definition 6: An evaluable Pclass shows physical
unclonability if it is hard to control its physical creation
procedure.
This definition is also applicable to the
mathematical/logical unclonability if it is hard to find a
precise mathematical model that can emulate the physical
functionality of a PUF structure.
Hypothetically, if the fabrication process first created the
(original) individual (PUF1 ) and attempted to create the
forged individual (PUFclone), then the clone can be checked
by an inter-distance rule. The physical clonability can be
tested in the form of inter-Hamming distance Dinter 1-clone,i, α
between the responses of the Y1,i,α , Yclone,i,α of both the
original and the cloned PUFs. In this test, responses are
measured against the same challenge (X) indexed by (i),
under the same environmental conditions α. Detailed
formulations of the inter-distance approach to check
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unclonability are in Appendix C.
F. PUF Anti-Tamper Sensitivity (Tamper Evidence)
One of the approaches to the study a PUF chip is by
accessing the internal structure of the chip. If the responses
are no longer the same, then the chip has the advantage of
being anti-tamper sensitive. The tampred chip is considred
as another chip that is clone to the original chip. In other
words, if the genuine PUF (before the physical invasion), is
denoted as PUF1 , and its noisy response against a challenge
word Xi was Y1, i , after the invasion, its would produce a
different output response Y2 , and the chip can be regarded as
another one, that can be denoted as PUF2 or PUFclone .
A convenient approach to study the tamper effect on a PUF
is usually made by comparing the output response before and
after the tamper. That is usually done by determining
Dintra
1-2,i,α between the noisy response (Y1,i,α ) of the untampered
(PUF1 ), the response after tampering (Y2,i,α). The reason
behind applying the intra -distance checkup rather than the
inter-distance one is because it is assumed that the verifier
side does not know about the tamper attempt and would still
consider the PUF as if it the sam e one. By extending the
tamper concept discussed in [49], then it is possible to test
the anti-tamper sensitivity, as: Dintra
1-2,i,α =||Y1,i,α − Y2,i,α ||. At
standard conditions (α), the equation can be written as
Dintra
1-2 =|| Y1 − Y2 ||, for short.
There are three possibilities for a tamper sensitivity of a
Pclass :
1) A very good tamper evidence indication is when (Y 2 ) is
very much different from (Y1 ), in other words, both are
less correlated to each other, which leads to a very high
intra-distance (Dintra
1-2 ) among their responses. In other
words, if: Dinter intra
a ve < D1-2 . That means (PUF2 ) is distinct, not
only from (PUF1) but also from the entire (P class ). The
larger the Dintra
1-2 is, the more anti-tamper the Pclass would be.
2) A good tamper-wise security indication is when (Y2 )
differs from (Y1 ), but not much. In other words, there is
still some correlation between (Y2 ) and (Y1 ); which leads
to a medium (Dintra 1-2 ), in other words;
If: Dinter
ave ≤ D intra
1-2 ≤ Dinter , ∃1 ≤ i ≤ Nchallenge
, then: PUF2 ≠ PUF1; however, still PUF2 ∈ Pclass
or Pr (Dintra
1-2
) = 0 for at least one challenge (Xi ) is high.
3) A bad tamper-wise security indication is when the
response (Y2 ) is very nearly similar to (Y1 ) in term of intra -
distance (Dintra
1-2
) such that;
If: Dintra
1-2, i = 0 , ∀1 ≤ i ≤ Ncha , then PUF2 (Xi ) ≡PUF1 (Xi ).
Alternatively, in less restricted mode:
If: Dintra
1-2, i = 0 , ∃1≤ i ≤ Nchallenge , then: (PUF2
(Xi ))≅(PUF1 (Xi )), where (N challenge ) represents the number
of the tested challenges. In both last cases (2 and 3), it is
concluded that the tested PUF design (the entire Pclass ) is not
 sensitive enough against tampering, in other words, it does
not have a tamper evidence quality [44].
Detecting the cloned PUF depends on the precision of the
response measuring and the permissible tolerance range (∆),
which is based on the chosen values of the FAR and the FRR
of the authentication process. Using a less tamper sensitive
PUF system or adopting a high FAR by the verifier means
allowing more tolerance. Some systems might generate Y2,i
that is still similar to Y1,i , then with the help of W1,i , the
authentication would be still possible, and the verifier can be
deceived. It is safer for a PUF to include a tamper-evidence
feature, which is considered a self-destructive ability, and
such a PUF is also called fragile PUF [148].
G. PUF Unpredictability (Mathematical Unclonability)
Beside physical unclonability, a secure PUF must have an
unpredictability quality, i.e., the unobserved responses are
supposed to be sufficiently random [49]. Mathematical
cloning tends to be an easier approach of PUF cloning, where
an attacker does not create a physical clone of the PUF, but
an algorithmic (or behavioral) clone model. An attacker can
apply black box testing approaches to design such a
mathematical model, usually through applying ML
algorithms on a CRPs training set. Obviously, the larger the
training set, the more likely the ML is to succeed in modeling
the PUF.
At the testing phase, when the mathematical clone model
is tested against a new challenge among the CRPs testing set,
it is common to calculate Hamming inter-distance between
the generated response string of bits and the original
response string from the testing set, as in Appendix C.
H. Randomness (Entropy) Tests and Accreditations
A single number by itself cannot be described as random, but
a series of numbers can show randomness; thereby, to
maintain unpredictability, the CRP lists should fulfill the
following conditions:
1) CHALLENGE LIST RANDOMNESS
The verifier is supposed to adopt an adaptive random
challenge selection approach to achieve unpredictability of
the next challenge.
2) RESPONSES LIST RANDOMNESS
Responses to different challenges must be independent.
That does not only imply the random correlation between
independent responses, but it also implies there is no
historicity in the PUF, i.e., no previous challenge or response
can affect the next response. Response bits should have a
degree of randomness to protect the PUF against modeling
attacks; thus, responses of many PUFs were tested using
statistical test suites for random a nd pseudorandom number
generators.
There are various well-known randomness testing software
suits, also called test batteries. Marsaglia presented his
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statistical test suit (Diehard) in 1995 [149], the national
institute of standards and technology presented its statistical
test suit (NIST STS) in 2001 [150], L’Ecuyer and Simard
presented their (TestU01) in 2007 [151].
In general, the NIST STS kit is currently the most standard
randomness test battery, and it showed that the responses of
some PUFs are sufficiently random [152]–[154]. However,
the relevancies of some tests are debatable [155], [156], and
the kit was updated in 2008 [157], 2010 [158], and is still
under revision, development, and optimization [159], [160],
[155].
It is worth remarking that, if the PUF response is intended
for cryptographic applications, more tests are to be carried
out on the entire cryptographic module in order to improve
its protection across four levels, according to ISO/IEC 19790
[161]. Furthermore, the module is to be accredited according
to the federal information processing standards (FIPS) 140
[162], [163].
3) LARGE NUMBER OF UNIQUE CRPS:
The PUF is supposed to have very large CRP sets. Otherwise,
the attacker can try all possible challenges, then records their
responses, then no secret response key is left undisclosed.
The number of CRPs is usually, but not always, exponential
to the of the components used to build a PUF [43].
Data randomness is usually assessed according to the
entropy concept. Entropy is a measure of the uncertainty one
has about the outcome of a random variable distributed
according to a given distribution; it also represents the
unpredictability of a secret random variable [44]. There is
Shannon’s entropy [164], which was formulated further by
Cover et al. [165], and a less minimum entropy margin
proposed by Rényi [166], which Dois discussed further
[167], [168].
I. Correlation Among Bits
Neighboring cells must not influence each other to avoid
security threats. Correlation between cells would reduce the
number of possible combinations and thus would increase
the risk of successful brute-force attacks. To check whether
a correlation exists between neighboring response bits
(Rn , Rn-j ), with a la g of (j), and an autocorrelation function
(AC ), then: ACXX (j)= ∑n=N
XX n=1 R n R , where (N) is the total
n-j
number of response bits.
If ACXX (j)=1, or (−1), then the data at lag (j) are
completely correlated; while, if ACxx (j)=0, then the data are
completely uncorrelated [50].
J. Correlation Among Chips
If the layout of an electronic chip is not done carefully, the
output responses of some cells within a PUF system may
depend on the positions of these cells. In such a case, the cells
tend to generate some specific response values, which leads
to a security threat, since knowing the output of one chip
makes it easier to guess the response of other chips within
the Pclass . PUFs usually generate each of their response bits
individually, the correlation among chips in the form of inter-
Hamming Distance (Dinter i ) can be determined similarly. If a
response string of bits of a PUF chip is considered as a
reference, then the mean value of all Hamming distances to
the responses of the other tested chips against the same
challenge (Xi ), and under the same environmental conditions
(α), can be represented as (Dinter ave,i ). The optimum target of
(Dinter
a ve,i ) is 50%, which means there is no correlation among
the tested PUF chips within that class [50]. However, some
tolerance is usually accepted, especially when a PUF
generates a large number of response bits, such as 64 or 128,
then having (Dinterave,i ) of (50 ± 2)%, for example, would not
help an attacker to model the PUF. After all, the adoption of
a specified tolerance rate depends on the nature of the
application.
K. One-Wayness
In computer science, a one-way function is defined as a
function that is easy to compute on every input, but hard to
invert to determine each input [37], [38], [49]. The terms
‘easy’ and ‘hard’ here are in the sense of computational
complexity, especially as polynomial-time problems. A
function is usually considered a one-way function if for a
given input challenge (X1,i,α ), indexed by (i), under
environmental conditions (α), it is easy to measure the noisy
output response (Y1,1,α ), but for a given response (Y1,2,α ), it
is hard to predict the input challenge (Xpredict,2,α, ) as an
inversion of the response:
Xpredict,2,α = inv (Y1,2,α )
In other words, the inversion has a negligible probability
if:
Pr( || X1,2,α -Xpredict,2,α || = 0 ), for more than one (i)) is low,
then the PUF function can be considered as a one-way
function until proving the opposite by figuring out an
inversion model.
IV. PUF USAGE PHASES AND COMMUNICATIONS
In order to understand the PUF usage phases, first it is
necessary to distinguish authentication (or verification) from
identification of an object. In case of identification, the
system recognizes an object, such as a smart card, by reading
a serial number stored on a non-volatile memory (NVM), the
system then matches that ID against any archived ID code.
Whereas an authentication process is based on a comparison
of a received biometric pattern with a pattern archived since
the training (or enrolment) phase. For each of the
identification and authentication cases, the system usually
adopts some FAR and FRR to decide whether the similarity
is sufficient or not. The usage of a PUF consists of two
phases, enrollment phase and authentication phase [169].
A. Enrollment Phase
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The enrollment phase, also known as learning or training
phase, should be performed before releasing the PUF to the
end-user, and it can be briefed as:
1) Assigning an ID to identify each tag/smart card chip,
then archive it within a database on a trusted server.
2) The PUF entity is challenged with a challenge word
indexed by (i) as Xi , to generate output response data
(Ri ), and an error-correcting or helping data (Wi ). In
most PUFs, Wi is stored on-chip in an NVM, to be used
later during the authentication phase to correct the noisy
response Yi and generate a corrected response (Si ).
Storing Wi on-chip poses a security threat. A safer
approach is to store Wi on a secure server, either of the
verifier’s side or as an independent third party,
especially in the case of an untrusted verifier [50]. The
verifier can correct the received noisy response Yi using
Wi to determine the related corrected response (S i ). The
archived number of CRPs would depend on the
application. For example, for a PUF that is embedded
into a credit/debit card, the verifier should test and save
many CRPs. Otherwise, if that PUF is embedded in an
RFID tag within an on-shelf item in a supermarket, then
such a verifier’s database would only need to include
one or a few CRPs if considering the possibility of
returning the purchased item, then resell it for multiple
times.
Due to noise during the enrolment phase, the reference
response (R i ) is measured against a challenge (Xi ) for several
times. Later, those independent challenges (X1 ,…, X ),
Ncha
and their corresponding reference responses (R1 ,…, R )
Ncha
are saved in the verifier database, where (Ncha ) is the
maximum number of possible CRP sets. For example, if the
number of the challenge bits (n = 64), then the number of
possible CRP sets is: Ncha = 2 n = 2 64 .
For each Xi , it is expected that the measured response Yi
during the verification phase would be slightly different from
Ri , which was measured during the enrolment phase. That
relation can be represented as: Y=R+E, where (E) represents
the error, and it is assumed to be zero during the enrolment
phase. In this article, X, R, Y, and E are digital numbers of n
bits.
During the verification phase, to improve the reliability of
the response detection, the device manages the difference
between Y and R via a signal processing function (G):
Si =G(Wi , Yi ), where (Wi ) is any form of helping data, which
assists error-correction. When: Si =Ri , then the authentication
is successful.
To sum up, the verifier’s database must archive the PUF chip
ID (i.e., serial number) linked to the following data lists:
- Challenge X: X1 ,…, X N
cha

- Response R: R1 ,…, R N
cha
- Helper data W: W1 ,…, W N
cha
B. Authentication Phase
During the authentication phase, Si is compared to R i , or if
no helper data are used, then Yi can be compared to R i
instead. The helper data can either be stored on NVM at the
PUF side [170] to help the ECC to correct Yi to R i , or
externally on the server [171], where Yi is
corrected/compared with R i . The latter scenario allows Yi to
serve authentication purposes only, unlike the first approach,
where R i for authentication and as a cryptographic key. It is
also possible that the server sends the archived helper data to
the ECC on the PUF chip, to generate Ri for
authentication/cryptographic key purposes [171]. In either
way, if the correction is done at the PUF side, it is also
possible to attain integrity by hashing R i and send it to the
server, which has also archived the hashed R i since the
enrollment phase, to compare with. There are several
authentication protocols for strong PUFs [172] and weak
PUFs [173]–[176]; however, the authentication protocols are
out of the scope of this article. Here we mention a basic
authentication protocol, considering that the verifier side is
trustworthy and immune from external and internal attacks.
However, the communications between the PUF at a client-
side and a bank, for example, as a verifier-side, are still to be
encrypted [177]. The serial number of card/tag is usually
stored on magnetic strip/NVM. It is equivalent to the
ID/username in internet terminologies, while the PIN code
represents the password.
If a smart card is not tapped on the card-reader machine, it
does not utilize the embedded RFID feature; instead, the
client inserts the chip contacts into a card-reader and enters
a PIN code, which adds more security, as it proves that the
client knows the secret PIN stored on the NVM. The card-
reader sets local secure communications with the smart card.
FIGURE 4. PUF authentication phase of an object with a trusted verifier.
VOLUME XX, 2017
Next, the card-reader uses a public or symmetric key, which
is read from the NVM, to encrypt/decrypt the
communications with the verifier side.
For a PUF-based contact/contactless smart card/RFID tag,
the underlying authentication protocol between the user and
the verifier sides illustrated in Fig.4 can be briefed as
follows:
User: The authentication phase starts when a package that
contains a PUF device is scanned by an RFID scanner at a
point of sale, for example. Similarly, for financial cards, the
reader can be an RFID scanner or a card-reader. The ID is
usually embedded within an RFID tag/smart card in various
forms [50]:
- If the ID is stored outside the chip, then it is to be read
from a magnetic strip or barcode.
- The ID is stored on-chip in an NVM, which is the case
of most RFID tags and smart card chips. The ID can be
generated using another on-chip PUF. The claimed ID is
sent to the verifier side; it would mostly be encrypted.
Verifier: The received ID leads the VS to access the
related CRP list, which was stored previously (during the
enrollment phase) on the secure server. The VS can then
randomly choose an index (i) then send the indexed
challenge (Xi ) to the PUF, where the archived CRP list
indexes each CRP and its helper data as (Xi , Ri , Wi ).
Key-generating PUFs usually have their helper data stored
on-chip, such as an ECC. Alternatively, a PUF can have its
helper data (Wi ) received along with the challenge from the
verifier side. Authentication-only PUFs can store their helper
data on the verifier’s side, which processes the response.
This latter approach is safer and reduces the cost of the chip
in terms of area, power and complexity.
User: The user reader challenges the PUF embedded
within the submitted smart card or the RFID tag, with
challenges Xi , measures (possibly noisy) response Yi , then
sends it to the verifier.
 Verifier: Due to the environmental driven errors during
the verification phase, the noisy measured response Y i
usually differs from the referenced response R i which has
been measured during the enrolment phase. Therefore, even
the simplest authentication protocol needs to include the
following basic steps:
• To eliminate the computational time of non-correctable
responses, the verifier may first determine whether
||Yi −Ri || ≤ ∆, where (∆) is the predetermined error
threshold, upon which the VS sets the FAR and FRR
limits, and ||Yi −Ri || is the difference among bits of the
response during verification (i.e., authentication) phase Yi
to the response measured during enrolment phase R i . This
difference is called Hamming distance (HD, or D for
short), and since the test in the above case involves all
response bits of both phases, so it is just like comparing
the entire response of two different PUF instances, then
such a distance is considered as inter-Hamming Distance
(Dinter
i,α ) [50].
• When the difference ||Yi −Ri || exceeds (∆), then Yi is far
from being correlated with R i . If this difference (or the
error) is uncorrectable nor ignorable, then the verifier
(usually software) denies the authentication. While, if the
difference is less than (∆), then the verifier approves the
authentication claim.
When ||Yi −Ri ||≤ ∆, the verifier calculates the corrected
response Si using the helper data Wi of the measured Yi, as
Si =G(Wi ,Yi ), then the verifier checks whether ||Si −Ri ||=0;
i.e. (Si =Ri ); if not, then the authentication is denied, else it
is successful.
To maintain a high-security level, the used (Xi , Ri , Wi )
templet can be deleted from the database, so it may not be
used again. After a successful authentication phase, an
encrypted access approval code number is sent to the user,
sometimes by using Yi as a session encryption key. On the
user side, the smart card, for example, uses its PUF session
response Yi to decrypt that permission code. The PUF design
should make sure that the generated response Yi , which is
sent to the verifier side, is stable during the authentication
phase. If the transaction requires exchanging secret messages
between the smart card and the verifier (e.g., for a financial
transaction), a secure authenticated channel can be set
between the verifier and the card using the response Yi as an
encryption key for the transaction session.
C. Untrusted Verifier
There are usually two sides of the transaction: 1) an end-user,
which is to be verified, and 2) a verifier side, a bank, for
example. There are various verification protocols to protect
the verifier side from outsiders’ frauds and MIT attacks
[178]. On the other hand, the user side is only protected by
chip-and-PIN, which was proven to be breakable [179].
VOLUME XX, 2017
Besides, there is less protection for the user-side (i.e., the
client) against insider frauds within the bank. To solve that,
a bank might not have all the database lists; instead, some are
kept at another independent 3 rd party server. For example, the
3 rd party server can have (ID, i, Wi , Ri ) lists, while the verifier
server would only ha ve (ID, i, Xi ) lists. When the verifier
receives a claimed ID from the user-side, it arbitrarily
chooses a one-time verification index (i), then sends the
related challenge word (Xi ) to the user-side. At the same
time, it sends the user ID and the chosen (i) to the 3 rd party
server, asking for the related helper data Wi . When the
verifier gets back the non-corrected noisy response Yi from
the user-side, it can correct it, then sends it to the 3 rd party
server, which compares it to Ri and approves the
authentications. In this case, both the user and the verifier are
protected and responsible at the same time. Exactly as having
a safe banking box, which cannot be accessed without
inserting both the client’s and the bank’s keys, so any party
cannot disclaim the process. However, discussing various
authentication protocols is out of the scope of this article.
V. SOURCES OF VARIATIONS
All known electronic PUFs are based on the unintentional
variations during a fabrication process. The terms
‘mismatch’ and ‘variation’ are interchangeable throughout
this article. Fabrication variations can lead to distinct
responses among multiple PUF individuals within a Pclass.
This is an essential quality for identification purposes, and
such variations are permanent. On the other hand, variations
in the working environment, such as voltage and
temperature, are temporary sources of response variations.
A. Sources of Permanent Variations
Unintentional variation in MOSFET properties wafer-to-
wafer and across the wafer (die-to-die) influence
connections, such as the variations in metal thickness due to
damascene process (e.g., copper polishing), is around (10-
20)% and the variation in the threshold volta ge (VT ) is
around 10% [180], while the variation in dielectric thickness
at wafer level is around 5% [180], [181]. There is a lso an
example of an arbiter PUF which is based on the variations
in propagation delay. It has reported an inter-chip (die-to-
die) response variation of (17-23)% for the regular arbiter,
and (28-38)% for the feed-forward arbiter PUF [116], such
variation depends on the die and the wafer locations.
Operating a MOSFET-based PUF circuit at the sub-threshold
voltage level allows the distinct properties of the circuits to
play a bigger role so that a PUF circuit would generate a
more distinctive response [182].
In CMOS-based PUFs, there are two main sources of
mismatches; permanent and temporary [183], [184], [50].
The permanent mismatches are attributed to variations
during fabrication. From the fabrication view side, there are
two main types of variations: global/systematic variation
sources and local/stochastic variation sources.
A.1. Global Mismatch Sources
These variations are attributed to inaccuracies in the
production process. They can be chip-to-chip, wafer-to-
wafer, and lot-to-lot variations. Approximately, 20% of the
variability is attributed to production inaccuracy [39], [50].
Global/ extrinsic process variations are caused, for example,
by temperature gradients across the wafer during annealing,
or process variations during photoresisting development,
etching, or photolithographic variations. Systematic
variations, light density and focus variations in the
lithography system, refers to a systematic offset applied to a
group of adjacent layout patterns. For example, over the
entire wafer, threshold voltage gradients can occur and may
converge toward a particular value, depending on the
position/ direction of the MOSFET [50].
A.2. Local Mismatch Sources
These variations are attributed to random (stochastic)
variations within a chip. Some variations during the
fabrication process of MOSFET devices are inevitable, such
as variations of charge, material, non-uniformity of
interfaces, and granularity of fabrication materials [185]. In
general, the local mismatches are the most vital for most
electronic PUFs, which depend on differences among multi-
paths within a chip, where bits propagate [186]. Local
variations of nano MOSFET processes can be classified as
systematic local process variations, and statistical local
process variations [183].
1) SYSTEMATIC LOCAL PROCESS VARIATIONS
The primary source of systematic local process variations is
attributed to the low resolution of the lithography process.
The imprecision issues of lithography are decreased by
resolution enhancement techniques (RETs), such as: 1)
applying phase information to the ma sk, which is called
phase shift masking (PSM); 2) optimizing the light
illumination angles, which is called mask off-axis
illumination (OAI); 3) controlling the illumination's
polarization, which is called source mask optimization
(SMO); and 4) optimizing the mask pattern, which is known
as optical proximity correction (OPC) [187]–[191]. In order
to understand the importance of RETs, it is worth mentioning
that immersion lithography and OPC techniques enable
foundries to produce 45 nm nodes using 193 nm steppers,
mainly by using directional pattern effects and mask shadow
techniques [183]. Local systematic variances are caused by
lithography issues, such as light phase shift, layout-mediated
strain, and well proximity. Although new lithographic
developments have
narrowed the local systematic variances of lithography to
some extent, RETs still preserve their importance to reduce
local systematic variations. For instance, even when using
extreme ultraviolet lithography (EUL) with a laser beam
wavelength of (13.4 nm), still OPC is needed to enhance
pattern pitch and direction.
VOLUME XX, 2017
The introduction of strain silicon to move silicon atoms
farther apart reduces the atomic forces that interfere with the
movement of electrons through the transistors and thus
improving the mobility, which enhances the chip
performance and lowers the power consumption. Therefore,
electrons can move faster, allowing strained silicon
transistors to switch faster [192]. Silicon straining
technology has begun with 90 nm technology, which has led
to more variation; as in addition to lithogra phy-related
geometry variations, additional variations have been added
due to spacing, distances to shallow trench insulation, and
contact positions. Using regularized design and dummy
features can significantly reduce the impact of systematic
variabilities [183].
2) STATISTICAL LOCAL PROCESS VARIATIONS
These types of local mismatches are also known as random
local process variations and usually attributed to stochastic
differences at the atomic level. Up to date, it is not possible
to fully control the process at the atomic level. Moreover, the
smaller the minimal feature size, the higher the influence of
each atom. Fluctuations in the physical thickness of a gate
oxide present a significant source of local mismatch. When
a transistor is scaled-down, the thickness of the gate oxide
can be only several atomic layers with a typical
semiconductor-to-insulator interface roughness of around 1–
2 atomic layers. The variance of such a small thickness can
be as high as 50%. [193]–[195]. That entails variation of
carriers’ mobility, which varies the gate current. Sub-100 nm
transistors have different mismatch sources which vary with
the type of the transistor. Some examples are:
- In polysilicon gated transistors, the mismatch is usually
caused by the variation (fluctuation) in doping
concentration in the gate region, unlike metal gate
transistors with a high-k dielectric material.
- In fully depleted silicon on isolator (SOI) transistors, the
threshold voltage varies with the body thickness [196];
therefore, when comparing with the MOSFET, a
MOSFET with a metal-gate and high-k insulator would
have less threshold voltage fluctuation [197].
In planar bulk MOSFET, there are three major random
local mismatch sources [50]:
1) Random discrete doping (RDD)
Random discrete doping (RDD) or random dopant
fluctuation (RDF) is originated during ion implanting and
redistributing during high annealing temperatures. RDD is
the main source of mismatch (variability), mainly at channel
region. However, the 22 nm node technology and beyond
have thinner bodies and lightly doped chann els, which
reduces RDD effect dramatically [198], [195].
2) Line edge roughness (LER), and line width
roughness (LWR)
Fluctuations of the edges across a patterned line, such as a
gate, a fin, or a nanowire line, are inevitable; the LER
represents the length variation, while the LWR represents the
width variation. Both LER and LWR are caused by
tolerances in materials and tools used in lithography
processes, mainly through photoresist process (jaggedness,
striations, and rippling) and etching [196], [199], [195],
[200]. The granularity of the photoresist, with other factors,
introduces unavoidable LER in the gate [183].
3) Poly-gate granularity (PGG)
It refers to the effect of poly-silicon grain boundary
distribution on the threshold voltage. When a transistor has a
polysilicon gate, then PGG is an important source of
variation (or mismatch). This variability is attributed to the
doping non-uniformity (fluctuation) when having a rapid
diffusion. The granularity becomes a significant source of
variability when the grain size becomes comparable to the
transistor feature size (L/W) [196], [201], [202]. In bulk
MOSFETs, the doping concentration in the polysilicon gate
region plays an important role, where the surface Fermi-level
pinning at the poly-Si grain boundaries dominates the poly-
Si.; while that is not the case in a metal gate with high -k
dielectric insulation material. It is concluded that for a PUF
device to have a larger PGG effect as a source of variance,
using a poly gate is recommended over the metal gate.
Various poly-Si based transistors for PUFs were proposed to
enhance uniqueness [203]–[205].
In general, for a planner transistor, RDD usually
dominates the mismatching behavior. However, RDD and
PGG induced competing variabilities at 35 nm and 25 nm
channel lengths. For shorter channel lengths, if the LER
could be scaled according to the International Technology
Roadmap for Semiconductors (ITRS) as 1.2, 1, 0.75, and 0.5
nm for the 35, 25, 18, and 13 nm channel length transistors
requirements, then RDD becomes the dominant source of
variability of the threshold voltage (VTH ). However, if LER
remains at (LER≅ 4 nm), then LER becomes the dominant
source of induced potential variabilities, which pins the
channel due to the very high concentration of mobile carriers
(especially the electrons in n-MOSFETs) below the 25 nm
channel length [206], [185]. Both RDD and the interface
roughness introduces significant statistical variability in the
gate leakage current [183]. With the further reduction of the
gate oxide thickness and doping concentration at the
interface as low as possible, the impact of the surface
potential pinning at the poly-Si gate grain boundaries will
increase. The use of poly-Si micro-grains can reduce the
fluctuations, as variability will be reduced if the
characteristic size of the grain is much smaller than the
device dimensions; thus, the associated potential fluctuations
will be self-averaged in the device. However, the best
approach would be using amorphous poly-Si or a uniformly
structured metal gate [206]. Using a metal gate eliminates the
VOLUME XX, 2017
PGG variability; but, it introduces both high-K granularity
(morphology) and work-function variations instead [207],
[208].
Materials, technologies, and transistor dimensions
contribute to variation; therefore, there is no absolute answer
to the question. ‘which transistor type has the most statistical
local variations?
In general, to obtain a Pclass where the PUF individuals
have high identifiability (uniqueness), it is recommended
that the designers and the manufacturers to contradict any
variation-limiting approach. The manufacturers can apply
PUF-aware OPC to improve the uniqueness of the PUF
individuals with the Pclass [209], [210]. Scaling down the
transistor feature size can also contribute to the uniqueness
of a PUF response. The 45 nm-based PUFs would have more
variations and thus uniqueness than 65 nm -based PUFs, and
the 28 nm PUFs would have more variations and uniqueness
than 45 nm PUFs [211]. In general, as the MOSFET device
scale goes down, as more the intrinsic variation of a device’
parameters would be [211].
B. Sources of Temporary Variations
Temporary mismatches are also classified as reversible
mismatch sources and irreversible mismatch sources.
1) REVERSIBLE MISMATCH SOURCES
The environmental conditions of a PUF at an authentication
time would differ from those at the enrollment phase, which
would vary the generated response. Such a response
variation is usually considered an error, and the collective
effect of all the environmental variations on a PUF is
considered a temporary source of error. These variations
happen during the authentication phase, when the
environmental conditions vary, such as of the supplied
voltage (VDD) and/or the ambient temperature, such
variations may alter the response bit(s). That may have a
significant impact on the reliability of the PUF, particularly
since it is not possible to control the environmental factors
on the verifier side during the authentication phase, as can be
done in the laboratory during the enrollment phase [31].
2) IRREVERSIBLE MISMATCH SOURCES
The properties of an electronic device vary during the device
lifetime, and such variations are usually referred to as
transient variations. Such variations are not temporary, nor
exist at the manufacturing time, and are not even constant
throughout the lifetime of the object. For example, an
electronic device ages throughout its lifetime, and the
properties of the device continue to change gradually.
Accelerated aging experiments were performed on a PUF
ring oscillator based on a 90 nm field-programmable gate
array (FPGA), and the results showed a significant aging
effect on the response, which reduces PUF reliability .
However, aging did not affect the randomness, which
maintained the PUF uniqueness [212], [184]. Other
accelerated aging experiments were applied on various 65
nm based PUF chips to measure the change in negative bias
temperature instability (NBTI). The results showed that
among the tested memory-based PUFs, SRAM and bus-
keeper PUFs are less affected by aging than latch and DFF
PUFs [213].
C. Temperature effect on MOSFET threshold voltage
and inversion charge
The electronic charge which occupies a MOSFET’s gate
surface can cause a shift in flat-band voltage (Vfb ) [190].
However, as the applied voltage is varied, the Fermi energy
at the oxide-semiconductor interface changes a lso and
affects the occupancy of the surface states. Considering that
(∅st ) is the surface potential at the threshold voltage level
(VT ), then:
Where (Cox ) is the oxide electric capacitance, (εs ) is the
kT NA
∅st = ±2 ln (1)
q ni
√2qNA εs |∅st |
VT = Vfb + ∅st ± (2)
Cox
silicon permittivity, (k) is Boltzman’s constant, (T) is the
temperature, (q) is the electron charge, (n i ) the intrinsic
carrier concentration, (N A ) is the acceptor doping
concentration in p-substrate, which is replaced by (ND ) as
donor doping concentration in case of n- substrate. For (1)
and (2), the positive signs are for p-substrate and the negative
signs for n-substrate. For p-substrate, VT in (2) becomes
lower at low temperatures [190]. At the inversion region of
a MOSFET, the total capacitance (when the drain and the
source are shorted externally) equals the series combination
of gate poly-silicon capacitance (Cpoly ), the oxide electric
capacitance (Cox ) and the inverted channel capacitance
(Cinv ). If the applied voltage at the gate is (VG ), and the
threshold voltage is (VT ), then:
Qinv = Cox (VG -VT ) (3)
εox
Qinv = (VG -VT ) (4)
tox
The channel charge (Qinv ) increases at low temperatures,
and this produces a rise in the total capacitance of the series
combination (Cpoly ), (Cox ), and (Cinv ) [190].
VI. UTILIZING FABRICATION VARIATIONS FOR PUFs
This section discusses some major variations which occur
throughout the fabrication process of a MOSFET-based chip.
These ra ndom variations create distinct parameters for each
MOSFET. A parametric variation is usually a source of
disturbance for most applications, while for PUFs, it can be
an excellent source of entropy to generate device-specific
response bits [8]. This section discusses the intrinsic
variations’ effects on the threshold voltage (VT).
The initial threshold voltage value of a MOSFET at zero-
bias (VT0 ) depends on the flatband voltage, the bulk
potential, the oxide electrical capacitance per unit area (C ox ),
and the depletion layer charges. The variation in the initial
threshold voltage (∆VT0 ) plays a vital role in forming
distinctive properties for a PUF chip. The polarities of VT
and VT0 are positive for an n-MOSFET and negative for a
positive- channel metal–oxide–semiconductor field-effect
transistor (p-MOSFET). In both MOSFET types, there is a
roll-off voltage that contributes to │∆VT0 │, which reduces
│VT0 │. For generic (non-PUF) applications, chip designers
try to reduce the intrinsic variations by taking into
consideration some factors, which are briefed here at
technology, layout and mask, and schematic levels. The
introduction of strained silicon since 90 nm CMOS
technology and below enabled the electrons to move faster,
which ultimately made MOSFETs switch faster.
Straining the silicon results in better MOSFET
performance and lower energy consumption. However, it
causes more deterministic, or systematic variability in a
MOSFET’s parameters, such as C ox , MOSFET channel
width (W), and charge carrier mobility (µ); μ can be defined
as electron/hole mobility for the n/p channel as (μ n /μp ) [214].
Statistical variability is attributed to random variations in
parameters like VT0 , μ, Cox , L, or W. The variation of VT0 is
the most prominent parameter and is primarily ascribed to
RDF, surface roughness, oxide charge, and LER [189]. The
variation in VT0 depends mainly on RDF, as the dopant
concentration can vary up to ±10% [215].
In this article, fabrication variations of a MOSFET are
studied at technology, layout and masking, and schematic
design levels.
1) VARIATIONS AT TECHNOLOGY LEVEL
The variation of t ox gained more importance as the
technology shrinks down. Using high-k insulators with
larger physical t ox abates its influence on variation. Unlike
tox , the effect of the oxide charge on VT value does not
represent a significant factor in modern fabrication
technologies, especially when a MOSFET works at strong
inversion mode [216]. Let K’=µC ox (W/L), then an RDF of
10% with 5% variation in t ox can lead to variation of 100 mV
in VT0 , 15% in K’, and 5% in the source-bulk (C SB) and the
drain-bulk (C DB) junction capacitances [217]. SOI
technology mitigates RDF, but an ultra -thin body SOI
MOSFET raises more uniformity concerns. The high -k
insulated metal gate technology reduces RDF but creates
metal gate granularity (MGG), which becomes among the
major sources of ∆VT0 in scaled bulk-MOSFETs [218]. In
general, a MOSFET fabrication technology tends to decrease
│∆VT0 │by: 1) strict control over doping fluctuation of the
source and the drain; 2) strict control over the critical
geometrical dimensions, such as the gate length and width of
the MOSFET; 3) scaling up the gate insulator thickness; and
4) scaling up the junction depth [219]. Choosing a MOSFET
manufacturing technology with less control of characteristics
can better serve chip authenticity applications.
2) VARIATIONS AT LAYOUT AND MASKING LEVELS
Low lithography resolution is a major source of systematic
local process variations. Such imprecision is treated with
resolution enhancement techniques, such as phase shift
masking by adding phase information to the mask, off -axis
illumination to optimize the angles of light illuminating the
mask, source polarization to control of the polarization of the
illumination, source mask optimization, and OPC to
optimize the mask pattern [220], [221], [187], [190], [189],
[191]. Besides the lithography-related geometry variations,
additional variations are added due to spacing, distances to
the shallow trench isolation, and position variances of
contacts. A regularized design and dummy features can
greatly reduce the impact of systematic variability [183].
Among the basic layout approaches tha t are commonly
applied to reduce such variations are: 1) matching the
orientation of the transistors’ layouts to decrease mobility
variations, 2) laying out transistors as close as possible and
using common centroid layout to minimize gradients
throughout the fabrication process, 3) using dummy gates at
the sides of transistor layouts, 4) not laying out contacts on
top of active gates, and 5) not laying out metal lines across
active gates [50]. Within an electronic PUF circuit, wherever
the intrinsic variations are desired, the layout and masking
processes can follow special approaches to oppose or at least
avoid any variation-limiting techniques.
3) VARIATIONS AT SCHEMATIC DESIGN LEVEL
An intrinsic-based variation of a MOSFET’s parameter
among similarly designed MOSFETs within a chip is usually
referred to as intra -die variation or mismatch. These
variations can be due to random local effects (such as the
non-flatness of the polysilicon gate due to granularity) and to
tox gradients over the chip. The general trend of MOSFET
technology evolution is toward smaller horizontal
dimensions, smaller physical t ox , smaller junction depth,
heavier substrate doping, and (although not always) lower
power supply voltage. In Fig. 5, a planar bulk MOSFET has
as a mask length (LM); this length is reduced due to depletion
of the source and drain junctions by a length (L dep ) on each
side, leaving a channel length (L), which is determined as
[222]:
L = LM − 2 Ldep (5)
It is important to emphasize that L, L M, and Ldep exist even
FIGURE 5. Regions of planar n-MOSFET.
Le = L − (∆LS + ∆LD ) (6)
without applying any external voltage at the MOSFET. After
applying a voltage on the drain/source, lateral extents of the
p-n depletion regions of the bulk-source and the bulk-drain
are produced, they are denoted here as (∆L S) and (∆LD ),
respectively. When a voltage is applied at the gate, there will
be a shared gate-source/gate-drain influence on the depletion
charges of the channel at the source/drain sides, respectively.
The remaining distance between the source and drain
depletion is considered the effective channel length (L e),
where the diffusion charges are influenced by the gate
voltage only [211]. Then the Le is calculated as:
The effective length exists only when the channel is formed
by applying external voltages at the MOSFET, while bulk -
source and the bulk-drain depletions exist even without
applying any external voltage to any of the MOSFET’s
terminals. A typical channel region contains only about L1.5 e
dopant atoms; therefore, as a MOSFET fabrication process
is scaled down, mismatch due to dopant fluctuation
increases [223]. Furthermore, since VT is inversely
proportional to the square root of the device area [224];
therefore, the current will have a similar dependency on the
area. For example, in analog designs, to improve the current
matching by a factor of 2, the device area is quadrupled. One
of the approaches to achieve that is doubling both W and L.
In small-geometry devices, various factors contribute to
∆VT0 , such as non-uniform vertical and lateral doping
concentrations, short channel effect (SCE), narrow width
effect (NWE), and drain-induced barrier lowering (DIBL)
[217]. At the schematic design level, a designer can choose
L and W of the MOSFETs. In short-channel MOSFETS, the
SCE varies VT0 by a value denoted as (∆VSCE T0 ), then:
VT =VT0 ± ∆VSCE
T0 (7)
Where (±∆VSCE
T0 ) is considered positive, despite the
channel type. The variation’s sign in (2.18.3) is negative for
n- channel and positive for p-channel. In other words, the
term (± ∆VSCE
T0 ) always carries an opposite sign to VT0 , as the
depletion regions around the junctions (the wells) reduce V T,
where |∆VSCE
T0 | ∝ (Xj /L) [225].
On the other hand, in narrow-channel MOSFETs, when W
is on the same magnitude order as the maximum depletion
region thickness Xdm, another source of variation that
contributes to VT must be considered. In addition to the oxide
thickness above the channel (tox), there is a thick field oxide
(FOX), which covers the region around the channel to resist
the surface leakage currents between adjacent MOSFETs.
The overlapped area between the gate electrode and FOX
develops a low depletion region, which raises V T. This
phenomenon is known as the narrow width effect (NWE)
[226]. The narrow-channel-based variation of VT0 is denoted
as (∆VNWE
T0 ), which always carries a positive sign. Then it
affects VT as [225]:
VT =VT0 ± ∆VNWE
T0 (8)
Where the sign in (2.18.4) is positive for n-channel and
negative for p-channel. In other words, the term ± ∆VNWE T0
always has a similar sign to VT0 , and if the absolute values
are considered, the narrow channel causes extra depletion
charge that ultimately increases |VT |. Combining SCE and
NWE, then VT is determined as:
VT =VT0 ± ∆VSCE NWE
T0 ± ∆VT0 (9)
In case of short-narrow n-channel, then the variations
(−∆VSCE NWE
T0 ) and (+∆VT0 ) tend to cancel each other out, and
a similar argument (but with opposite signs) is valid for a
short-narrow p-channel [225].
At design level, a PUF designer should oppose the general
anti-variation approaches which most analog designers
follow, such as:
- To avoid the intra -chip mismatch among MOSFETs,
which is attributed to statistical randomness, if the
current should match, a high gate-to-source voltage
(VGS) is usually recommended to decrease the influence
of VT [227]. Another approach to decrease the current
mismatch by a factor of 2 is by squaring the MOSFET’s
area [217].
- On the other hand, if the voltage should match, it is
recommended to keep low VGS . That can be done by
increasing the channel width-to-length (W/L) ratio
[227], [189].
- In some cases, a designer can choose between using n -
MOSFET or p-MOSFET. Usually, n-MOSFETs have more
intrinsic variations than p-MOSFETs. The random discrete
dopants, the LER, the polysilicon granularity of the gate
electrode, and surface potential pinning at the poly -Si grain
boundaries play an important role in the statistical variation
within n-MOSFETs while playing a negligible role in p-
MOSFETs [201].
- For resistors, an N-well diffusion resistor is less
susceptible to the intrinsic variations due to its lower
doping and larger volume. Furthermore, it is made of
monocrystalline materials, which reduces the impact of
defects and grain borders [228]. Alternatively, a
MOSFET-base resistor is more susceptible to the
intrinsic variations.
From all the above, to improve the uniqueness of MOSFET-
based PUF design, it is significant to include short-channel
MOSFETs and/or narrow-channel MOSFETs. In either way,
VT would be more distinct among the equally scaled
MOSFETs, which can eventually lead to more distinctive
PUF chips. Since such differences are attributed to random
intrinsic variations, it is quite probable to have unique
properties for each PUF chip. Reversing or at least avoiding
any variation-limiting approach allow for more intrinsic
variations, which can create unique PUF chips. Furthermore,
scaling down a MOSFET increases the sensitivity to
threshold voltage variations [229].
VII. PUF TYPES AND APPLICATIONS
This section lists the most basic types of PUFs and classifies
them according to various categories and focuses on
electronic PUFs.
A. PUF Overview and Classifications
Many PUFs have been proposed in the last two decades,
making it difficult to list them a ll. Some literatures have
listed and classified many of them [230]. Nowadays, most
electronic devices, such as resistors, condensers, and
transistors, are manufactured using sub-micron technologies
that are highly susceptible to process variations. They are not
controlled by the manufacturer and are referred to as random
(or stochastic) variations [37], [177]. They vary the physical
parameters and lead to disparities in 1) current [231]; 2)
frequency of oscillating structures [232]; 3) propagation-
delay of racing signals along the transmission paths [45]; 4)
thickness of coating layers [233]; and 5) initial state of
memory or memory-like circuitries [64], [66]. Variations a re
usually problematic for most circuit applications, but they
are a source of entropy to generate device-specific
authentication bits. This section lists several PUF
implementations at both reconfigurable and application-
specific integrated circuit (ASIC) levels.
Prior to year 2001, several hardware authentication methods
were proposed, but not under the PUF title, and most of them
lacked for comprehensive mathematical representation. In
2001, Pappu proposed his optical-based authentication
approach and presented the concept of the one-way function
(OWF) [37], [38]. Since Gassend et al. coined the ‘PUF’
term in 2002 [232], Pappu’s device was considered an optical
PUF, and many adopted the ‘PUF’ title [234]–[237].
Fig. 6 illustrates a basic classification approach where a
PUF can be classified either according to its security level,
applications, physical contents, or according to its source of
variation [238]. PUFs can also be broadly classified
depending on their physical contents into electronic and non-
electronic PUFs. The focus of this article is on electronic
PUFs, with more coverage for mixed-signal PUFs.
• Electronic or Silicon PUFs
In this type of PUFs, the challenge-response determining
methodology is determined based on the electronic
properties of an object such as delay of a gate, the threshold
voltage of a transistor, etc. Among the well-known PUFs,
the integrated circuit identifier (ICID) [239]–[241], ring
oscillator PUF (RO-PUF) [232], [242]–[277], crossover
RO-PUF [278], arbiter PUF [116], feed-forward arbiter
PUF [279], [45], [118], coating PUF [106], various SRAM
PUFs [280], [281], data flip-flop (DFF) PUF [60], [61],
power distribution PUF (or resistive PUF) [121], LC PUF
[282], double arbiter PUF [283], glitch PUF [284], and
diode-clamped inverter [285] Electronic PUFs are
categorized further according to their implementation
approaches, into:
- Digital PUFs
It is first important to emphasize that all electronic PUFs
receive and generate digital inputs and outputs, but
internally, all challenging processes are analog by nature
due to the inherent physical characteristics of the
electronic devices. That may explain the limitations
which all current PUFs face, such as their susceptibility
to environmental conditions. The terminology ‘digital
PUFs’ can carry various meanings; however, in this
work, it refers to any electronic PUF that generates its
response in a digital form directly without needing an
analog-to-digital converting stage. Recently, the term
FIGURE 6. PUF classification.
‘digital PUFs’ also includes the reconfigurable PUFs,
which usually implemented on FPGA systems [101],
[117], [286]–[294]. Digital PUFs are discussed further
in Section B.
- Mixed-Signal PUFs
This type is based on embedded analog measurement
techniques; then ultimately, it uses an explicit analog-to-
digital conversion stage to end up having a digital
response. Examples of such PUFs are the ICID (or the
threshold voltage PUF) [239]–[241], the inverter gain
PUF [295]–[297], the microelectromechanical systems
(MEMS) PUFs [298]–[302], the current mirror PUFs
[303]–[306], the threshold voltage PUF [307], and the
capacitive PUF [308], [309]. Mixed-signal PUFs are
discussed further in Section C.
• Non-electronic PUFs
When a PUF is not based on variations of electronic
devices, then such a PUF is a non-electronic PUF or non-
silicon PUF. In this type of PUFs, the challenge-response
mechanism is determined based on some non-electronic
properties of an object. The optical PUF family is an
example of non-electronic PUFs. This family includes the
optical PUF proposed by Pappu [37], [38], then by Pappu et
al.[38] then further developed by Rührmair [234], the CD
PUF [310], and the paper PUF [311], [312]. The optical
PUF proposed by Pappu [37], [38] has been made up of
transparent optical medium containing bubbles. Shining a
laser beam through the medium produces a speckle pattern
(the response) behind the medium that depends on the exact
position and direction of the incoming beam (the
challenge).
PUFs are also categorized according to their source of
 variations into intrinsic and non-intrinsic PUFs [44].
• The Intrinsic PUFs
Physical variations within the intrinsic PUFs, are obtained
unintentionally due to the uncontrollable sources of
randomness throughout the production process. For
example, in semiconductor-based electronic devices, the
variation of doping, the thickness of the gate oxide, and
geometrical variations among the fabricated MOSFET
devices can cause variation in the device’s parameters,
such as the threshold voltage (VT) parameter. If measuring
such a parameter is made possible, that means the
readability of a unique identity and such uniqueness is
inherited to each object attached to the MOSFET-based
PUF device. In general, a PUF is considered intrinsic when
it fulfills both of the following conditions:
- Randomness is inherited during the production process
implicitly, without any added effort or cost.
- Response evaluation is performed internally (even if
externally corrected). This means that there are fewer
external stimuli during a response measuring and thus
fewer chances for errors to occur. The other advantage is
security; for example, in case of weak PUFs, it is essential
to have the response evaluation internally, then encrypted
before disclosing it to outside the chip.
The intrinsic PUFs include: the arbiter PUF [116],
exclusive OR (XOR) arbiter PUF [117], [289], [290], feed-
forward arbiter PUF [116], [279], [45], [118], RO-PUF ,
glitch PUF [313], [284], [314], various SRAM PUFs, latch
PUF [88]–[93], flip-flop PUF [60], [61], bistable ring PUF
(BR-PUF) [246], ICID [239]–[241].
• The Non-intrinsic PUFs
The non-intrinsic PUFs are called so because they either
are not entirely embedded in the object, or they are not
produced in the standard manufacturing process of their
embedding object, or both [44]. The non-intrinsic PUFs can
be in va rious forms, such as optical-based PUFs, including
CD PUF [310], paper PUF [311], [312], and phosphor PUF
[315], [316].
Electronic-based PUFs, including magnetic PUF [317],
acoustical PUF [318], coating PUF [106], [319], and power
distribution network PUF [121]. RF-based PUFs, including
RF-DNA [320] and LC PUF [282].
PUFs can also be classified according to their a pplication
type, into stand-alone PUFs, and integrated PUFs [169].
Finally, PUFs are sometimes classified according to their
security levels, into strong and weak PUFs [34]. Weak PUFs
usually protect themselves by an algorithm that controls the
access to the PUF and thus called controlled PUFs [112],
[113].
B. Digital PUFs
Digital PUFs are part of the electronic PUFs. They are
subdivided further into memory-based PUFs (whether at the
register level or the array level) and delay-based PUFs.
1) MEMORY PUFS
Memory-based PUFs are conceptually the simplest kind
of PUFs. A digital secret key K is embedded in a tamper-
proof package along with some logic circuit that computes
Response=RF(K, Challenge), where RF is a random
function. Relying on an embedded key makes such a system,
not a compelling PUF. Most of the known digital PUFs are
memory-based. Memory devices can be utilized as PUFs
[134], [321], [322]. Memory PUFs can be volatile or non-
volatile memory-based PUFs.
Intrinsic variations of non-volatile memory have enabled
them to serve as PUFs [323], [324], such as, domain wall
memory (DWM) PUF [325], phase change RAM (PC-RAM)
PUF [326]–[330], resistive RAM (ReRAM) or (RRAM)
PUF [331]–[349], spin-transfer torque magnetic RAM
(STTM-RAM)or MRAM PUF [350]–[355], memristor PUF
[356]–[374], and flash memory PUF (FPUF) [375]–[385],
and electrically erasable programmable read-only memory
(EEPROM) PUF [386].
Volatile memory PUFs includes: DRAM PUF [97]–[105],
[387]–[389], latch PUF [88]–[93], linear feedback shift
register (LFSR) PUF [390]–[394], and various SRAM PUFs
[280], [281]. Some PUF approaches can combine more than
one form of memory, such as SRAM and DRAM [395].
Memory PUFs can be further classified into two
categories:
• Initial state value memory-based PUFs
They are based on the random initial digital value at the
power-on time of some memory elements such as latches
and flip-flops; therefore, such PUFs are called metastable-
(or bi-stable) memory-based PUFs. Examples of such
PUFs: power-up SRAM PUF [64]–[79], flip-flop PUF
[60], [61], latch PUF [88]–[93], and buskeeper PUF [63].
There are also some weaker PUFs in this category, known
as physically obfuscated keys, which are based on a type
of NVM that is more difficult to attack than the regular
EEPROM.
• Steady-state memory-based PUFs
They are based on reading a steady digital value stored
in an address that is randomly chosen by the challenge
word. The memory is commonly a large read-only
memory (ROM), such as: SHIC PUF [125], [126],
destabilized SRAM PUF [81]–[83], SRAM failure PUF
[84], SRAM transformed PUF [85], [86], and static
memory-based PUFs [88], [396], which are also known as
mono-stable memory-based PUFs.
2) DELAY PUFS
Some silicon PUFs are based on the propagation delay
variations of digital signals across separated paths across
identically designed devices. The racing signals are usually
manipulated by a chain of switches and interconnects to
manipulate delays, which ultimately leads to generating a non-
predicted output response [130]. For example, a ring of an
even number of inverters has one of two possible states when
powered up; based on that, the BR-PUF was proposed [246].
Other delay-dependent response bits are generated based on
the frequency difference between oscillators, and there are
various versions of RO-PUFs. A glitch also causes a delay,
and this is the idea behind the glitch PUF [284].
C. Mixed-Signal PUFs
A PUF in this category is considered as a mixed-signal PUF
if it adopts an analog measurement technique, then an
explicit analog-to-digital converter (ADC) to convert its
response into digital form. Most known mixed-signal PUFs
are based on fabrication variations, such as geometric and
doping, which their influences are obvious, mainly on the
threshold voltage parameter of the MOSFET. The mixed -
signal PUFs can be subdivided into:
• Memory-based Mixed-Signal PUFs
They include: super-high information content (SHIC)
PUF [125], [126] and SRAM transformed PUF [85], [86].
• Non-Memory-based Mixed-Signal PUFs
They include: ICID PUF [239]–[241], inverter gain PUF
(or nanokey PUF) [295]–[297], current-starved inverter
PUF [231], current mirror array (CMA) PUF [304], current
mirror crossbar array (CMCB) PUF [305], organic current
mirror (OCM) PUF [306]. capacitive PUF [308], enhanced
capacitive PUF (EC-PUF) [309], and differential circuit
PUF (DiffC-PUF) [109].
D. Electronic PUF Applications
Since early 2000s, electronic PUFs are used for various
applications. Instead of on-chip key storage, some PUFs
were used as on-the-fly key generators, like the RO-PUF
[232], [242]–[277]. PUFs can also be employed as true and
pseudo-random number generators [338], [397]–[402]. The
generated keys can be used as figure prints and cryptographic
keys. PUFs can also help solve the intellectual property (IP)
protection problem [403]–[405].
In 2007, SiidTech company [406] reported that it has
deployed ICID units in millions of integrated circuit chips
[241] of Hitachi Solutions Technology Ltd. (former Hitachi
ULSI Systems Co., Ltd.) [407]. Later, Intrinsic-ID company
[408], a spin-out of Philips, announced that it has deployed
SRAM-based PUF in more than 170 million devices, to
generate an ID at the power-up of the SRAM, and that ID
can be used as an encryption key [409], [410].
Regarding possessors and microcontrollers, in 2005, Suh
et al. used FPGA to design a PUF-based secure processor
[411], and they used Bose-Chaudhuri-Hocquenghem (BCH)
ECC. In 2011, Böhm et al. [412] implemented a power-up
SRAM-PUF using NXP LPC1768 microcontroller. They
utilized one built-in SRAMs in MCU, and instead of using
ECCs, which are complicated and have lower correction
capabilities, Böhm et al. wrote a repetitive correction code
into the flash memory of an MCU; which Hofer and Boehm
suggested erlier for SRAM-PUFs [413].
In 2016, NXP Semiconductors company added SRAM
PUF unit into its P60D145 microcontroller, a member of the
P60-Step-Up generation of the well-known SmartMX2
microcontroller family [414]. It was meant for
contact/contactless authentication and protection of
credential low power applications, which include electronic
identification cards, travel documents, eGovernment,
banking, and public transport RFID tokens. The SmartMX2
MCU was embedded in MIFARE smart cards [415]. Later,
NXP company integrated SRAM PUF into other MCUs
[416]–[418]. Wireless sensor networks (WSNs) usually use
DRAM or SRAM memory elements, which can be exploited
for increasing the security of WSNs [267], [419], [420].
These PUFs can be used for licensing and certification
applications and to secure smart cards, and also for remote
services/features activation [403]. The emerging use of IoT
devices has urged researchers to develop PUFs and
authentication protocols for IoT [421]. Some IoT PUF
concepts are based on exploiting an already existing unit
within these IoT devices, and some require embedding an
additional physical unit. Among the units proposed to serve
IoT authentication, voltage regulator [422], ring oscillator
[260], [270], transceiver, DRAM [102], [387], LFSR [391],
memristor [374], SRAM [69], [423], sensor [424], MEMS
[300], radio frequency transmitter [425], and hash functions
[426].
VIII. SECURITY PROSPECTS
Data accessing the PUF can be managed via the application
program interface (API) to prevent unauthorized access to
the PUF. The API can also be set to prevent the generation
of a repeated response to a repeated challenge; that is to
harden the task of side-channel modeling attacks, which may
attempt to reproduce the attack in order to test the reliability
of the measured response. [427]. A PUF which employs an
API is called a controlled PUF [113], and communications
to the remote verifier are then considered protected from end
to end [428]. Security attacks are generally classified into
invasive, semi-invasive, and non-invasive attacks.
A. Invasive Attacks
Invasive attacks require removing the chip’s packaging by
etching, drilling, or laser cutting, then using a micro-
probing workstation to probe the chip [429]–[434].
Researchers have invented various protection
mechanisms, for example, adding metal layers forming a
sensor mesh above an actual circuit can provide a tamper-
sensing environment [430], [118], [435]. This sensor mesh
technique has been used in some commercia l smart card
CPUs such as ST16SF48A and in some battery-buffered
SRAM security processors such as DS5002FPM and
DS1954 [429]. Later, Immler et al . proposed their battery-
free, tamper-resistant PUF [436], based on the capacitive
properties of a mesh of fine electrodes. Alternatively, an
active post-process spray coating containing inhomogeneous
particles can be included as introduced in [233], [106] to: 1)
embed a unique signature for smart cards by measuring some
electrical properties at specific spots within the
inhomogeneous coating material, 2) protect the chip from the
invasive attacks, and 3) harden the basic optical non-invasive
attacks. The active coating included particles of variou s
permeabilities, shapes, and sizes. In a later work, metal
sensors were layered beneath the passivation layer to form
an active-coating capacitive PUF [319]. In [437], the metal
sensors were reshaped into pairs of metal comb capacitors to
increase the surface area exposed to the coating. This model
was elucidated further in [438]. A newer active-coating
capacitive PUF stacked more than one layer of metal comb
capacitors [439].
B. Semi-Invasive Attacks
Semi-invasive attacks attempt to inject a temporary error into
the PUF, either by a faulty instruction or by operating the
chip in certain conditions. They would include testing the
targeted chip with various input data, supply voltages,
temperatures, and frequencies. However, such attacks do not
permanently alter the properties of the chip [440]–[444].
C. Non-Invasive Attacks
Non-invasive attacks include optical, brute-force, man-in-
the-middle (MITM), and side-channel attacks.
- Optical Attacks: These attacks aim to view the internal
structure of the chip. Ray-resistant encapsulant shields
can be used to resist such attacks.
- Brute-Force Attacks: An attacker tries multiple
challenges to generate a specific response. This attack is
more relevant to weak PUFs with a single CRP or a few
CRPs. By contrast, it is not an imminent threat to strong
PUFs, where each CRP is only used once or a few times.
Furthermore, controlling the PUF interface to prevent
applying a challenge more than once reduces reliability
of such attacks. Alternatively, when accessibility to a
PUF is uncontrolled, an attacker can collect a large
number of CRPs, and use some for training a
mathematical model and the rest for testing that model.
- MITM Attacks: These eavesdropping attacks are more
relevant to uncontrolled PUFs, if communications to the
verifier side were not encrypted or the attack decipher
the encryption [112], [445]. Generally, if challenges are
never to be reused, it is not essential to encrypt the CRP
during the authentication phase [242].
- Side-Channel Attacks: These include optical emission
power analysis (OEPA) [446], electromagnetic (EM)
attacks [447], and differential power analysis (DPA)
[448], [449]. In these attacks, an attacker analyzes many
power traces of the chip to discern its inward function.
Decoupling capacitors can oppose such attacks [450]–
[454].
Applying a post-processing coating can protect the internal
data communication between the PUF and the
microcontroller (MCU) from invasive attacks, while
encrypting the communication between the smart card and
the verifier side defies MITM attacks.
IX. CONCLUSION
Hardware-based authenticity using a physically unclonable
function (PUF) is a hot field of research, and PUF designers
pursue the finest combination of security, compactness, and
reliability. This article reviewed many of the basic properties
and metrics of PUFs, in general, and CMOS-based electronic
PUFs, in particular. Electronic PUFs can be digital, mixed-
signal, memory-based, or memory-free circuits. In one way
or another, they are all based on the analog nature of basic
electronic devices, such as metal-oxide-semiconductor field-
effect transistor (MOSFET), capacitor, inductor, or resistor.
Thereby, even digital PUFs are affected by temperature and
voltage variations, and such temporal environmental
variations may alter the response; therefore, most PUF chip
designs include an error correction code (ECC) unit.
Most PUFs combine authentication with cryptographic-
key generation, which implies no error tolerance, and thus
ECC units are essential for such systems. ECC units cost
area, power, and data processing time and pose security
threats, such as invasive attacks and side-channel attacks.
Although alternative error correction approaches, such as
repetitive correction code would reduce complexity and
increase the ability to correct errors, such PUF would still
use on-chip memory to store a correcting code, which still
poses a vulnerability to security attacks. Whether a memory
unit is used to generate or correct the response, any memory-
based PUF is classified as a weak PUF. On the other hand,
mixed-signal PUFs are generally safer, but more susceptible
to environmental and aging variations, and therefore rely
more on ECC. However, there is an example of the EC-PUF,
which is an ECC-free mixed-signal PUF, but it allows a
margin of error tolerance and is therefore intended for
authentication only, and not for key generation.
Scaling down the transistor feature size contributes to the
uniqueness of a PUF response. For example, 45 nm CMOS-
based PUFs would have more variations and thus uniqueness
than 65 nm CMOS-based PUFs, and the 28 nm PUFs would
have even more uniqueness. In general, despite the CMOS
technology adopted, the lower the scale of the MOSFET
device, the greater the inherent variation in the parameters of
the device would be. The article also concludes that in order
to build a CMOS-based Pclass with a high uniqueness among
its chips, it is recommended that designers and challenge indexed by (i=150), the challenge is denoted as
manufacturers contradict any variation-limiting approach, (X150 ), and if the tests are done under some certain set of
wherever suitable. At the design level, for example, using environmental conditions (α3 ), then the measured responses
either short-wide or long-narrow MOSFET channels would can be denoted as Y1, 150, 3 , Y2, 150, 3 , Y 3, 150, 3 , Y4, 150, 3 ,
enhance the uniqueness of the PUF class (Pclass ). At the and the number of non-repeated PUF combinations can be
masking level, it is recommended to apply PUF-aware determined as:
optical proximity correction to optimize the mask pattern to (N )(N −1 ) (4 )(4−1)
improve the uniqueness of the PUF chips. At manufacturing Npair = PUF PUF = = 6 pairs, and the inter-
2 2
technology level, some CMOS manufacturing technologies distances are:
and materials are more recommended than others to increase Dinter inter inter inter inter inter
1-2, 150 , D1-3, 150 , D1-4, 150 , D2-3, 150 , D2-4, 150 , D3-4, 150
randomness and thus enhance the uniqueness of PUF devices If the pairs are numbered as (p), then the inter-distance can
within the Pclass .
be denoted as (Dinter p,i
):
X. APPENDICES Dinter inter inter inter inter inter
1, 150, 3 , D2, 150, 3 , D3, 150, 3 , D4, 150, 3 , D5, 150, 3 , D 6, 150, 3 ,
and the average inter-distance (Dinter )
against a challenge
ave,i
A. Average Hamming Distance
(Xi ), within an ambient (α), is:
The Hamming distance (Dinter 1-2,i ) between each possible p=Pair inter
∑p=1 Dp, i
pairing group of the tested PUFs within that (P class ) is first inter
Dave, i =
found as: p
Dinter ( ) ( )
1-2, i ≜ dist [PUF1 Xi ; PUF 2 Xi ]
For example, if the above parameters are applied to find
or Dinter Dinter
ave,i , then:
1-2,i ≜ dist [PUF1,i,α ; PUF 2,i ]
p=Pair inter
or Dinter ( ) ( ) ∑p=1 Dp, i
1-2, i ≜ || PUF1 Xi − PUF 2 Xi || inter
inter Dave,i =
, then D1-2 (Xi ) ≜ dist [Y1,i ; Y2,i ] No. of Pairs
Dinter inter inter inter inter inter
1, 150 + D2, 150 + D3, 150 + D4,150 + D 5, 150 + D6, 150
or Dinter
1-2 (Xi ) ≜ || Y1, i − Y2, i || =
6
Hamming distance is usually measured by the number of
B. Average Inter-Hamming Distance Distribution
different bits between any two digital strings. When referring
to the hamming distance in terms of percentage, the ideal The average distance distribution (µinter
i
) is determined as:
Dinter
ave,i
inter-distance of the chip should be around 50%, in order to µinter
i
= , If substituting the formula of Dinter
ave,i,α , then:
avoid bias in the response. This means that half of the bits Nres
p=Pair inter
∑p=1 Dp,i
are different between the two response strings. The p=Pair inter
Dinter
No. of Pairs
ave, i 1 ∑p=1 Dp, i
Hamming distance can be found for each possible pair µinter
i
= = = .
combination of the tested PUF individuals within the tested Nres Nres Nres No. of Pairs
p=Pair inter
(Pclass ) [49]. If the experiments are done under the same 1 ∑p=1 Dp, i
condition (α), and ∀1 ≤ i1 ≠ i2 ≤ Npuf ; for different PUF = .
Nres (Npuf ). Npuf − 1 )
(
individuals (i 1 , i2 ) within the Pclass , then the minimum value 2
for (Npuf ) is 2, and if the experiments are repeated using only p=Pair
2
two different PUF individuals within the Pclass , then the value = . ∑ Dinter
p, i
Nres . Npuf .(Npuf − 1 )
of (N puf ) increases by one each time a new (Dinter 1-2,i
) is tested pair=1

between two different PUF entities. If the number of the

C. Clonability of a PUF
challenge tests is denoted as ( Ncha ), and the input challenge
Hamming distance between the response of the original PUF
digital string is indexed by (i), then the testes are repeated
instance (PUF1 ) and the response of the cloned PUF instance
(Nmea s ) times and indexed by (i) as ∀1≤ i ≤ Ncha .
Among these (Npuf ) objects, it is required to determine (PUFclone) can be formulated as [49]:
Dinter ( )
1-clone, i ≜dist [PUF 1, α Xi ; PUFc lone, α Xi ]
( )
Hamming distance between each two different PUF inter
individuals, i.e. (Dinter or D1-clone, i ≜dist [PUF 1, i, α ; PUFclone, i, α ]
1-2,i ) against the same challenge. This
means Hamming distance is determined for each pair of two or Dinter ( ) ( )
1-clone, i ≜|| PUF1,α Xi − PUF1,α Xi ||
elements, i.e. (L=2) within that class. The total number of all , then Dinter
1-clone, i ≜|| PUF1, i, α − PUFclone, i, α ||
possible pairs (Npair ) within a class can be calculated as: or Dinter
1-clone, i ≜||Y1, i, α − Yclone, i, α ||.
n! n (n−1 ) (n−2)! n (n−1 ) n ( n−1 ) (Npuf )(Npuf −1 )
Npair = = = = =
( )
L! n−L ! 2! ( n−2 )! 2! 2 2 If Dinter
1-clone, i ≜0, for ∀1≤ i ≤ Ncha , then (PUFclone) is an
For example, if the noisy response Yi,α is measured once for identical clone of (PUF1 ), where (Ncha ) is the maximum
each of four PUF individuals (1, 2, 3, 4), for the same
number of possible challenges (i.e., CRP) sets. Alternatively,
for less restriction, if Pr(Dinter
1-clone, i = 0) for more than one Xi is
high, then there is a high probability that (PUF clone,i ) is an
identical clone of (PUF1 ,i ) for the other untested challenges
and under other environmental conditions.
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