A

SPICE CMOS LEVEL-2, LEVEL-4,

AND BSIM-PLUS MODEL FILES

Computer-aided design tools have become indispensable in the integrated-

circuit design. The SPICE (Simulation Program with Integrated Circuit Em-
phasis) program [1, 2] has been widely accepted for circuit analysis since its
introduction a decade ago. Circuit simulation execution time has been substan-
tially reduced through algorithm improvement and hardware enhancements in
the past few years.

Device modeling plays an important role in VLSI circuit design because

computer-aided circuit analysis results are only as accurate as the models used.
The SPICE2G6.B and SPICE 3F.3 programs have provided six built-in MOS
transistor models [3]-[10]. The LEVEL-1 model, which contains fairly simple
expressions, is most suitable for preliminary analysis. The LEVEL-2 model,
which contains expressions from detailed device physics, is widely used for the
analysis of analog circuits. Its accuracy is quite limited when small-geometry
transistors are used. The LEVEL-3 model represents an early attempt to pursue
the semi-empirical modeling approach, which only approximates device physics
and relies on the proper choice of the empirical parameters to accurately repro-
duce device characteristics. The LEVEL-4 model, which is also called BSIM
(Berkeley Short-Channel IGFET Model), is ideal for the simulation of digital
and analog circuits with effective channel lengths as small as 0.8 J.lm. The
LEVEL-5 model, which supports more than 100 device parameters, requires
special care to use and very elaborated parameter extraction. The LEVEL-6
model is based on the empirical nth power law and specially optimized for quick
estimation of digital circuit behavior. In addition, the BSIM_plus model has
been developed at University of Southern California. It is a greatly enhanced
version over the original LEVEL-4 model.

513
514 ApPENDIX A

The modeling equations for the LEVEL-2 model can be found in the books
by P. Antognetti and G. Massobrio [11] and by D. Divekar [12]. A set of
typical parameter values for the LEVEL-2 model is listed in Table A.I. These
parameter values were extracted from a 2-J,Lm double-polysilicon p-well CMOS
process. The test wafers were fabricated by Orbit Semiconductor Inc. through
The MOSIS Service at USC/Information Sciences Institute.

Table A.1 Typical parameter values for the LEVEL-2 model.

parameters symbols n-channel p-channel unit

vtho VTO 0.888 -0.738 V
T01! TOX 3.9E-8 3.9E-8 m
Xj XJ 2.0E-7 2.0E-7 m
N6Ub NSUB 2.2E+16 5.8E+15 em-Oj
~f PHI 0.6 0.6 V
,\ LAMBDA 0.028 0.058 V-I
J,Lo UO 585 273 em 2 /V - S

J,Lcrit UCRIT 121762 57420 V/em

J,Le1!p UEXP 0.221 0.255 -
'Y GAMMA 0.952 0.518 Vl/2
Vma 1! VMAX 72452 36876 m/s
Ld LD 2.1E-7 2.4E-7 m
Gj CJ 4.06E-4 2.05E-4 F/m 2
Mj MJ 0.46 0.45 -
Gj6W CJSW 4.17E-I0 2.34E-IO F/m
Mj6w MJSW 0.35 0.32 -
GGDO CGDO 2.69E-IO 3.0IE-10 F/m
GGSO CGSO 2.69E-IO 3.0lE-10 F/m
GGBO CGBO 2.00E-IO 2.00E-IO F/m

The modeling equations for the LEVEL-4 model can be found in [4]-[6]. The
format of the parameters is listed below.

TRANSISTORS
name L sens. factor W sens. factor units of basic
parameter
I VPB (VFB) VPBI (LVFB) VPBw (WVFB) V
2 <Ps (PHI) <PSI (LPHI) <Psw (WPHI) V
SPICE CMOS LEVEL-2J LEVEL-4J and BSIM_plus Model Files515

3 Kl (Kl) KlI (LKl) K lw (WKl) vt

4 K2 (K2) K21 (LK2) K2w (WK2)
5 TJo (ETA) TJOI (LETA) TJow (WETA)
6 jJz (MUZ) dl (DL) dw (DW) cm 2/V - s
(jJm, jJm)
7 Uoz (UO) UOZI (LUO) Uozw (WUO) V-l
8 Ulz (Ul) UlZI (LUI) UlZ w (WUl) jJmV- l
9 jJZB (X2MZ) jJZBI (LX2MZ) jJZBw (WX2MZ) cm 2/V 2 - s
10 TJB (X2E) TJBI (LX2E) TJBw (WX2E) V-l
11 TJD (X3E) TJDI (LX3E) TJDw (WX3E) V-l
12 UOB (X2UO) UOB/ (LX2UO) UOBw (WX2UO) V- 2
13 UlB (X2Ul) UlBI (LX2Ul) UlBw (WX2Ul) jJmV- 2
14 jJs (MUS) jJSI (LMS) jJSw (WMS) cm 2/V 2 - s
15 jJSB (X2MS) jJSBI (LX2MS) jJSBw (WX2MS) cm 2/V 2 - s
16 jJSD (X3MS) jJSDI (LX3MS) jJSDw (WX3MS) cm 2/V 2 - s
17 UlD (X3Ul) UlDl (LX3Ul) UlDw (WX3Ul) jJmV- 2
18 Tor (TOX) Temp (TEMP) Vdd (VDD) jJm(OC,v)
19 CGDO CsubGSO CGBO P/m
20 XsubPART DUMI DUM2
21 No NOI Now
22 NB NB/ N Bw
23 ND NDI NDw

INTERCONNECTS

1 R.h (RSH) Cj (CJ) Cjw (CJW) Ijs (IJS) Pj (PJ)

2 Pjw (PJW) M j (MJ) Mjw (MJW) Wdf (WDF) dl (DL)

The names of the process parameters of transistors are listed below:

VFB flat-band voltage
rPs surface inversion potential
K1 body effect coefficient
K2 drain/source depletion charge sharing coefficient
TJo zero-bias drain-induced barrier lowering coefficient
jJz zero-bias mobility
Uoz zero-bias transverse-field mobility degradation coefficient
Ulz zero-bias velocity saturation coefficient
jJZB sensitivity of mobility to the substrate bias at Vd. = 0
TJB sensitivity of drain-induced barrier lowering effect to the substrate bias
TJD sensitivity of drain-induced barrier lowering effect to the drain bias,
at Vd.= Vdd
516 ApPENDIX A

UOB sensitivity of transverse-field mobility degradation effect to the

substrate bias
U1B sensitivity of velocity saturation effect to the substrate bias
J-Ls mobility at zero substrate bias and at Vd, = Vdd
J-LSB sensitivity of mobility to the substrate bias at Vd, = Vdd
J-LSD sensitivity of mobility to the drain bias at Vd, = Vdd
UlD sensitivity of velocity saturation effect to the drain bias, at Vd,= Vdd
Tox gate-oxide thickness
Temp temperature at which the process parameters are measured
Vdd measurement bias range
No zero-bias subthreshold slope coefficient
NB sensitivity of subthreshold slope to the substrate bias
ND sensitivity of subthreshold slope to the drain bias
CaDo gate-drain overlap capacitance per meter channel width
Caso gate-source overlap capacitance per meter channel width
CaBO gate-bulk overlap capacitance per meter channel length
XPART gate-oxide capacitance model flag

Note: XPART= 0, 0.5, and 1 selects the 40/60, 50/50, and 0/100 channel-
charge partitioning methods, respectively.

The names of the process parameters of diffusion layers are listed below:
sheet resistance/square R,h fJ/square
zero-bias bulk junction bottom capacitance/unit area Cj F/m 2
zero-bias bulk junction sidewall capacitance/unit length Cjw F/m
bulk junction saturation current/unit area lj. A/m 2
bulk junction bottom potential Pj V
bulk junction sidewall potential Pjw V
bulk junction bottom grading coefficient M·J
bulk junction sidewall grading coefficient Mjw
default width of the layer Wdf m
average reduction of size due to side etching or mask
compensation m

The names of the process parameters of poly and metal layers are listed as
following:
sheet resistance/square fJ/square
capacitance/unit area F/m 2
edge capacitance/unit length F/m
default width of the layer m
SPICE CMOS LEVEL-2, LEVEL-4, and BSIM_plus Model Files517

average variation of size due to side etching or mask

compensation m

The following is an example of a parameter set from The MOSIS Service. The
lines starting with "*,, are used as comments.
NM1 PM1 DU1 DU2 ML1 ML2
*PROCESS=hp
*RUN=n29z
*WAFER=2
*Gate-oxide thickness= 176.0 angstroms
*Geometries (W-drawn/L-drawn, units are f.lm/ f.lm) of transistors
measured were:
* 1.5/1.0,3.0/1.0,9.0/1.0,3.0/3.0, 3.0/9.0
*Bias range to perform the extraction (VDD) = 5 volts
*DATE=02-11-93
*NMOS PARAMETERS
-7.58998E-01, 2.14897E-02, 1.23152E-01
7.42201E-01, O.OOOOOE+OO, -2.83200E-24
8.90900E-01, -3.11958E-02, -3.54696E-01
7.88072E-02, 5.78136E-02, -1. 73583E-01
-2.99119E-03, 2.33191E-02, -1.70910E-02
5.54302E+02, 4.81357E-001, 4.75992E-001
1.01538E-01, 9.08377E-02, -9. 19324E-02
-9.93277E-03, 8.94698E-02, 8.29828E-03
8.86808E+00, -4.74779E+00, -4.92191E-01
-6.74775E-04, -4.16015E-03, 2.76833E-03
3.57104E-04, -1.45437E-03, 8.70530E-04
-2.91818E-04, -1. 71502E-03, -1. 70371E-03
2.87472E-04, 3.81244E-03, -5.70459E-03
5.96706E+02, 3.38649E+01, -1. 06304E+0 1
6.06875E-01, 8.52691E+00, -1.53784E+01
1.06405E+00, 7.52749E+00, -1.59711E+00
-1.46476E-04, 4.02165E-03, -2.18420E-03
1. 76000E-002, 2.70000E+01, 5.00000E+00
7.08322E-010, 7.08322E-010, 3.88315E-010
1.00000E+000, O.OOOOOE+OOO, O.OOOOOE+OOO
1.00000E+000, O.OOOOOE+OOO, O.OOOOOE+OOO
518 ApPENDIX A

O.OOOOOE+OOO, O.OOOOOE+OOO, O.OOOOOE+OOO

O.OOOOOE+OOO, O.OOOOOE+OOO, O.OOOOOE+OOO

* Gate Oxide Thickness is 176 Angstroms

*PMOS PARAMETERS
-3.13668E-Ol, 7.71734E-02, -8.49659E-02
7.46549E-Ol, O.OOOOOE+OO, O.OOOOOE+OO
4.90935E-Ol, -1.06839E-Ol, 1.39901E-Ol
-8.01381E-03, 4.93369E-03, 2.51322E-02
-1.17312E-02, 2.85411E-02, -1.52749E-03
1.78348E+02, 3.17007E-001, 4.86131E-001
1.57383E-Ol, 9.28071E-02, -9.12893E-02
-5.32992E-03, 4.19297E-02, 1.02423E-02
8.400 17E+00, -2.31231E+00, -3.92977E-Ol
-1. 73344E-03, -7.90961E-05, -3.56574E-04
9.49485E-04, -1.29339E-03, -7.37481E-04
7.58006E-03, -8.69999E-04, -2.05270E-03
-1.55610E-04, 6.62824E-04, 7.69415E-04
1.93009E+02, 3.63502E+Ol, 1.10325E+00
8.58552E+00, -8.36685E-Ol, 6.17576E-Ol
6.00906E-Ol, 2.70248E+OO, -4.46530E-02
4.15907E-04, -3.64701E-03, -4.84883E-04
1. 76000E-002, 2.70000E+Ol, 5.00000E+00
4.66479E-OI0, 4.66479E-OIO, 3.92039E-OI0
1.00000E+OOO, o.OOOOOE+OOO, o.OOOOOE+OOO
1.00000E+000, o.OOOOOE+OOO, O.OOOOOE+OOO
O.OOOOOE+OOO, O.OOOOOE+OOO, O.OOOOOE+OOO
O.OOOOOE+OOO, o.OOOOOE+OOO, O.OOOOOE+OOO
*N+ diffusion
8.148, 1.530100e-04, 3.803900e-l0, 0, 0.8
0.8, 0.678315, 0.333107, 0, 0
*p+ diffusion
6.944, 5.775000e-04, 9.559400e-11, 0, 0.85
0.85, 0.493244, 6.842700e-02, 0, 0
*METAL LAYER - 1
6. 990000e-02, 0, 0, 0, o
0, 0, 0, 0, o
*METAL LAYER - 2
REFERENCES 519

6. 790000e-02, 0, 0, 0, o
0, 0, 0, 0, o
The modeling equations for the experimental BSIM_plus model can be found in
[8]-[10]. A set of typical parameter values is listed in Table A.2. These param-
eter values were extracted from industrial submicron MOS devices fabrication
by TRW Inc. and Samsung Electronics Co.

Table A.2 Typical parameter values for the BSIM_plus model.

Parameters Description n-channel p-channel Unit

~s surface inversion potential 1.631 0.889 V

VFB fiat-band voltage -1.299 -0.330 V
zero-bias body-effect coeff. 0.421 0.563 yO.5
"II
"12 high-bias body-effect coeff. 0.328 0.309 V°.5
Ks depletion charge-sharing coeff. 2.7e-4 3.4e-4 -
KNZ narrow-width threshold voltage coeff. 0.244 0.217 V/lm
KNB narrow-width thresh. volt. substrate coeff. 5.4e-5 -3.ge-4 /lm
Tlz drain-induced barrier lowering coeff. -0.669 -0.037 -
'ilL short-channel barrier-lowering coeff. 0.185 0.042 f.Lm
f.Lo intrinsic surface mobility 350.35 90.0 cm 2Ns
M. channel length reduction 0.1 0.18 /lm
t!.W channel width reduction 0.04 0.02 /lm
Uosz gate-voltage mobility degradation coeff. -0.12 -0.071 y-I
UOSL short-channel adjustment of ugsz 0.313 0.093 y-If.Lm
U BS substrate-volt. mobility degradation coeff. 4.ge-3 l.5e-4 V-I

EcRIT critical electric field for velocity saturation 70 314 V//lm

Ho output conductance modulation prefactor 0.142 1.61 -
HI output conductance modulation exponent 2.238 42.25 V
Tox gate oxide thickness 8 8 nm
10 subthreshold drain-current coefficient 1e-7 0.3e-7 A
N subthreshold drain current slope 1.5 1.55 -

REFERENCES
[1] L. W. Nagel, "SPICE2: A computer program to simulate semiconductor
520 NEURAL INFORMATION PROCESSING AND VLSI

circuits," Electron. Res. Lab. Memo ERL-M520, University of California,

Berkeley, May 1975.

[2] T. Quarles, A. R. Newton, D. O. Pederson, A. Sangiovanni-Vincentelli,

SPICE 3F3 User's Guide, Dept. of EECS, U.C. Berkeley, CA, May 1993.

[3] A. Vladimirescu, S. Liu, "The simulation of MOS integrated circuits using

SPICE2," Electron. Res. Lab. Memo ERL-M80/7, University of California,
Berkeley, Oct. 1980.

[4] B. J. Sheu, "MOS transistor modeling and characterization for circuit sim-
ulation," Electron. Res. Lab. Memo ERL-M85/22, University of California,
Berkeley, Oct. 1985.

[5] B. J. Sheu, D. L. Scharfetter, P. K. Ko, M.-C. Jeng, "BSIM: Berkeley

short-channel IGFET model for MOS transistors," IEEE Jour. of Solid-
State Circuits, vol. SC-22, no. 4, pp. 458-466, Aug. 1987.

[6] B. J. Sheu, W.-J. Hsu, P. K. Ko, "An MOS transistor charge model for
VLSI design," IEEE Trans. on Computer-Aided Design, vol. CAD-7, no.
4, pp. 520-527, Apr. 1988.

[7] T. Sakurai, A. R. Newton, "A simple MOSFET model for circuit analysis,"
IEEE Trans. on Electron Devices, vol. 38, no. 4, pp. 887-894, Apr. 1991.
[8] S. M. Gowda, B. J. Sheu, "BSIM_plus: an advanced SPICE model for
submicron MOS VLSI circuits," IEEE Trans. on Computer-Aided Design,
vol. 13, no. 9, pp. 1166-1170, Sept. 1994.

[9] S. M. Gowda, BSIM_plus: An Advanced MOS Transistor Model for VLSI

Circuits, Tech. Rep. #225, Signal and Image Processing Institute, USC,
Los Angeles, CA, Nov. 1992.

[10] R. C. Chang, B. J. Sheu, "An analog MOS model for circuit simulation and
benchmark test results," IEEE Int'l Symposium on Circuits and Systems,
vol. I, pp. 311-314, London, England, May 1994.

[11] P. Antognetti and G. Massobrio, Semiconductor Device Modeling with

SPICE, McGraw-Hill: New York, 1988.

[12] D. A. Divekar, FET Modeling for Circuit Simulation, Kluwer Academic:

Boston, MA, 1988.
 B
BASIC VLSI BUILDING BLOCKS

Figure B.1{a} and {b} shows the simulated drain current with respect to the
drain-source voltage VDS and the gate-source voltage Vas, respectively. In
Fig. B.1{a}, the transistor is biased in the strong-inversion region with the
different constant gate-source Vas applied which is larger than the threshold
voltage vth all the time. The operational range mainly consists of two regions:
the linear region {or the triode region} and the saturation region. In the linear
region where VDS S Vas - vth, the drain current can be expressed as,

{B.1}

where {3 is the transconductance coefficient. If the drain-source voltage VDS is

small, the higher-order term of VDS can be neglected and {B.1} because,

{B.2}

Thus, the transistor in the linear region can be used as the voltage-controlled
resistor with the equivalent resistance value,

{B.3}

The resistance can be controlled by Vas value.

If the drain-source voltage VDS is larger than Vas - vth, then the transistor
enters the saturation region and the drain current can be expressed as,

{B.4}

521
522 ApPENDIX B

,,
300 300

,,,
IInHrrtglon ." ..tCl'lltgion IUbthnthoid reglan

250
, VGS.2.00V 250

200
VGS_1.75V

~'50
5!
VGS.UOV
100

VGS.U5V
50
VGS.1.00V

U
VOSM
1.6 U s. ,.
VGSM

(a) (b)

Figure B.1 SPICE-3 simulation results of the n-channel MOS transistor with
W/L = 1OJ.£m/2J.£m. (a) IDS versus VDS for different values of VGs, Here,
=
V SB OV. The dashed line shows the transition between the linear region and
the saturation region. (b) IDS versus VGS for VDS =
5.0V. Here, the values
of VSB changes in order to reflect the body-effect.

by neglecting the channel-length modulation effect. Thus, the transistor in

the saturation region operates as a voltage-controlled current source with the
controlling voltage being the gate-source voltage Vas. The transconductance
value 9m is derived from the relation between the drain current IDS and the
gate-source voltage Vas such as,
aIDS ~
9m = aVas = .B(Vas - lith) = v .BIDS. (B.5)

When the channel-length modulation effect is considered, then (1 + AVDS) is

multiplied in the drain current expressions of (B.1) and (B.4), respectively.

Figure B.1(b) shows the relation between the drain current IDS and the gate-
source voltage Vas with the different constant VDS'S applied to the transistor
biased in the saturation region. If Vas is smaller than the threshold voltage, a
very small current can still flow and the transistor remains in the subthreshold
(or weak-inversion) region.

The intrinsic voltage amplification factor at} is defined as the ratio of the
transconductance value 9m to the output conductance value 90' Assume that
90 is proportional to the drain current IDS in both the subthreshold region
and the strong-inversion region. Then, at} is constant in the subthreshold re-
gion and proportional to l/VIDS in the strong-inversion region as shown in
Fig. B.2. The figure clearly shows the advantages of the circuits using tran-
Basic VLSI Building Blocks 523

sistors biased in the subthreshold region. A high voltage gain can be achieved
at a small power consumption. The circuits using transistors biased in the
strong-inversion region take advantage of a high-speed operation due to the
large amount of charge/discharge currents to the capacitive node and the high
noise-immunity capability due to the large signal range.

gm ocVo

10g(VAF)

'---------i-----... log 10
Subthreshold Strong -inversion
regin region

Figure B.2 Plots of voltage amplification factor all = gm/go for the sub-
threshold region and the strong-inversion region.

(A) Differential Pair

Before addressing the operation ofthe transconductance amplifier, the differen-

tial pair shown in Fig. B.3 can be described first. The differential pair consists
of two n-channel input transistors Ml and M2 and the bias-current transistor
MB. Here, the two input transistors are assumed to be of the same size. In the
strong-inversion region, the drain current expressions are

(B.6)

and
(B.7)
If the transistors are biased in the weak-inversion region, the drain expressions
are
(B.8)
and
(B.9)
524 ApPENDIX B

Figure B.3 Circuit schematics of the differential pair.

Here the voltage are normalized by the factor kT/ q.

After some manipulations, expressions of the differential output currents in

both bias regions can be obtained as

{B.lO}

for the strong-inversion operation. Here V; = V;1 - V;2 and {B.lO} is valid for
a differential input voltage range of

{B.ll}

In the weak-inversion region, the differential output current can be expressed

as,

{B.12}

Figure B.4 shows the calculated differential output currents for both bias re-
gions.
Basic VLSI Building Blocks 525

'00 '00

80 80

60 60

~ "" ! ""
ia 2<) ~
a 20

i 0
,OuA
i
..a
0
a
i .2<)
1. 20

i..., i ·40

-60

·80 ·80

.'~. ., -0.5 0
dl",.na.lnpul voKlQ. M
0.5 '.5 "~50 ·100 -so 0 so '00 ,50
dllftlWltIIJ Input vd_ge (mV)

(a) (b)

Figure B.4 Calculated results of the transconductance amplifier of the

differential pair. (a) For transistors in the strong-inversion region. Here
=
f3 50/lA/V 2 and the bias current IE changes to 10, 20,40, and 80 /lA. (b)
For transistors in the subthreshold region. Here n = 1.3 and the bias current
IE changes to 10, 20, 40 and 80 nA.

The effective transconductance is defined as the differential output current

change with respect to the differential input voltage around the zero input,

(B.13)

Thus, the value of Gm in the strong-inversion region can be determined as,

•i -- V PlB
Gm V[ -- Vf3 [·ij2
1 -- Vf3 [·ij2
2 -- 9ml
.i -- 9m
.i 2' (B.14)

The value of G m in the weak-inversion region can be determined as,

[ [ wi [wi
Gwi B 1 2 wi wi
m = 2nkTjq = nkTjq = nkTjq = 9ml = 9 m2' (B.15)

(B) Transconductance Amplifier

A transconductance amplifier receives the input voltage and produces the out-
put current which is linearly proportional to the input voltage. The differential
pair described earlier is a core portion of a transconductance amplifier. Fig-
ure B.5(a) shows the circuit schematic of the basic transconductance amplifier
which has the differential input voltage and the single-ended output current.
526 ApPENDIX B

In addition to the differential pair, the current mirror consisting of p-channel

transistors M3 and M4 are used to realize the difference between the output cur-
rents. The transconductance value can be determined from (B.14) and (B.15)
for corresponding bias regions. Please note that their values is electrically
controllable, by changing the bias currents lB. Figure B.5(b) shows the cir-
cuit schematic of the transconductance amplifier which has a wide operational
range.

In order to increase the output resistance value of the transconductance ampli-

fier so that the output current can be nearly independent of the output voltage,
the cascode circuit technique can be used. In addition, the linear operation
range can be expanded by using a degenerate differential pair.

(C) Analog Multiplier

The output currents of the differential pair shown in Fig. B.3 can be expressed
as,
r-------,. 2
I 1_-(3- (Yin
-+-1 (B.16)
2 2 2
and

(B.17)

by solving the common source voltage Vx in the expressions of (B.6) and (B.7)
with the use of
(B.I8)
For a small differential input voltage Yin, (B.I0) can be approximated as,
(B.19)

In order to implement a linear multiplication between the input voltage and the
stored weight voltage, the Gilbert multiplier circuit can be used. Figure B.6
shows the schematic diagram of the Gilbert multiplier core. The output current
is obtained from the difference of two currents, I+ and I- , as

(B.20)
Basic VLSI Building Blocks 527

Voo

(a)

Voo

(b)

Figure 8.5 Circuit schematics of the transconductance amplifiers. (a) Basic

TC amplifier. (b) Wide-range TC amplifier.

With the assistance of the expression of (B.19), (B.20) can be reformulated as,

Vf3ult(V3 - V4 ) - Vf3u 12 (V3 - V4 )

$u(.Ji; - y'I;')(V3 - V4 ), (B.21)
528 ApPENDIX B

where Pu = = = =
P3 P4 P5 P6. If the expressions in (B.16) and (B.17) are
used, (B.21) can be simplified to

(B.22)

where P, = Pi = P2.

11

Figure B.6 Circuit schematic of the Gilbert multiplier core.

 c
CURRENT-MODE CIRCUITS FOR
PIECEWISE-LINEAR FUNCTIONS

A systematic circuit-design technique was described by A. Rodriguez-Vazquez

and M. Delgado-Restituto [1] for synthesizing piecewise-linear (PWL) func-
tions. This powerful current-mode circuits technique is summarized below.

The best match properties of MOS transistors are obtained in the strong-
inversion region. In the triode region,

Va - Vtho
Va> Vtho + aVs, and VDS < VDS,sat = a - Vs, (C.1)

the simple drain-current expression is

IDS = (3 [(Va - Vtho - aVs)VDS - '2a VDS

2
]' (C.2)

Here the factor "a" depends slightly on the source voltage Vs and ranges typ-
ically from 1.2 to 1.5. In the saturation region, VDS > VDS,Iat and Va > VthO
+ aVs, the simple drain-current expression is
(C.3)

If the Taylor-series expansion is applied to the drain-current expression in the

saturation region around a bias point (IDs = IQ, Va = VaQ, and Vs = 0),
then
LHDS = 9mAVa + b~VJ' (C.4)
where 9m = 2IQ/(VaQ - Vtho - aVs)= (2kWIQ/aL)t. The magnitude of
the transistor current gain with short-circuit load drops to 1 at the transition

529
530 ApPENDIX C

frequency IT [1, 2],

9m k(VaQ - lithO)
(C.5)
IT ex: 211"0.6W L ex: 211"aO.6£2 .
For a typical1-Jlm CMOS technology with VaQ - lIthO= 2.5 V, the transition
frequency is around 10 GHz.

(A) Integrators

Integrators are major components for the state-variable synthesis approach.

The schematic diagrams of a Miller integrator and an open-loop integrator are
shown in Fig. C.1 (a) and (b), respectively. The integration capacitor is driven
by voltage-controlled currents. The open-loop integrator is also called the GmC
or OTA-C integrator [3].

(a) (b)

+
VJ
l ~
virtual
ground
~
-----r--l--
~
JJ
~
9mJ
- = '"'£'" =
(c)

Figure C.I Schematic diagrams. (a) Miller integrator. (b) Open-loop inte-
grator. (c) Realization of box N.

Two different schemes, as shown in Fig. C.1(c), can be used to realize the box
N of Fig. C.l(a). If an active resistor is needed, the MOSFET-C analog circuit
design method [4, 5] is appropriate,
L
Rj = kW(Va _ litho _ aVs)' (C.6)
The circuit schematics shown in Fig. C.2(a) and (b) are to implement lossless
integrators with a time constant T = C/9m. The Miller integrator is quite
Current-Mode Circuits for Piecewise-Linear Functions 531

insensitive to the parasitic capacitance because the effect of CT is attenuated

by the Op-Amp dc gain Ao, while the effect of CB is minimized due to the
low-impedance connection.

p'
-+-
-+-
c
Vo VI Vo
9m VI -

(a) (b)

I
Ro +
~

~I
Vo
Gm(s}VI

-
(c) (d)

Figure C.2 Integrator equivalent circuits and parasitic capacitances. (a)

Miller integrator. (b) Open-loop integrator. (c) Parasitic capacitances. (d)
vees macromodel.
The open-loop integrator is preferable for high-frequency applications if pre-
distortion is performed to compensate for time constant errors [1]. On the
other hand, the Miller integrator is desirable for low- and medium-frequency
ranges, without the need of pre-distortion. If an improved Op-Amp without
internal compensation is used, the Miller integrator is also suitable for high-
frequency range [6].

The PWL functions can be synthesized through the decomposition into a sum-
mation of simpler functions. The extension operator concept [7] can be utilized
to express an undimensional function as
Np -1

f(x) = Ax + B + L: Mjup(x - Ej) + L: Mjun(x - Ej). (C.7)

j=1 j=-N n

Here the functions up ( .) and Un (.) are defined as

up(x)
I = {Xl0 if x' > 0
(C.8)
otherwise.
532 ApPENDIX C

and
Un (x') = { ox, ifx'>O
otherwise. (C.9)

with the shapes shown in Fig. C.3 (a) and (b).

(M)

(a) (b)

x
x

(e) (d)

Figure C.3 Elementary functions for PWL function synthesis, (a) Concave
function. (b) Convex function. (c) Radial base function. (d) Absolute-value
function.

A different synthesis approach for PWL functions uses the radial base functions
[8],
N
f(x) = Ef(Ej)¢(x,Ej ) (C.lO)
j=l

where the multi-dimensional base functions ¢(x, Ej) have the generic shapes
shown in Fig. C.3(c). For multi-dimensional PWL functions, the Kang and
Chua's method [9] can be applied,
N
fi(X)=ATx+B+ECjIDJx-Ejl, l$i$N. (C.ll)
j=l

The characteristic of an absolute-value operator is plotted in Fig. C.3(d).

(B) Differential Amplifier

Current-Mode Circuits for Piecewise-Linear Functions 533

The transfer characteristic of a source-coupled MOS differential pair can be

expressed as

1 1 - { gm lti - T.., V;3 + 0(') for Ilti I ~ F (C.12)

01 - 02 - IQ . sgn(lti) otherwise.

gm =
kW )1/2 IT.., = 8I~.5
(-;'TIQ 1 (kW)1.5
-;'T
(2a L )1/2
, F = kW IQ (C.13)

Notice that Taylor expansion around lti = 0 was assumed in obtaining (C.12).
The l't-order approximation of (C.12) is plotted in Fig C.4 for T.., = 0(') = o.

Figure C.4 First-order approximation to differential transconductance char-

acteristic.

The differential pair shows odd nonlinearity as in contrast to the strong even
nonlinearity 6f a single-transistor voltage-controlled current source (VCCS). If
the deviation from ideal linearity is required to be within a pre-determined
value,
for IAltil ~ 6, (C.14)

then
6 _ {2fF for unilateral amplifier I
(C.15)
- 2,fiF for differential amplifier.
Here Alo and A lti denote increments around the quiescent point.

Hence, the linearity range of a differential pair is much larger than that of a
single-transistor VCCS. The quasi-linear interval amplitude 6 and the transcon-
ductance value gm can be independently controlled by the device geometry W /L
and the quiescent current IQ.
534 ApPENDIX C

(C) Current Mirror

The current-mirror structure, shown in Fig. C.5(a), has an inherent rectifica-

tion property and can realize the unilateral current rectification. If inverting
bilateral replication is needed, the current-shifting biasing scheme shown in
Fig. C.5(b) and (c) can be utilized. Two inverting mirrors can be cascaded to
achieve the non-inverting current replication as shown in Fig. C.5(d).

(a) (b)

(c) (d)

Figure C.5 Current mirrors. (a) Scaled replication. (b) Bilateral signal
weighting by bias shifting. (c) Bilateral signal weighting by complementary
transistors. (d) Non-inverting bilateral replication.

Characteristics of current mirrors are usually degraded by random and sys-

tematic error sources. The systematic error due to finite Early voltage, VA, of
an MOS transistor can cause the current offset error. In addition, the finite
input resistance will cause ac current errors. The circuit components in the ac
current mirror macromodel shown in Fig. C.6 can be determined by

(C.16)

and
(C.17)
Current-Mode Circuits for Piecewise-Linear Functions 535

(a) (b)

Figure e.6 AC macromodels. (a) Differential amplifier. (b) Current mirror.

For a unity-gain mirror, the current gain error caused by random transistor
mismatch can be expressed as [1]

(C.18)

(D) Improved Differential Pairs and Current Mirrors

Circuit techniques to increase linearity of differential pairs and to enhance the

input and output resistances of current mirrors are available. There are three
major types of circuit structures to increase the linearity range over the achiev-
able value in a simple differential pair [1]:

1. Ohmic transconductors [10, 11],

2. degenerated differential pairs [12, 13], and

3. square-law transconductors [14]-[17].

In the first approach, MOS transistors are biased in the triode region so that

(C.19)

It is critical to maintain the drain terminals with equipotential, independent of

the differential input voltage. The second approach uses feedback to maintain
536 ApPENDIX C

VGS of the transistor practically constant for a large input range,

I I gm TT
01 - 02 = 1 _ g:nR Vi (C.20)

where g:n is the transistor transconductance value. The third approach relies
on the algebraic combination of square-law functions, in a simple form as

(a + b)2 - (a - b)2 = 4ab. (C.2l)

Four different circuit configurations of the third approach are shown in Fig. C.7.

Circuit schematic diagrams of the improved current mirrors are shown in

Fig. C.8. Feedback can be used to keep input and output terminals at equipo-
tential and to enhance the input and output resistances by the amount of
feedback, as shown in Fig. C.8(a). The cascode configurations are useful, too.
The drain voltage of transistor M2 in Fig. C.8(b) is kept constant by the source
follower operation of transistor M4 with external bias VCAS. The effectiveness
of casco de in the current mirror shown in Fig. C.8(c) is enhanced by feedback.

(E) PWL GmC building Blocks

Radial basis functions can be realized by the circuit shown in Fig. C.9(a)
[1, 18, 19]. Assume the two differential pairs are of the identical size, and the
~ value equals to 2F with the F defined in (C.13), the corresponding transfer
characteristic is shown in Fig. C.9(b). Main design considerations are mismatch
and the large common-mode input voltages.

The PWL functions can also be generated by using a front-end quasi-linear

transconductance amplifier [1, 20]. Figure C.lO shows a schematic diagram
to realize the PWL extension operator functions using a current switch and
a class-AB configuration. Any positive input current will increase the input
voltage and turn the transistor Mp on and the transistor Mn off. Similarly, any
negative input current will decrease the input voltage and turn the transistor
Mn on and the transistor Mp off. A detailed schematic diagram to realize full-
wave current rectification and linear base function is shown in Fig. C.ll. The
output current IFw R is the shifted full-wave rectification of the input current 1;.
The output current hBF is related to a base function for positive interpolation
data. Slopes of the base function are controlled by the current-mirror gains.
The position and height of the breakpoint are determined by the dc biasing
currents IDFT and IREF, respectively.
REFERENCES 537

(a) (b)

Vc
:r

(e) (d)

I-
V.-(1/2)VId

IQ IQ

(e)

Figure C.7 Square-law MOS transconductance. (a) Cross coupling[14]. (b)

Adaptve biasing[15]. (c) Class-AB[16]. (d) Voltage shifting.[l7] (e) The degen-
erated differential pair in 2nd approach. Notice that S represents W fL.

REFERENCES
[1] A. Rodriguez-Vazquez, M. Delgado-Restituto, CMOS design of chaotic
oscillators using state variables: a monolithic Chua's circuit," IEEE Trans.
on Circuits and Systems, Part II, vol. 40, no. 10, pp. 596-613, Oct. 1993.
538 NEURAL INFORMATION PROCESSING AND VLSI

- - -
(a) (b) (c)

Figure C.S Improved current mirrors. (a) Active. (b) Cascode. (c)
Regualted cascoded.

lo,~ ~102

E-~2-1
I- 21Q
10 ,-1 02

E-A E,IQ) E+A

Vss

(a) (b)

Figure C.9 Radial basis function implementation. (a) Circuit schematic. (b)
First-order transfer function.

[2] J. M. Steininger, "Understanding wide-band MOS transistors," IEEE Cir-

cuits and Devices Magazine, vol. 6, pp. 26-31, May 1990.

[3] R. L. Geiger, E. Sanchez-Sinencio, "Active filter design using operational

transconductance amplifiers: a tutorial," IEEE Circuits and Devices Mag-
azine, vol. 1, pp. 20-32, Mar. 1985.

[4] Y. Tsividis, M. Banu, J. Khoury, "Continuous-time MOSFET-C filters in

VLSI," IEEE Trans_ on Circuits and Systems, vol. 33, pp. 125-140, Feb.
1986.
[5] M. Ismail, S. Smith, R. Beale, "Four transistor continuous-time MOS
transconductor," Electronics letters, vol. 23, no. 20, pp. 1099-1100, Sept.
1987.
REFERENCES 539

Figure C.IO PWL extension operator circuit.

IFWR

Figure C.1I Full-wave current rectification and linear base function imple-
mentation with positive interpolation data via a current switch rectifier.

[6] K. D. Peterson, A. Nedungadi, R. L. Geiger, "Amplifier design consider-

ation for high frequency monolithic filters," Proc. of European Conf. on
Circuit Theory Design, pp. 321-326, Sept. 1987.

[7] L. O. Chua, S. M. Kang, "Section-wise piecewise-linear functions: canon-

ical representations, properties and applications," Proc. of IEEE, vol. 65,
pp. 915-929, June 1977.
[8] G. A. Watson, Approximation Theory and Numerical Methods Wiley: Bing-
hamton, NY, 1980.
540 NEURAL INFORMATION PROCESSING AND VLSI

[9] S. M. Kang, L. O. Chua, "A global representation of multi-dimensional

piecewise-linear functions with linear partition," IEEE Trans. on Circuits
and Systems, vol. 25, pp. 938-940, Nov. 1978.
[10] J. Pennock, P. Frith, R. G. Barker, "CMOS triode transconductor
continuous-time filters," IEEE Custom Integrated Circuits Conference,
pp. 378-381, Rochester, NY, May 1986.
[11] B. Nauta, E. Klumperink, W. Kruiskamp, "A CMOS triode transconduc-
tor," IEEE Int'l Symposium on Circuits and Systems, pp. 2232-2235, May
1991.
[12] Y. P. Tsividis, Z. Czarnul, S. C. Fang, "MOS transconductors and inte-
grators with high linearity," Electronics Letters, vol. 22, pp. 245-246, Feb.
1986.
[13] F. Krummenacher, "Design considerations for high-frequency CMOS
transcondcutance amplifier capacitor (TAC) filters," IEEE Int'l Sympo-
sium on Circuits and Systems, pp. 100-105, 1989.
[14] H. Khorramabadi, P. R. Gray, "High frequency CMOS continuous-time
filters," IEEE Jour. of Solid-State Circuits, vol. 19, pp. 939-948, Dec. 1984.
[15] A. Nedungadi, T. R. Viswanathan, "Design of linear CMOS transconduc-
tance elements," IEEE Trans. on Circuits and Systems, vol. 31, pp. 891-
894, Oct. 1984.
[16] E. Seevink, R. F. Wassenaar, "A versatile CMOS linear
transconductor/square-Iaw circuit," IEEE Jour. of Solid-State Circuits,
vol. 22, pp. 366-377, June 1987.
[17] P. Wu, R. Schaumann, "Tunable operational transconductance amplifier
with extremely high linearity over very large input range," Electronics
Letters, vol. 27, pp. 1454-1455, July 1991.
[18] J. W. Fattaruso, R. g. Meyer, "MOS analog function synthesis," IEEE
Jour. of Solid-State Circuits, vol. 22, pp. 1056-1063, Dec. 1987.
[19] C. Turchetti, M. Conti, "A new class of neural network based on approx-
imate identities for approximation and learning," IEEE Int'l Symposium
on Circuits and Systems, pp. 359-362, 1992.
[20] E. Sanchez-Sinencio, J. Ramirez-Angulo, B. Linares-Barranco, A. Rod-
riguez-Vazquez, "Operational transconductance amplifier-based nonlinear
function synthesis," IEEE Jour. of Solid-State Circuits, vol. 24, pp. 1576-
1586, Dec. 1989.
 D
SELECTED SOFTWARE LISTING

D.l CELLULAR NEURAL NETWORK

There are two program listings in this appendix for cellular neural network
simulation. The first one is a C program and the second one is a set of MAT LAB
functions.

The C program can be compiled by any standard C compiler. In Unix system,

if the file is named as cnn.c, the command to use after the system prompt is

prompt> cc cnn.c -0 enn <enter>.

Each pixel in the input image is stored in 8 bit (0-255) unsigned gray-level
format and arranged row by row. The output will be stored as text, which can
later be read in by MATLAB for display. Each pixel will use one line and still
be saved row by row (column-first).

Put the MATLAB functions in the same working directory and invoke them by
'cnn' after MATLAB prompt. Here is the list of provided functions:

cnn.m, tran_a.m, lump..b.m, mat2vec.m, cnndifi'.m, vec2mat.m.

Input images are stored externally using MATLAB built~in .mat format. The
display routine which works under version 4.0 is also included.

541
542 ApPENDIX D

D.2 C LANGUAGE SOURCE LISTING

,.............................................................................
C Program Source listing of the Cellular leural letvork(CII) simulation.

Program prepared by Tony H. Wu and Sa H. Bang under Prof. Sheu's guidance.

Dept. of Electrical Engineering and Dept. of Biomedical Engineering
University of Southern California
Last Revised: Jul. 25 1994
(This program is used for edge detection.)

.............................................................................
#include <stdio.h>
,
#include <stdlib.h>
#include <math.h>

,.............................................................................
#include <malloc.h>

.............................................................................,
Define the processed image size

#define Irov 64

,.............................................................................
#define Icol 64

.............................................................................,
Functions declarations

void ••Oet_Array() ,Free_Array() ,output_result() ,

void init_CII(),ReadInData();
double sigmoid(),ExtA(),ExtB(),derfn();

,.............................................................................
void CII_Dperation(),Runge_Kutta4();

.............................................................................,
Variables declarations

double Vu[lrov+2] [lcol+2] ,Vx[lrov+2][lcol+2];

double Vxl[lrov+2] [lcol+2] ,Vy[lrov+2][lcol+2];
double Rx=1,Cx=1,gtime = O,gain=-2;
,. Variable that you can modify.'
double Ibiass=-1.5; ,. Bias information .,
double tperiod=20.0; ,. time used (in unit time) .,

,.............................................................................
double tsteps=80.0; ,. integration steps im tperiod .,

.............................................................................,
CII main program

mainO
{
CII_Dperation«(double (.»(ExtA»,«double (.»(ExtB»,
«double (.»(sigmoid»,20.0,20.0);
}
/ ............................................................................ .
Description of feedback matrix A and control matrix B.
For different templates, modify A, B (here) and
Ibias information (in the variables declarations .
............................................................................. ,
Selected Software Listing 543

double ExtA (i , j)
int i,jj
{
double outAj
outA = 2.0.Vy[i][j] j
return outAj
}
double ExtB(i,j)
int i,jj
{
int k,lj
double tmp,outBj
static double RB[3] [3]={{-0.25,-0.25,-0.25},
{-0.25,2.0,-0.25},{-0.25,-0.25,-0.25}}j
outB = OJ
for (k=Ojk<=2jk++)
for (1=Ojl<=2jl++)
outB += RB[k] [1] • Vu[i+(k-l)][j+(l-l)]j
return outBj
}
/ ............................................................................ .
Description of desired sigmoid function used .
............................................................................. /
double sigmoid(x)
double Xj
{
return«1.0-exp(gain.x»/(1.0+exp(gain.x»)j
}
/ ............................................................................ .
Initialize the enlarged initial states, inputs,
and the initial outputs .
............................................................................. /
void init_CII(tran_output)
double (.tran_output)()j
{
int i,jj
double Vin[lrow][lcol],double Vini[lrow][lcol]j
ReadInData("edge.inp",Vin,lrow,lcol,O)j /. read in input image ./
ReadInData("edge.ini",Vini,lrow,lcol,O)j /. read in initial state image ./
/. all boundary will be set to 0 ./
for (i=Oji<=lrow+lji++)
for (j=Ojj<=lcol+ljj++)
Vu[i][j] = Vx[i][j] = Vy[i][j] = O.Oj
for (i=lji<=lrowji++)
for (j=ljj<=lcoljj++)
{
Vu[i] [j]=Vin[i-l] [j-l] j
Vx[i] [j]=Vini[i-l] [j-l] j
Vy[i] [j]=(.tran_output) (Vx[i] [j]) j
}
}
/ ............................................................................ .
544 ApPENDIX D

Read in the data from external files.

Data are stored in column-first method.
Each pixel occupy one byte and as unsigned char .
............................................................................. /
void ReadInData(fname,InData)
char .fname j
double InData[lrov][lcol]j
{
int i,jj
unsigned char IIT1[lrov][lcol]j
FILE .fptrj
if «fptr=fopen(fname,lrb"»==JULL)
/. test vhether the input file is valid ./
{
printf("Error: Fail to open Xs\n",fname)j
exit(S)j
}
for (i=Oji<lrovji++)
if (fread(IJT1[i],sizeof(unsigned char) ,Icol,fptr) !=Icol)
{
printf("Error: Fail to read file Xs at rov ~d\n" ,fname, i) j
exit(S) j
}
fclose(fptr)j
/. normalized the data to range from -1 to 1./
for (i=Oji<lrovji++)
for (j=Ojj<lcoljj++)
InData[i] [j]-(IJT1[i] [j]-128.0)/128.0j
}
/ ............................................................................ .
Main CII operation code
............................................................................. /
void CII_Operation(tmpA,tmpB,tout,tf,steps)
double tf,stepsj
double (.tmpA)(),(.tmpB)(),(.tout)()j
{
double dt, time j
dt == tf/stepsj
init_CII«double .)(tout»j
/. here is real cnn transition process, Runge-Kutta method vas used .• /
for (time==Ojtime<tfjtime+=dt)
Runge_Kutta4(time,dt,«double .)(tout»,«double .)(tmpA»,
«double .)(tmpB»)j
output_result()j
}
/ .............................................................................
Write the result into an external file.
Data are vritten in "double" format 'for further
processing, such as MATLAB .
............................................................................. /
void output_result()
{
Selected Software Listing 545

FILE .fptrj
int i,jj
fptr = fopen("edge.out","ll")j
for (i=lji<=lrOllji++)
{
for (j z 1jj<-lcoljj++)
fprintf(fptr,"%lf ", Vy[i] [j]) j
fprintf(fptr ,"\n") j
}
fclose(fptr)j
}
/ ............................................................................ .
Calculate the right-side term in CII equation
............................................................................. /
double derfn(i,j,x,tempA,tempB)
int i,jj
double x,(.tempA)(),(.tempB)()j
{
double sumAj
sum! = «.tempA)(i,j) - x/ax + (.tempB)(i,j) + Ibias)/Cxj
return sumAj
}
/ ............................................................................ .
Use Runge-Kutta 4-th order integration method
to solve the differential CII equation .
............................................................................. /
void Runge_Kutta4(time,dt,output_transfer,TA,TB)
double time,dt,(.output_transfer)(),(.TA)(),(.TB)()j
{
double K1,K2,I3,K4j
int gi,gj,itj
char fname[20]j
FILE .fptrj
gtime = timej
printf("time = %If\n", time) j
for (gi=ljgi<=lrOlljgi++)
for (gj=ljgj<=lcoljgj++)
{
K1=dt.derfn(gi,gj,Vx[gi] [gj],«double .)(TA»,«double .)(TB»)j
K2=dt.derfn(gi,gj,Vx[gi] [gj]+K1/2.0,«double .)(TA»,«double .)(TB»)j
K3=dt.derfn(gi,gj,Vx[gi] [gj]+K2/2.0,«double .)(TA»,«double .)(TB»)j
14=dt.derfn(gi,gj,Vx[gi] [gj]+K3,«double .)(TA»,«double .)(TB»)j
Vxl[gi] [gj] = ·Vx[gi] [gj]+(K1+2.0.K2+2.0.K3+K4)/6.0j
}

for (gi=ljgi<=lrOlljgi++)
for (gj=ljgj<=lcoljgj++)
{
Vx[gi] [gj]=Vxl[gi] [gj] j
Vy[gi] [gj]=(.output_transfer) (Vx[gi] [gj]) j
}
it = (int)(time)j
546 ApPENDIX D

sprintf(fnllllle,"exttd.out",it)j
fptr = fopen(fnllllle,"lf")j
for (gi-1jgi<=lrOlfjgi++)
{
for (gj-1jgj<=lcoljgj++)
fprintf(fptr ,"td ", (int) (127.Vy[gi] [gj]+128» j
fprintf(fptr,"\n")j
}
fclose(fptr)j
}

D.3 MATLAB SOURCE LISTING

Please put the following MATLAB functions in separate files and place them
in one working directory.

t-----------------------------------------------------------------------------
t cnn.m
t-----------------------------------------------------------------------------
I = 16j
ts = OJ
tf .. 50j
global AT uOj

colormap(gray(256»j
clfj
axis('image')j

load objectj
object1 .. -1 .ones(I+2)j
object1(2:1+1,2:1+1).object(1:I,1:1)/128-ones(l)j
disp('load image and transform complete! ')j
subplot (2 ,1,0 j
image(frame(object»j
axis('image')j
axis(loff') j

t transient matrix
RA1 • [0 0 OjO 2 OjO 0 0] j
RB1=[-0.25 -0.25 -0.25j-0.25 2.0 -0.25j-0.25 -0.25 -0.25]j
IB1=-1.5j
AT" tran_a(RA1,I)j
disp('AT complete!')j
uO = lump_b(RB1,IB1,object1,I)j

t initial condition
x1 .. matv2vec(reduce(object1»j
Selected Software Listing 547

l start cnn transition

uxl-zeros(I*I,l)j
[tl,uxl]-ode46('cnndiff',ts,tf,xl)j
[rovl,coll]=size(uxl)j
BV .. vec2aat(uxl(rovl,:),I)j
subplot(2,l,2)j
image(frame(map(BV»)j
axis (l image' ) j
axis(loff') j

l-----------------------------------------------------------------------------
l tran_a.1I
l-----------------------------------------------------------------------------
function AT-tran_a(RA,I)
l translate the input A matrix into large transition matrix

r-zeros (I ,1) j
c.zeros (I ,1) j
r(1)"RA(2,2) j
r(2)-RA(2 ,1) j
c(O=RA(2 ,2) j
c(2)=RA(2,3)j
A2=sparse(toeplitz(r,c»j
r(1)"RA(3,2) j
r(2)=RA(3,3)j
C(O=RA(3,2) j
c(2)-RA(3,3)j
A3=sparse(toeplitz(r,c»j
r(1)=RA(1,2) j
r(2)=RA(1,1) j
c(1)=RA(l,2) j
c(2)-RA(1,3) j
Al=sparse(toeplitz(r,c»j

for i=1:1
if i •• 1
AT" [A2 A3 sparse(I,(1-2)*I)]j
alseif i==1
AT = [ATj sparBe(I,(1-2)*I) A1 A2]j
elBe
AT - [ATjBparse(I,(i-2)*I) A1 A2 A3 BparBe(I,(I-i-1)*I)]j
end
end
l---------------------------------------------------------------------------~-
l lump_b.1I
l-----------------------------------------------------------------------------
function y-lump_b(RB,IB,object,l)

y=[] j
for i-1:1
for j=1:1
y=[YjBum(BUII(RB.* object(i:i+2,j:j+2»)+IB]j
548 ApPENDIX D

end
end
1-----------------------------------------------------------------------------
1 mat2vec.m
1-----------------------------------------------------------------------------
function Y~at2vec(mat)

[rovO,colO]=Bize(mat)j
y=[] j
for i"'l:rovOj
Y=[Yjmat(i,:)'] j
end
1-----------------------------------------------------------------------------
~ cnndiff.m
1-----------------------------------------------------------------------------
function udot=cnndiff(t,ux)
global AT uOj

udot .. AT*«1-exp(-2*ux» ./ (1+exp(-2*ux»)-ux+uOj

1-----------------------------------------------------------------------------
1 frame.1II
1-----------------------------------------------------------------------------
function y=frame(x)

[rovl,coll]=Bize(x)j
y=266*oneB(rovl+2,coll+2)j
y(2:rovl+l,2:coll+l)-xj
1-----------------------------------------------------------------------------
X vec2mat.m
X-----------------------------------------------------------------------------
function y=vec2mat(vec,l)

[rovl,coll]=Bize(vec)j
nrov-col1/lj
y=[] j
for i=l:nrov
Y=[Yjvec(l,(i-l)*I+l:i*I)]j
end

for i=l:nrov
for j=1:1
if y(i,j»=l
y(i,j)=lj
elBeif y(i,j)<=-l
y(i,j)=-lj
elBe
diBp ( •error happened! .) j
y(i,j)=128+y(i,j)*100j
end
end
BRIEF BIOGRAPHIES OF SPECIAL
ASSISTANTS
Robert C.-H. Chang was born in Taiwan in 1965. He received the B.S. and
M.S. degrees in electrical engineering from National Taiwan University, Taipei,
Taiwan in 1987 and 1989, respectively. He is currently a Ph.D. candidate in
the Electrical Engineering Department at University of Southern California.

From 1987 to 1989, he was a research assistant at National Taiwan University

working on signal and image processing. Since 1992, he has been a research
assistant at USC. In spring 1993, he served as a teaching assistant on Analog
Integrated Circuits in the Electrical Engineering Department. He worked as
a Senior Lecturer on the same course in Fall 1994. He serves as an Associate
Editor of CAS Column in IEEE Circuits and Devices Magazine starting from
March 1995. In addition, he is a co-Guest Editor of a special issue on Jour-
nal of Analog ICs and Signal Processing (Kluwer) in late 1995. He also serves
as an Assistant Editor for the IEEE ISCAS-95 Tutorial Book. His research
interests include advanced VLSI for signal/image processing and telecommuni-
cation, neural networks, and intelligent machines. He received an Outstanding
Academic Achievement Award from USC Office for International Students and
Scholars in April 1993. He is a member of the IEEE and Tau Beta Pi. His
research goal is on technical breakthrough in academia or research institutions.

Tony H.-Y. Wu was born in Taiwan in 1967. He received the B.S. degree
in electrical engineering from National Taiwan University, Taipei, in 1989, and
M.S. degree in electrical engineering from University of Southern California in
1992. Currently, he is a Ph.D. candidate at University of Southern California.

At USC, Mr. Wu was a teaching assistant for two graduate-level courses in

digital highway. He works as a graduate research assistant in the VLSI Signal
Processing Laboratory. He also helps to manage the computing facility and
equipment. He has participated in many research topics including VLSI image
processing and signal transmission, neural networks, and intelligent systems.
He has been an active participant in IEEE activities. He serves on the Technical
Program Committee of the 1995 International Conference on Computer Design
in the Architectures-and-Algorithm Track. He also serves as an Assistant Editor
of the ISCAS-95 Tutorial Book. He has co-authored more than five papers in
IEEE. He is a member of the IEEE. His future goal is exploitation of new
technologies for industrial, scientific, and business applications.

549
550 BRIEF BIOGRAPHIES OF SPECIAL ASSISTANTS

Sa Ho Bang was born in Kyungbook, Korea, in 1958. He received the B.S. and
M.S. degrees in electronics engineering from Hankuk Aviation College (formerly
National Aviation College of Korea), Seoul, Korea in 1982 and 1984, respec-
tively. He received the Ph.D. degree in electrical engineering from University
of Southern California in 1994.

From 1984 to 1989, he worked at Samsung Electronics Co., Ltd., where he was
responsible for the development of telecommunication systems. From 1988 to
1989, he was a project manager working on hand-held mobile phones. Since
1994, he is a technical consultant on system developments and VLSI design
of personal communication systems. His research interests include system de-
sign and VLSI implementation of communication modules. He has received
five Korean and one U.S. patents on communication circuits and systems. He
has co-authored more than 16 papers in international scientific journals and
conferences. He is a member of the IEEE.

Dscal To-Co Chen was born in Taiwan in 1965. He received the B.S. degree
in electrical engineering from National Taiwan University, Taipei, in 1987, the
M.S. and Ph.D. degrees in electrical engineering from University of Southern
California in 1990 and 1994, respectively.

Mr. Chen served as the President of USC Engineering Graduate Student Asso-
ciation during Sept. 1993 to Aug. 1994. At USC, he was a graduate research
assistant in the VLSI Signal Processing Laboratory. He also helped to manage
the computing facility. He has participated in many research topics includ-
ing data compression, image analysis, VLSI and optical interconnects, neural
network learning methods. He was a teaching assistant for two graduate-level
courses in image processing and data compression in Summer 1991 and Fall
1992 semesters. He was the recipient of 1994 USC Leadership Award and 1994
Oversea Chinese Outstanding Youth Award. He has co-authored more than
18 papers in international scientific journals and conferences. He serves on the
Technical Program Committee of 1994 and 1995 IEEE International Confer-
ence on Computer Design in the Architectures and Algorithm Track and on
the Technical Program Committee of 1996 IEEE International Conference on
Neural Networks. He works at Computer and Communication Labs. of ITRI
in Hsin-Chu, Taiwan. He is a member of the IEEE.
 ABOUT THE AUTHORS

Bing J. Sheu was born in Taiwan in 1955. He received the B.S.E.E. degree
(Honors) in 1978 from the National Taiwan University, the M.S. and Ph.D.
degrees in electrical engineering from the University of California, Berkeley, in
1983 and 1985, respectively.

In National Taiwan University, he was the recipient of the Distinguished Book-

Coupon Award for 7 times. In 1981, he was involved in custom VLSI design
for a speech recognition system at Threshold Technology Inc., Cupertino, CA.
From 1981 to 1982, he was a Teaching Assistant in the EECS Department, UC
Berkeley. From 1982 to 1985, he was a Research Assistant in the Electronics
Research Laboratory, UC Berkeley, working on digital and analog VLSI circuits
for signal processing. In 1985, he joined the faculty in Electrical Engineering
Department at University of Southern California and is currently an Associate
Professor with a joint appointment in Biomedical Engineering Dept. He has
been an active researcher in several research organizations at USC including
Center for Neural Engineering (CNE), Signal and Image Processing Institute
(SIPI), Institute for Robotics and Intelligent Systems (IRIS), and Center for
Photonic Technology (CPT). He serves as the Director of VLSI Signal Pro-
cessing Laboratory. Since 1983, he has served as a consultant to the micro-
electronic and information processing industry. His research interests include
high-speed systems, massively paralleled neural networks and image process-
ing, wireless/networked communication system modules, and optoelectronics.
He is an Honorary Consulting Professor in National Chiao Tung University,
Hsin-Chu, Taiwan.

Dr. Sheu was a recipient of the 1987 NSF Engineering Initiation Award and, at
UC Berkeley, the Tse-Wei Liu Memorial Fellowship and the Stanley M. Tasheira
Scholarship Award. He was also a recipient of the Best Presenter Award at
IEEE International Conference on Computer Design in both 1990 and 1991.
He has published more than 160 papers in international scientific and technical
journals and conferences and is a coauthor of the book Hardware Annealing
in Analog VLSI Neurocomputing in 1991, and the book Neural Information
Processing and VLSIin 1995 (Kluwer Academic Publishers). He served on the
Technical Program Committee of IEEE Custom Integrated Circuits Conference.
He served as a Guest Editor on custom VLSI technologies for IEEE Journal of
Solid-State Circuits in the March 1992 and March 1993 Special Issues; a Guest
Editor on computer technologies for IEEE Transactions on VLSI Systems in

551
552 ABOUT THE AUTHORS

June 1993 Special Issue. He is on the Technical Program Committees of IEEE

Int'l Conference on Neural Networks, Int'l Conference on Computer Design,
and Int'l Symposium on Circuits and Systems. At present, he serves as an
Associate Editor of IEEE Transactions on VLSI Systems; an Associate Editor
of IEEE Transactions on Neural Networks; and an Associate Editor of IEEE
Circuits and Devices Magazine. He also serves on the editorial board of the
Journal of Analog Integrated Circuits and Signal Processing, Kluwer Press;
and the editorial board of Neurcomputing Journal, Elsevier Press. He serves
as the Tutorials Chair of 1995 IEEE Int'l Symposium on Circuits and Systems
and an editor of a Tutorial Book focusing on multimedia design and processing
technology (IEEE Press, 1995); and serves as Technical Program Chair of
1996 IEEE Int'l Conference on Neural Networks. He is among the key
contributors of the widely used BSIM model in the SPICE circuit simulator.
He is a Senior Member of IEEE, a member of International Neural Networks
Society, Eta Kappa Nu, and Phi Tau Phi Honorary Scholastic Society.

Joongho Choi was born in Korea, in 1964. He received the B.S. and M.S. de-
grees in electronics engineering from Seoul National University, Korea, in 1987
and 1989, respectively. He received the Ph.D. degree in electrical engineering
at University of Southern California, Los Angeles, CA, in 1993. He is currently
working at IBM Thomas J. Watson Research Center in Yorktown Heights, NY.

In the master-degree project, he worked on a 32-bit RISC microprocessor and

an oversampling AID converter. During 1989-1993, he was a research assistant
at the VLSI Signal Processing Laboratory at USC and participated in several
research organizations at USC including Center for Neural Engineering (CNE),
Signal and Image Processing Institute (SIPI), and Center for Photonic Technol-
ogy (CPT). He has been involved in various information processing VLSI design
projects including artificial neural networks, analog and digital VLSI neuropro-
cessors, mixed-signal data processors for mobile communication, oversampling
AID converter for digital audio, and optoelectronic circuits for photonic in-
terconnection and signal processing. He has published more than 25 papers
in technical journals and conference proceedings. He taught a graduate-level
Course on mixed-signal VLSI systems at USC in Fall 1993. He co-authored a
chapter of the book Analog VLSI edited by M. Ismail (McGraw-Hill Press) in
1994. He serves on the Editorial Board of Journal of Analog ICs and Signal Pro-
cessing (Kluwer Academic Publishers) and served on the Technical Program
Committee of IEEE International Conference on Neural Networks,
1994 &; 1996. His research areas include mixed-signal VLSI design for neural
networks, signal processing, and multimedia communication.

I-D cellular networks, 125
for wireless communication, 125
2-D cellular networks
See also cellular neural network,
94
3-Dneurocube, 467,469
neuron cell, 470
synapse cell, 470
3-D optoelectronic neural system,
382
Adaptive Resonance Theory
(ART),38
Adaptive Solutions Inc., 253, 496
Adaptive vector quantization, 315
Address-event protocol, 486
Analog building block
analog multiplier, 526
differential pair, 523
transconductance amplifier, 525
Analog neural computer from U.
Penn and Corticon Inc., 481
circuit board, 485
neuron chip, 482
software organization, 485
switch-matrix/time-constant
chip, 483
synapse chip, 483
system architecture, 481
Analog tapped-delay line, 136
ANNA neural network board, 472
comparator, 474
multiplier cell, 473
INDEX
neuron cell, 474
optical character recognition
(OCR),477
stroke-based noise removal, 478
weight refresh, 474
Applied AI Machines & Software
Inc., 511
Applied Neurodynamics, 486
ART-2A network, 379
optoelectronic implementation,
380
ARTI
optoelectronic implementation,
377
Artificial life, 354
Associative memory
parallel optical system, 372
Automatic target recognition, 374
Back-propagation learning, 23,
193, 230, 282
backward learning, 24
competitive weight update
method, 27
forward retrieving, 23
learning rate adaptation, 25
momentum method, 26
Newton method, 26
on-chip learning, 283
Optimal Brain Damage method,
27
Bellcore
analog neural-coprocessor
system, 478
554 NEURAL INFORMATION PROCESSING AND VLSI
software package "braincore" ,
480
Berger, Theodore, 16
Bidirectional associative memory
(BAM), 32
energy, 33
Bifurcation, 442
Biological neural neural networks,
15
Biological neural system for target
localization, 339
Bionic eye, 123
Boltzmann Machine, 40
energy, 41
learning algorithm, 42
weight updating rule, 42
optical implementation, 370
Cellular network chip, 397
piecewise-linear function circuit,
402
bidirectional current conveyer,
403
double-MOS differential resistor,
405
nonlinear sigmoid function, 408
optical input, 414
connected component detection
chip, 419
processing circuitry, 416
radon transform chip, 419
sensory circuitry, 415
programmable synapses circuit,
410
synaptic weights and input
circuits, 399
transresistance multiplier, 405
Cellular neural network (CNN),
97-98, 432
equivalent circuit diagram, 100
generalized energy function, 103
hardware annealing, 138
neighborhood cells, 98
QPSK modulation, 133
software listing, 541
stability, 103
taxonomy, 98
template, 98
Cellular nonlinear networks, 97
Chaos, 442
Chaotic neural chip
current-mode design, 454
switched-capacitor (SC)
implementation, 457
Charge-couple device (CCD), 328,
332, 334
Chua's circuit, 442
CMOS implementation, 447
gyrator, 447
piecewise-linear function, 444
Chua, Leon, 123
CNAPS, 253, 431, 496
CNN universal machine, 107
analog program register (APR),
109
analogic computing, 107
application potential, 122
applications, 113
bionic eye, 123
comparison, 107
design example, 112
global analogic programming
unit (GAPU), 108
global architecture, 108
instruction decoder circuit
(IDC), 109
local analog memory, 110
local analog output unit
(LAOU), 110
local communication and control
unit (LCCU), 110
local logic memory (LLM), 110
local logic unit (LLU), 110
Index
logic program register (LPR),
109
software-hardware codesign, 111
superscalar execution, 111
Switch configuration register
(SCR), 109
template information, 113
universal cell, 110
Combinatorial optimization, 126,
131
Computer vision, 75
Corticon Inc., 481
Current-mode circuit
current mirror, 534
differential amplifier, 532
improved current mirror, 535
improved differential pairs, 535
integrator, 530
PWL GmC circuit, 536
Current-mode design, 187
multiplier or divider, 187
Data communication scheme, 230,
428
Decision-feedback equalizers
(DFE),285
Digital communication systems,
285
Digital communication
block diagram of baseband
model, 126
Digital neuroprocessor, 192
Discrete-time cellular network chip
switched-current design, 421
switched-current design
input-output strategies, 428
processing circuitry, 423
Discrete-time cellular neural
networks, 105
energy function, 106
Distributed neuron-synapse
combination, 280
555
Dual-scale topology optoelectronic
processor (D-STOP), 383
Dynamic associative memory, 453
Early vision, 75
Edge-detection chip, 92
ETANN chip, 498
block diagram, 498
interconnection schemes, 499
neuron cell, 499
synapse cell, 499
Extended Kalman filtering (EKF)
algorithm, 287, 289
Floating-gate analog memory, 198
Floating-gate approach, 209
liMOS inverter, 212
variable threshold transistor, 211
Frequency-sensitive
self-organization (FSO)
method, 315
FSO neural processor, 317
Future effort, 13
Fuzzy control, 71
Fuzzy logic, 71
Fuzzy set theory, 71
Fuzzy system, 70, 241
defuzzification, 242
fuzzy numbers, 242
fuzzy rules, 243
fuzzy unit (FIT), 242
MAX and MIN circuit, 246
current-mode circuits, 247
Max and MIN circuit
voltage-mode circuits, 248
membership function, 241
VLSI implementation, 243
FuzzyTECH
Explorer software, 504
MCS-96 code generator, 505
MCU-320 system, 505
556 NEURAL INFORMATION PROCESSING AND VLSI

Gauss-Newton Method, 49 Kohonen network, 36

Gaussian-function neural learning rule, 37
networks, 232 winner-take-all (WTA) function,
Genetic algorithms, 62 36
communication codes, 67
fitness, 63 Laser diode, 388
motion estimation, 69 Light emitting array (LEA), 370
neural network learning, 65 Light emitting diode, 388
replication, 63 Lumped neuron-synapse
Gilbert multiplier, 221, 280 combination, 280
Gradient descent technique, 151
Grand Challenge, 13 MA16 chip, 258, 503
Machine vision, 334, 339, 350
Hamming network, 34, 300 MathWorks Inc., 509
analog implementation, 300 Matlab, 509
Hamming distance, 35 neural network toolbox, 509
Hebbian learning, 21 Maximum-likelihood sequence
Hecht-Nielsen Neurocomputers estimation (MLSE), 125, 285
(HNC) Software Inc., 495 Maximum-likelihood sequence
High-performance computing, 13 estimation (MLSE) receiver
Hippocampal Brain Region, 343 block diagram, 129
Hologram, 372 Maximum-likelihood sequence
Hopfield network, 27 estimator, 127
analog-to-digital converter, 29 MAXNET, 34,300
local minima, 31 Mead, Carver, 16
weight values, 30 Mean field annealing, 151
energy function, 28 Micro-optics, 388
Hybrid opto-electronic approach, Microlenses, 389
374 Microrobot
Hermes, 511
1-1000 chip, 480 insect robot, 362
Ill-conditioned network, 171 living robot, 354
Inform Software Corp., 504 MIT AI Lab, 510
Input neuron, 224 Prometheus, 510
Intelligent machines, 5, 9, 124, 356 Mitsubishi Electric Corp.
Inter-chip communication, 230 self-learning neural network chip,
488
Joint transform correlator (JTC), Moments calculation
380 first moment, 321
second moment, 322
Kennedy, John F., 16 zero moment, 321
Khepera micro-robot, 511 MOS transistor
Index
biased in subthreshold region,
185
linear region, 521
saturation region, 521
Multi-chip module (MCM), 14,
386, 467
Multi-layered neural network, 277
Multi-module system, 488
Multiplication-based synapse cells,
221
synapse weight programming
scheme, 223
Nano-robots, 362
National Semiconductor Corp., 505
Nestor Inc., 501
Nestor learning system, 502
NeuFuz system, 505
NeuralWare Inc., 506
NeuralWork, 506
Neurocomputer, 192
Neurocomputing, 70
NilOOO chip
Ni1000 development system, 501
NTT LSI Lab.
digital neuroprocessor chip, 491
liMOS circuit, 213
winner-take-all circuit, 214
Object orientation, 322
Optical computing, 369
Optical flow, 326,432
Optical flow computing, 432
neuroprocessor, 433
Optical flow velocity, 76
Optical signal processing, 369, 386
Optimal solution
1-D Cellular Networks for
wireless receiving, 125
Cellular Neural Networks, 159
Hopfield Networks, 154
Optimization, 151
557
Output neuron, 225
current-to-voltage conversion,
227
sigmoid function, 230
Perceptron learning, 22
Phase-conjugate mirrors(PCMs),
372
Photodiode array (PDA), 370
Piecewise-linear (PWL) functions,
529
Probabilistic reasoning, 70
Processing element (PE)
optical inputs and electronic
outputs, 383
Processing node (PN), 431
Prometheus robot, 510
Pulse-amplitude modulation
(PAM),288
Pulse-code method, 202
analog implementation, 206
neuron, 207
synapse cell, 206
digital implementation, 202
chopping clocks, 204
neuron, 204
synapse cell, 204
pulse-stream, 202
winner-take-all circuit, 208
Quasi-Newton Method, 47, 60
algorithm, 48
BFGS technique, 48
Radial basis function (RBF), 231,
261
circuit analysis, 235
cuurent-mode design, 536
programmability, 237
simulation, 239
Real World Computing Program,
13
558 NEURAL INFORMATION PROCESSING AND VLSI
Reconfigurability, 280
Regularization theory, 75
Resistive grid, 324, 341, 343
Resistive network, 77, 321
Roska, Tamas, 123
SCAP system, 431
Secant Method, 49
Self-organization neural network,
298
image compression, 314
implementation, 313
Sensorimotor framework, 350
Siemens Nixdorf, 503
Silicon cochlea, 188
block diagram, 190
building element, 188
frequency characteristics, 189
transfer function, 191
transient behavior, 189
Silicon Cortex Board (SCX-l), 486
Silicon retina, 77
neighborhood combinatorial
processing (NCP), 89
adaptive silicon retina, 84
bipolar cell, 80
forward-recursive formula, 80
hexagonal resistive network, 77
horizontal cell, 78
photoreceptor, 78
programmable Boolean array
processor, 88
pseudo-conductance approach,
82
two-bipolar-transistor approach,
85
Simulated annealing, 41, 151
Simulated Cauchy annealing
method, 49
Smart living machines, 354
survival, 360
Smart vision, 336
Smart VLSI, 13
Smart-pixel network, 414
SNAP, 495
Soft computing, 70
Space-time-attribute event
identification code, 488
Spatial light modulator (SLM),
370, 377
SPICE circuit simulation, 513
BSIM model, 513
BSIM_plus model parameters,
519
BSIM_plus model, 185, 513
LEVEL-2 model parameters, 514
LEVEL-4 model parameters, 514
Stability of annealed networks, 165
Stereo correspondence, 334
Subsumption architecture, 510
Superconducting, 389
Josephson devices, 390
SQUIDs, 390
Synapse cells with dynamic
capacitor storage, 195
four matched transistors, 197
modified Gilbert multiplier, 196
Synapse weight storage
digital storage, 202
dynamic capacitor, 195
floating-gate analog memory, 198
SYNAPSE-I, 503
nAPL language, 503
TILShell Software, 508
Time-delay neural network
(TDNN),57
delay block, 57
energy function, 59
simulation results, 59
three-layered TDNN, 58
Togai InfraLogic Inc., 508
Traveling salesman problem
(TSP), 453
 559

Two-neuron network, 172

Ubige Software & Robotics Corp.,

510

Video motion detection, 431

hybrid VLSI neural chip, 431
Visual information processing, 75
Viterbi algorithm, 286

Wafer-scale integration, 14, 467

Werblin, Frank, 123
Winner-take-all (WTA) circuit,
300, 303
analysis and design, 307
cascading of stages, 308
distributed biasing, 309
dynamic current steering, 310
experimental results, 312
schematic diagram, 305
velocity-selective neuroprocessor,
439
Wireless channel equalizer, 283
neural-based equalizer, 286
switched-capacitor analog delay
circuit scheme, 290
system architecture, 286
system environment, 292
training algorithm, 288
VLSI implementation, 290