Current Equations for MOSFETs in Saturation MOSFETs are in saturation when they are being used in analog devices

and when a digital device is switching. The source-drain current, ID is described by the following equations For PMOS devices

ID =

W L

p C ox 2

(Vsg + VTP ) 2

This is sometimes written in the following two forms

ID =
Also

W 2 2 k p ' (Vsg + VTP ) = K p ' (Vsg + VTP ) L

gm =

ID Vsg W = 2 k p ' (Vsg + VTP ) L W =2 k p ' ID L

ID Vsg W 2 ID = k p ' (Vsg + VTP ) L W ID = k p ' (Vsg + VTP ) L gm =

(V
For NMOS devices

sg

+ VTP ) =

ID W kp' L

ID =

W n C ox 2 (V gs VTN ) L 2 W 2 2 k n ' (V gs VTN ) = K n ' (V gs VTN ) L ID Vsg W k n ' ID L

this is sometimes written in the following two forms

ID =
Also

gm = =2

Below is a diagram showing two views of a MOSFET (could be either an NMOS or PMOS)
Gate Drain Gate Drain

Source

Source

Drain overlap (XL or LD)

4 L

Gate length (channel length) = L Gate width (channel width) = W Gate area = WL Source Area = (4 )W Drain Area = (4 )W Perimeter of source/drain: 2 (4 +W)

Gate length (channel length) = L Effective Gate length = L-LD

Small signal model:

G (gate)

Cgd

D (drain)

Cgs

ro gmVgs Cd

Cs

S (source)

We will be designing using the AMIS .5 um (micron) process. Below is a table summarizing the parameters in the equations above: From: http://www.mosis.org/cgi-bin/cgiwrap/umosis/swp/params/ami-c5/t3af-params.txt
Parameters common to NMOS and PMOS devices Parameter W L Lambda () PMOS or NMOS minimum sized device Cox Parameters specific to PMOS devices Parameter p k= ( p Cox)/2 VTP Cjsw Cj Cjswg Cgdo Parameters specific to NMOS devices Parameter n k= ( n Cox)/2 VTN Cjsw Cj Cjswg Cgdo

description Gate width of either NMOS or PMOS Gate Length for either NMOS or PMOS Design parameter for scalable rules Smallest possible PMOS or NMOS device Gate capacitance per unit area

value .35 microns W = 3 = 10.5 m L = 2 = .75 m ~2.5 fF/um2

description Effective mobility of holes ------PMOS Threshold Voltage Source/drain Side wall capacitance (F/m) Source/drain bottom plate capacitance Units (F/m2) Source/drain Side wall capacitance on drain side Units (F/m) Drain overlap capacitance (F/m) Description Effective mobility of electrons ------NMOS Threshold Voltage Source/drain Side wall capacitance: (F/m) Source/drain bottom plate capacitance Units (F/m2) Source/drain Side wall capacitance on drain side: Units (F/m) Drain overlap capacitance (F/m)

value

value 446.9 cm2/V-sec

The input capacitance of a digital device can be determined as follows: Cg = Cox (WxL) where WL is the gate area.

How to determine Capacitance:

Saturation Linear Cgs[i] Cox W L[ii] Cox W L Cgd[i] Cox W LD = Cdgo W 0

Both linear and Sat

Cd and Cs (to ground) Cj (src/drain area) + Cjswg(W) + Cjsw [W + 2 (source drain length)][iii]

i ii iii

For small devices one has to also consider add in the fringe capacitance = Cfringe (W) Many use Cgs = 2/3 Cox W L for saturation. This is more conservative. What this is is: Cj (area of the source or drain) + Cjsw (perimeter of source or drain). For the diagram above this would be Cj (W 4) + Cjsw 2 (W+4). Cjsw is called side wall capacitance and Cj is bottom plate capacitance.