NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA

END SEMESTER EXAMINATION, 2018

SESSION: 2017 – 2018 (Spring)
M.Tech. 2nd Semester

Subject code: EC-626 Subject Name: Low Power VLSI Design VLSI & EI
No. of pages: 1 Full Marks: 50 Duration: 3 Hours

Figures at the right hand margin indicate marks.

All parts of a question should be answered at one place.

Answer all questions

Q.No. Particulars Marks
1. a) Discuss briefly the basic structure of an SRAM. 3
b) Identify the power dissipation sources of SRAM and then briefly
discuss three low power design techniques. 4
c) Describe the basic operation of a standard DRAM. 3

2. a) Discuss the operation of Carry Look Ahead Adder Circuit. Comment 4

on its advantages.
b) With the help of a schematic circuit describe the structure of a general
3
Data Path Unit.
c) Perform the following multiplication using Radix-4 Modified Booth 3
Algorithm: M= - 10, R= - 13.

3. a) Describe different power minimization synthesis techniques. 4

b) Explain with an example how hardware software co-design can reduce
capacitance and power consumption of VLSI Circuits. 3
c) Explain how Self-refreshing technique can be used to reduce the leakage 3
power of a DRAM.

4. a) Discuss different leakage power reduction techniques. 6

b) Between Clock Gating and Power Gating, which one will be more 4
efficient to reduce power and why?

5. a) Describe how Adiabatic Logic circuits can be used to address the low 5
power issues.
b) Discuss different techniques of Load Capacitance minimization in VLSI 5
architecture.