AJAY KUMAR 221EC3360 LAB-S VERMA Lab 5: Study of Flip-Flops and Register 1, Design of Flip-Flops:- a) Je Flop: : To design a J-K Flip-Flop using vivado software, Theory : J-K Flip-Flop is the most versatile of the basic flip flops. J-K flip-flop can be treated as an alteration of the S-R flip-flop. J represents SET, and 'K’ represents CLEAR. In the JK flip-flop, the ‘S’ input is known as the ‘I’ input, and the “R’ input is known as the ‘K” input. The output of the JK flip-flop does not modify if both ‘J’ and K’ are ‘0°, If both the inputs are ‘1’, then the output dial to its free. The figure shows the circuit diagram of a JK flip-flop. JK Flip Flop Clock, Pulse Truth Table: Same | Clock Input Output Description asfor | Clk J K Q Q’ SR x 0 0 1 0 Memory Latch [~ x 0 0 0 1 no change a 0 1 1 0 Reset Q>50 x 0 1 o 1 V 1 0 0 1 Set Q>>1 x 1 oO 1 o Toggle | —V_ 1 1 0 1 Toggle action | V 1 1 1 0AJAY KUMAR 221BC3360 VERMA Code: LAB-S “timescale Ins Ips module jk_fifelk, .q.qbar); input clk,,k; output reg ¢; ‘output gbar; always @(posedge clk) begin end assign qbar = ~q; endmoduleAJAY KUMAR 221BC3360 VERMA Test bench: LAB-S timescale Ins / Ips module jk_tb; reg IK, CLK; wire Q, QBAR; jk_AT dut(.q(Q), qbar(QBAR), (0), -K(K), elk(CLK)); initial begin CLK=0; forever #10 CLK = ~CLK; end initial begin I= 1; K=0; #100; J= 0; K= 1; #100; J- 0; K~ 0; #100; J= 1; K=1; #500; J= 0; K= 1; #100; J= 0; K- 0; #100; J= 1; K=I; end endmodule Synthesis Report: RESOURCES | UTILIZATION | AVAILABLE UTILIZATION Total power % on chip LUT’s 1 53200 0.00 FFs 1 106400 0.00 1371W 10°s 5 200 2.50AJAY KUMAR 221BC3360 LAB-S VERMA Simulation results : awaansun Conclusions: ‘Thus by using vivado software a JK flip-flop is designed and simulated, Results were observed and compared with the values in truth table. The JK flip-flop designed is working properly and the results are matched with the desired results.AJAY KUMAR 221BC3360 LAB-S VERMA T Elip-£ Aim: To design aT Flip- Flop using a vivido software. Theory he T flip-flop is also called toggle flip-flop. It is a change of the JK flip-flop. The T {ip flop is received by relating both inputs ofa JK flip-flop. The T flip-flop is received by relating, the inputs ‘J’ and ‘K”. When T = 0, both AND gates are disabled. Therefore, there is no change in the output. When T= 1, the output toggles. The diagram demonstrates the circuit diagram of a T flip-flop Flip Flop Clock Pulse Truth Table: Previous Next a a Ble} olola Rlole] colo olFRl el] colo olR}ole RlololeAJAY KUMAR, 221BC3360 VERMA Cod LAB-S module t_fi(T,Cik,Q,Qbar ); input T,CIk; output Q,Qbar; reg Q,Qbar; always@(T,posedge(Clk)) begin if(T==0) begin Q =Il; Qbar=1'b0; end else endmodule Test bench: module t_ff tb; reg T; reg Clk; wire Q: wire Qbars 1 faut (11), Clk(Clk), QQ), Qbar(Qbar) % initial Clk = 0; always #100 Clk = ~C! initial always #100 TT; initial beginAJAY KUMAR 221BC3360 LAB-S VERMA Synthesis report: RESOURC UTILIZATION | AVAILABLE | UTILIZATION | Total power on % chip LUT's 1 33200 0.00 1371W FFs i 10640 0.00 0 10's 5 200 2.50 Simulation results: auwean " 2 Conclusions: Thus by using vivado software a T flip-flop is designed and simulated. Results were observed and compared with the values in truth table. The T flip-flop designed is working properly and the results are matched with the desired resultsAJAY KUMAR, 221BC3360 LAB-S VERMA ()D-flinfon: ‘Aim: To design a D flipflop using vivado software. Theory: A D (or Delay) Flip Flop is a digital electronic circuit used to delay the change of state of its output signal (Q) until the next rising edge of a clock timing input signal occurs. ce—t > (@) Logie diagram with Nand gates (© Transtion table Code: module dfi(d,clk,clear,g,qbar); input d, elk, clear; output reg q, qbar; always@(posedge clk) begin if(clear= 1) begin g endmoduleAJAY KUMAR 221BC3360 VERMA Testbench: module dff th; reg D, CLK.reset; wire Q, QBAR; LAB-S df dut(.q(Q), bar(QBAR), .clear(reset), d(D), .clk(CLK)); // instantiation by port name. initial begin CLK-0; forever #10 CLK = ~CLK; end initial begin reset=1; D ); #100; reset=0; D #100; D<=0; #100; D<=1; end endmodule Synthesis reports: RESOURCES | UTILIZATION | AVAILABLE | UTILIZATION% | Total power on chip LUT's 1 53200 0.00 FFs 2 106400 0.00 0.63W 10's 3 200 2.50AJAY KUMAR 221BC3360 LAB-S VERMA Simulation result Conclusions: ‘As we can see from th , output Q is also 0 with a small delay. This delay can be eased based on the user requirements. Hence a D filp-flop is designed using Vivado software. imulation results that when increased or d And results are observed and compared with the desired values from the truth table of D flip-flop. 10