Bit/Field Name Type Reset Description

Invalid Data Raw Interrupt Status

Value Description
0 An interrupt has not occurred.
An interrupt is pending because a bit that was previously
programmed as a 0 is now being requested to be programmed
as a 1.
1
This bit is cleared by writing a 1 to the INVMISC bit in the FCMISC
register.
10 INVDRIS RO 0
Pump Voltage Raw Interrupt Status
Value Description
0 An interrupt has not occurred.
An interrupt is pending because the regulated voltage of the
pump went out of spec during the Flash operation and the
operation was terminated.
1
This bit is cleared by writing a 1 to the VOLTMISC bit in the FCMISC
register.
9 VOLTRIS RO 0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8:3 reserved RO 0
EEPROM Raw Interrupt Status
This bit provides status EEPROM operation.
Value Description
0 An EEPROM interrupt has not occurred.
1 An EEPROM interrupt has occurred.
This bit is cleared by writing a 1 to the EMISC bit in the FCMISC register.
2 ERIS RO 0
Programming Raw Interrupt Status
This bit provides status on programming cycles which are write or erase
actions generated through the FMC or FMC2 register bits (see page 505
and page 515).
Value Description
0 The programming or erase cycle has not completed.
1 The programming or erase cycle has completed.
This status is sent to the interrupt controller when the PMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register.
1 PRIS RO 0
508 January 19, 2013
Texas Instruments-Advance Information
Internal Memory