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  • FCRIS Register (See Page 507)

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    Mustafa Demir
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    This document describes the bit/field names, types, reset values, and descriptions of status and clear registers. It includes fields for invalid data masked interrupt status and clear (INVDMISC), voltage masked interrupt status and clear (VOLTMISC), and EEPROM masked interrupt status and clear (EMISC). Each field reads as 0 when the interrupt has not occurred and 1 when the interrupt has occurred and been unmasked. Writing a 1 clears both the specific field and a corresponding bit in another register.

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    This document describes the bit/field names, types, reset values, and descriptions of status and clear registers. It includes fields for invalid data masked interrupt status and clear (INVDMISC), voltage masked interrupt status and clear (VOLTMISC), and EEPROM masked interrupt status and clear (EMISC). Each field reads as 0 when the interrupt has not occurred and 1 when the interrupt has occurred and been unmasked. Writing a 1 clears both the specific field and a corresponding bit in another register.

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    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
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    6 views1 page

    FCRIS Register (See Page 507)

    Uploaded by

    Mustafa Demir
    This document describes the bit/field names, types, reset values, and descriptions of status and clear registers. It includes fields for invalid data masked interrupt status and clear (INVDMISC), voltage masked interrupt status and clear (VOLTMISC), and EEPROM masked interrupt status and clear (EMISC). Each field reads as 0 when the interrupt has not occurred and 1 when the interrupt has occurred and been unmasked. Writing a 1 clears both the specific field and a corresponding bit in another register.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
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    of 1

    Bit/Field Name Type Reset Description

    Invalid Data Masked Interrupt Status and Clear


    Value Description
    When read, a 0 indicates that an interrupt has not occurred.
    A write of 0 has no effect on the state of this bit.
    0
    When read, a 1 indicates that an unmasked interrupt was
    signaled.
    Writing a 1 to this bit clears INVDMISC and also the INVDRIS
    bit in the FCRIS register (see page 507).
    1
    10 INVDMISC R/W1C 0
    VOLT Masked Interrupt Status and Clear
    Value Description
    When read, a 0 indicates that an interrupt has not occurred.
    A write of 0 has no effect on the state of this bit.
    0
    When read, a 1 indicates that an unmasked interrupt was
    signaled.
    Writing a 1 to this bit clears VOLTMISC and also the VOLTRIS
    bit in the FCRIS register (see page 507).
    1
    9 VOLTMISC R/W1C 0
    Software should not rely on the value of a reserved bit. To provide
    compatibility with future products, the value of a reserved bit should be
    preserved across a read-modify-write operation.
    8:3 reserved RO 0
    EEPROM Masked Interrupt Status and Clear
    Value Description
    When read, a 0 indicates that an interrupt has not occurred.
    A write of 0 has no effect on the state of this bit.
    0
    When read, a 1 indicates that an unmasked interrupt was
    signaled.
    Writing a 1 to this bit clears EMISC and also the ERIS bit in the
    FCRIS register (see page 507).
    1
    2 EMISC R/W1C 0
    Programming Masked Interrupt Status and Clear
    Value Description
    When read, a 0 indicates that a programming cycle complete
    interrupt has not occurred.
    A write of 0 has no effect on the state of this bit.
    0
    When read, a 1 indicates that an unmasked interrupt was
    signaled because a programming cycle completed.
    Writing a 1 to this bit clears PMISC

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