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INT0(Divide by Zero Error)

 The interrupt with type number 0 is dedicated to ‘divide by


zero error’ .

 This interrupt is an ‘error generated’ interrupt.

 On division, if quotient register is not large enough to contain


the quotient, this interrupt is generated automatically.

 Dedicated type 0 for this case means that the corresponding


interrupt vector in the interrupt vector table is available at
0000:0000.
INT1(Single Stepping)
 This type number is dedicated for ‘single stepping’ or
‘trace’.

 The ISR for viewing the register and memory contents will
be pointed by the vector of interrupt type 1.
INT 2 (Non Maskable Interrupt)
 This interrupt is corresponds to the vector of hardware
interrupt NMI.

 When an interrupt is received on the pin NMI of the


processor, a type 2 interrupt occurs- this means that the
ISR for NMI must be written in the address pointed by the
corresponding IVT content.
INT 3(Breakpoint Interrupt)
 This is the breakpoint interrupt, which is useful for
debugging.

 Since setting breakpoints is an important aspect of


debugging, the breakpoint interrupt is special in that it is
single byte instruction with the code CCH.

 When we set breakpoints in debugging, what is really


happening is that this code(CCH) is inserted and getting
executed at the position in the program where the break
point is set.
INT 4(Overflow Interrupt)
 This interrupt corresponds to the overflow flag.

 If the OF is set, this interrupt occurs but not


automatically.

 An instruction INTO must be written after the program


segment which is likely to cause the OF to be set.
MOV AL, NUM1
ADD AL, NUM2
INTO

The last line of this program segment can pass control to


the ISR written for INT3, if the OF is set by the result of
addition. Otherwise, INTO acts as a NOP instruction.
Allocation of Interrupt Type Number
 Interrupts with type number 0 to 4 has been allotted pre-
defined actions related to the CPU.

 Interrupts with type numbers 5 to 31 are reserved by Intel


for special uses and for future processors.

 Some interrupts are used for various hardware and I/O


devices and some for error conditions of the higher
processors in the x86 family.

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