8086 Interrupt

INTERRUPT
 Breaks the normal sequence of execution
 Diverts to ISR (interrupt service routine)
 Control is transferred back to main program

NESTED INTERRUPTS
 Sequence of appearance of interrupts
 Interrupt within interrupt
 CPU – multiple interrupt processing capability
 2 INTERRUPT PINS
NMI
 non maskable interrupt

INTR
 masked using interrupt flag (IF)
 256 types from 00 to FF
 Programmable interrupt controller to handle more
than one interrupt
INTERRUPT CYCLE
Two types
1. External interrupt:
- Generated outside processor
- Example: Keyboard

2. Internal interrupt:
- Generated inside processor
- Example: Divide by zero, Overflow
 INTA PIN
If INT request
 CPU checks IF Flag
 If set
• sends acknowledge

Else
• Request ignored

NMI, TRAP & Divide by Zero are independent of IF

flag
 After acknowledgement, CPU computes vector
address based on type if interrupt
 Content of IP, CS and PSW are pushed to stack
 IF flag is cleared
 TF is also cleared, after every single step of
interrupt
 Control is transferred to ISR
 New address will be in vector table
 After ISR execution last instruction should be
IRET
 IRET – retrieves IP, CS and PSW and then starts
executing main program
NON MASKABLE INTERRUPT
 NMI – highest priority among external interrupts
 TRAP – (Type 1) highest priority among internal
interrupts except Divide by zero (Type 0)
 NMI pin must be free of logical bounces

to avoid erratic responces

 MASKABLE INTERRUPT
 INTR has low priority compared to NMI
 If IF is set processor responds to INTR
 If IF is reset processor will not serve any interrupt