Control of Dual-Output DC Duty Cycle and Frequency

Article
Control of Dual-Output DC/DC Converters Using

Duty Cycle and Frequency
Yoshinori Matsushita 1,2, *, Toshihiko Noguchi 1 , Kazuki Shimizu 3 , Noritaka Taguchi 2 and
Makoto Ishii 2
1 Graduate School of Science and Technology, Shizuoka University, Hamamatsu 432-8561, Japan;
noguchi.toshihiko@shizuoka.ac.jp
2 Yazaki Research and Technology Center, YAZAKI Corporation, Susono, Shizuoka 410-1194, Japan;
noritaka.taguchi@jp.yazaki.com (N.T.); makoto.ishii@jp.yazaki.com (M.I.)
3 Graduate School of Integrated Science and Technology, Shizuoka University, Hamamatsu 432-8561, Japan;
shimizu.kazuki.16@shizuoka.ac.jp
* Correspondence: yoshinori.matsushita@jp.yazaki.com

Received: 28 September 2020; Accepted: 10 November 2020; Published: 13 November 2020
Abstract: As part of the integration process of the auxiliary power systems of electric vehicles,
plug-in hybrid vehicles and fuel cell vehicles, this study proposes a method to control two different
voltage types using two control factors of the rectangular alternating waveforms contained in DC/DC
converters, namely the duty cycle and frequency. A prototype circuit consisting of an H-bridge
inverter, a transformer, two series resonant filters and two diode bridge circuits was constructed.
The H-bridge inverter was connected to the primary side of the transformer and the diode bridge
rectifier circuit was connected to the secondary side in parallel. Series resonant filters were inserted
between one of the diode bridge circuits and the transformer. Thereafter, the proposed control method
was applied to the transformer voltage of the prototype circuit. Although the circuit operation became
complex owing to the circulating current flowing between the ground (GND) of the two output
circuits, it exhibited ideal static and dynamic characteristics, thereby confirming the possibility of
controlling two voltages with the duty cycle and frequency control factors. The results of the efficiency
evaluation and loss analysis demonstrated a minimum efficiency of 68.3% and a maximum efficiency
of 88.9%. As the output power of the circuit containing the resonant filters increased, the current peak
value increased and the circuit became less efficient.
Keywords: dual output; DC/DC converter; pulse width and frequency control; auxiliary power
source; duty cycle; frequency
1. Introduction
1.1. Research Motivations

Considering that the transportation field is estimated to be responsible for 26% of all CO2
emissions globally [1], the reduction of CO2 emissions from vehicles is an effective measure to curb
global warming. In an attempt to reduce CO2 emissions, the vehicle market is switching from gasoline
cars to electric vehicles (EVs), plug-in hybrid vehicles (PHVs) and fuel cell vehicles (FCVs), which are
equipped with high-voltage sources that enable motor driving. The market for such vehicles is
expected to grow continually in the coming years [2]. The auxiliary power sources of EVs, PHVs and
FCVs use isolated DC/DC converters with input that provides high-voltage power for driving [3,4].
With the electrification of conventional functions (drive by wire) and the sophistication of internal
environments, the number and types of auxiliary loads are increasing continually. That is, the power
World Electric Vehicle Journal 2020, 11, 72; doi:10.3390/wevj11040072 www.mdpi.com/journal/wevj

World Electric Vehicle Journal 2020, 11, 72 2 of 20
capacity required for the auxiliary power supply is increasing and, depending on the use conditions
of the car, the power consumption of the auxiliary load may have a significant impact on the total
vehicle power consumption [5,6]. One factor that increases the power consumption is the additional
conduction losses caused by the large current that flows when a heavy load is driven with a 12 V
power supply. An option for reducing these conduction losses is to set the power supply voltage
of the auxiliary system to 48 V and to reduce the current value [7,8]. However, owing to the costs,
part supplies and maintenance service involved, it is difficult to make all loads for a 12 V power supply
compatible with a 48 V power supply and, as a result, the demand for loads requiring a 12 V power
supply remains. For this reason, the auxiliary power supply requires a dual system that supports both
48 V and 12 V.
The configuration known as the 48-V mild hybrid, standardized as LV148 in Europe, supplies a
dual system of 48 V and 12 V by generating a direct current of 48 V in the alternator of engine-powered
vehicles and producing a 12 V power supply with a non-isolated bidirectional DC/DC converter of
48 V and 12 V [9]. However, the fact that two power conversions are required to generate 12 V makes
this system inefficient. Moreover, the system contains two sets of power supply equipment, making it
expensive and bulky.
1.2. Literature Review

To overcome these issues, numerous studies have been conducted on single-input, dual-output
DC/DC converters that input high voltages for driving and output 48 V and 12 V, as well as bidirectional
multiport converters that make use of a power supply from renewable energy sources installed in cars
and V2X [10–16]. On the other hand, studies have been carried out on mastering GaN devices since
GaN devices provide a high switching speed that enable operations at higher frequencies than those of
conventional Si and SiC devices, which makes power converters more compact and efficient [17–21].
The studies of the auxiliary power sources of cars have exhibited functions such as bidirectional
power transmission and four or more inputs/outputs. However, as a result of the multiple functions,
the number of switching devices sending control signals has increased, thereby increasing the total
wiring length of the control signals. As control signals are vulnerable to noise, they are incompatible with
the high frequencies resulting from the use of GaN devices or increases in the power capacity of auxiliary
equipment. Furthermore, when the total wiring length of the control signal increases, the layout
becomes more complex to prevent induction noise from the power section. However, few studies have
focused on the issue.
1.3. Contribution
To attenuate this problem, the authors have proposed a method for controlling single-input,
dual-output DC/DC converters as integrated auxiliary power sources for EVs, PHVs and FCVs,
with fewer control signals and a shorter wiring length [16]. The method has novel characteristics
switching devices on input port are able to control two output voltages, which is not shared by
References [10–15]. However, Reference [16] only had demonstrated the efficacy of the method with
simulation. In this paper, therefore, the validity of the method is verified using an actual circuit with
1 kW output.
2. Overview of Proposed Control Method and Main Circuit Configuration
2.1. Overview of Proposed Control Method and Main Circuit Configuration

Figure 1 presents the concept of the proposed control method. The two output voltages Vout1
and Vout2 are controlled by two control factors, namely the duty cycle and frequency (period) with
rectangular alternating voltage. This control method requires the main circuit to contain waveforms
with a duty cycle and frequency, as well as elements with output voltages that vary according to
the changes in the duty cycle and frequency. Therefore, in this study, the isolated DC/DC converter
depicted in Figure 2 was adopted as a simple main circuit to validate the proposed control method.
World Electric Vehicle Journal 2020, 11, x 3 of 21
The isolation approach used consists of a transformer, the primary side of which is an input capacitor
(C
Thein ) isolation
and an H-bridge
approach inverter that is formed
used consists by the switching
of a transformer, devices S1,
the primary sideS2, ofS3 and S4.
which Theinput
is an gate
signals G1, G2, G3 and G4 are input to each switch, respectively. G1
capacitor (Cin) and an H-bridge inverter that is formed by the switching devices S1, S2, S3 and S4. to G4 generate a rectangular
alternating
The voltage
gate signals G1,with
G2,theG3dutyand cycle
G4 are and frequency
input to each control
switch, factors and this G1
respectively. voltage
to G4is generate
applied to a
the primaryalternating
rectangular side of the voltage
transformer.with theOndutythe secondary side of thecontrol
cycle and frequency transformer,
factorsaand rectifier circuit of
this voltage is
output voltage
applied Vout1 consisting
to the primary side of the of diodes D11, D12,
transformer. On D13, D14, Lout1 side
the secondary and C theand,
ofout1 similarly, aa rectifier
transformer, rectifier
circuit of
circuit of output voltageVV
outputvoltage out2
out1
consisting
consisting of D21,D11,
of diodes D22,D12, D23, D24,
D13, Lout2
D14, and
Lout1 andCout2
Cout1are
and, connected
similarly,in a
parallel. A series of resonant filters consisting of L srA , C srA , L srB and C srB
rectifier circuit of output voltage Vout2 consisting of D21, D22, D23, D24, Lout2 and Cout2 are connected are inserted between the
latter
in diode A
parallel. bridge
seriescircuit and thefilters
of resonant transformer.
consisting Thisofseries
LsrA, C resonant filter changes the impedance to an
srA, LsrB and CsrB are inserted between the
arbitrary
latter diodevalue by operating
bridge circuit and thethefrequency
transformer.and thereby
This series controls
resonantthe output voltage.the
filter changes Toimpedance
maintain the to
symmetry of the operation, the parameters of the two series resonant
an arbitrary value by operating the frequency and thereby controls the output voltage. To filters must have the same values.
maintain
Impedance
the symmetry changes
of the caused
operation, by frequency
the parametersaffect of
thethe
impedances
two series of both the
resonant seriesmust
filters resonant
have filter and
the same
the subsequent
values. Impedance smoothing
changesfilter.
caused In this
by frequency = Lsr2the
case, if Lsr1affect =L sr and Csr1 =
impedances sr2 = the
ofCboth Csr , series
the impedance
resonant
of the series resonant filter
filter and the subsequent smoothing (Z sr ) to the frequency of the transformer voltage
filter. In this case, if Lsr1 = Lsr2 = Lsr and (f ) and the
tx Csr1 = Csr2 impedance
= Csr, the
following the
impedance of smoothing filter of the
the series resonant Vout2
filter (Zsrside (Zsm2
) to the ) can respectively
frequency be expressed
of the transformer as (ftx) and the
voltage
impedance following the smoothing filter of the V out2 side (Zsm2) can respectively be expressed as
1
Zsr ( ftx ) = j ωLsr − 1 , (1)
Zsr f = j ωLsr − ωC,sr (1)
ωCsr
 
Rout2 Rout2 
 2𝜔 (
𝑅𝑜𝑢𝑡2 Rout2 2 Cout2 
2ω2 𝐶)𝑜𝑢𝑡2 
Zsm2 ( ftx ) =Z ftx = + j ( 2ω
2𝜔 )𝐿L −− , , (2)
 
2 1+ 2ω 22 R𝑜𝑢𝑡2 𝐶𝑜𝑢𝑡2
2 2
+j out2
𝑜𝑢𝑡2 2 2
1+ 2𝜔 2 𝑅𝑜𝑢𝑡2 2 𝐶𝑜𝑢𝑡2
 (2)
1 + (2ω) Rout2 Cout2 2 
 1 + (2ω) Rout2 Cout2 2 2
where ω
where ω== 2πf tx and Rout2 is the load resistance value of the Vout2-side circuit. Considering that the
2πftx and Rout2 is the load resistance value of the Vout2 -side circuit. Considering that the
frequency of the waveforms doubles
frequency of the waveforms doubles after
after the
the diode bridge full-wave
diode bridge full-wave rectification,
rectification, the
the frequency
frequency in
in
Z sm2 is doubled. With these values, Zout2, which is the impedance of the Vout2-side circuit for ftx, can be
Zsm2 is doubled. With these values, Zout2 , which is the impedance of the Vout2 -side circuit for ftx , can be
approximated
approximated as as

out2 ( f𝑓
Z|𝑍 tx ) |= |Z sr|| ++|Z|Zsm2
= 22|Z
out2 sr|.. |. sm2
(3)
(3)
If the condition is satisfied whereby |Z out2 (ftx
|Zout2 )| decreases or increases monotonically within the
tx)|
operating frequency range, f
range, ftx tx and |Z
|Zout2 |
out2| exhibit a one-to-onerelationship
exhibit a one-to-one relationshipand andVVout2 can be
out2 can be controlled
controlled
by fftx
tx.. Moreover, circuit V
Moreover, as the side circuit Vout1 isaa typical
out1 is typical diode diode bridge rectifier circuit,VVout1
rectifier circuit, can be
out1 can be changed
changed
by the duty cycle of the secondary side voltage of
cycle of the secondary side voltage of the transformer (D the transformer (D ). Therefore,
txtx). Therefore, Vout1 V out1 is mainly
is
controllable by Dtxtxand
by D andVVout2
out2is is mainly
mainly controllable
controllable byby ftx but
ftx but changes
changes in Dintx D
affect Vout1Vas
tx affect well
out1 as as
well as,
Vout2
V out2 , whereas
whereas changes
changes in ftx affect
in ftx affect Vout2
Vout2 as well as as
well as. V
Vout1 out1 . Thus,
Thus, it ispossible
it is not not possible to control
to control Vout1 Vand and
out1 V out2
V out2 independently
independently usingusing Dtx and
Dtx and ftx , respectively.
ftx, respectively. However,However, by by adding
adding a gap
a gap ininthetheresponse
responsespeed speed of
both output voltages, it is possible to prevent interference interference in in the
the control
control by by DDtxtx and ftx tx and to adjust
both output voltages to the target values.
Figure 1.
Figure Concept of
1. Concept of dual-output
dual-output control.
control.
Figure 2. Circuit configuration for applying proposed control method.

Figure 2. Circuit configuration for applying proposed
proposed control
control method.
method.
Although
Although the proposed control method requires the incorporation of a circuit such as aa series
series
Although the the proposed
proposed control
control method
method requires
requires thethe incorporation
incorporation of of aa circuit
circuit such
such asas a series
resonant
resonant filter to link the frequency and control target, it is possible to control two output voltages
resonant filter
filter to
to link
link the
the frequency
frequency and and control
control target,
target, itit is
is possible
possible to
to control
control two
two output
output voltages
voltages
using
using only the switching devices necessary to generate an AC rectangular waveform voltage
voltage (that
(that is,
using only
only thethe switching
switching devices
devices necessary
necessary to to generate
generate an an ACAC rectangular
rectangular waveform
waveform voltage (that is,
is,
without
without adding
adding new
new switching
switching devices
devices for
for dual-output
dual-output control).
control). This
This reduces
reduces thethe layout
layout restrictions
restrictions to
without adding new switching devices for dual-output control). This reduces the layout restrictions
to prevent
prevent inductive
inductive noisenoise
fromfrom the large
the large current
part ofpart of the mainresulting
circuit, resulting
in greaterin greater
to prevent inductive noise from the current
large current the main
part circuit,
of the main circuit, resulting flexibility
in greater
flexibility
in the in the
circuit circuitMaterials
design. design. Materials
and and Methods
Methods should should
be be described
described with with sufficient
sufficient details details
to to
allow
flexibility in the circuit design. Materials and Methods should be described with sufficient details to
allow
others others to replicate and build on published results. Please note that publication of your
allow to replicate
others and build
to replicate and on build
published results. Please
on published results. note that publication
Please of your manuscript
note that publication of your
manuscript
implicates implicates that youallmust make data,all materials,
computerdata, code computer codeassociated
and protocols
manuscriptthat you must
implicates thatmakeyou mustmaterials,
make all materials, data, and protocols
computer code and protocols with
associated
the publicationwith the publication available to readers. Please disclose at the submission stage on any
associated withavailable to readers.
the publication Pleasetodisclose
available readers. at Please
the submission
disclose atstage
the any restrictions
submission stage the
any
restrictions
availability on
of the availability
materials or of materials
information. Newor information.
methods and New methods
protocols shouldand beprotocols
described should
in be
detail
restrictions on the availability of materials or information. New methods and protocols should be
described
while in detail while
well-established well-established
methods methods
can be briefly can be
described andbriefly describedcited.
appropriately and appropriately cited.
described in detail while well-established methods can be briefly described and appropriately cited.
2.2. Operating Principles of Proposed Control Method
2.2. Operating Principles of Proposed Control Method
Figure 3 presents a block diagram of the proposed control method. The calculation is conducted
Figure 3 presents a block diagram of the proposed control method. The calculation is conducted
by a Field Programmable Gate Array (FPGA) (FPGA) and the signals input into the FPGA are the feedback
by a Field Programmable Gate Array (FPGA) and the signals input into the FPGA are the feedback
signals V Vfb1 and Vfb2 fb2, , which
which are obtained
obtained bybydividing
dividingby byVV andVVout2
out1and
out1 out2, respectively.
respectively.VVfb1 and V
fb1 and Vfb2
fb2 are
signals Vfb1 fb1 and Vfb2, which are obtained by dividing by Vout1 and Vout2, respectively. Vfb1 and Vfb2 are
input into the FPGA via the AD converter and and thethe differences
differencesfromfromthetherespective
respectivetargettargetvaluesvaluesVVout1out1*
input into the FPGA via the AD converter and the differences from the respective target values Vout1*
and V * are input into the PI calculation part (PI and PI ). The output
and Vout2 * are input into the PI calculation part (PI1 and PI2 ). The output signal from PI1 contains
out2 1 2 signal from PI 1 contains the
and Vout2* are input into the PI calculation part (PI1 and PI2). The output signal from PI1contains the
information
the information of theof thephase shift
phase shift amount
amountδ (δα(α
δ) required
) requiredbybythe thepulse
pulsewidth
widthcontrol
control to to define
define D Dtx,,
information of the phase shift amount δ (αδ) δrequired by the pulse width control to define Dtxtx,
whereas the output signal from PI contains the information necessary to
whereas the output signal from PI2 contains the information necessary to define ftx (αT ). These signals
2 define ftx ( α T). These signals
whereas the output signal from PI2 contains the information necessary to define ftx (αT). These signals
are input into
are input into the
the pulse
pulse widthwidth and and frequency
frequency control
control (PWFC)
(PWFC) section
section and are converted
and are converted into into thethe
are input into the pulse width and frequency control (PWFC) section and are converted into the
switching signals G1
switching signals G1′ to0 to G4
G4′,, which
0 which contain the information
contain the information of of DDtx and
and fftx needed
needed for for the
the transformer
transformer
switching signals G1′ to G4′, which contain the information of Dtxtx and ftx tx needed for the transformer
voltage to control V
voltage to control Vout1 and Vout2 . Thereafter, a signal with a certain dead time provided to G1to
out1 and V out2 . Thereafter, a signal with a certain dead time provided to G1′ G4′
0 to G4is0
voltage to control Vout1 and Vout2. Thereafter, a signal with a certain dead time provided to G1′ to G4′ is
output
is output fromfrom the FPGA
the FPGA and
andit itisissubsequently
subsequentlyoutput outputtotothethegates
gatesofofS1S1to to S4
S4 via
via thethe isolated gate
isolated gate
output from the FPGA and it is subsequently output to the gates of S1 to S4 via the isolated gate
driver (G1 to
driver (G1 to G4).
G4).
driver (G1 to G4).
FPGA
FPGA
G1'
- G1' G1
Vout1** - PI1 G2' G1
Vout1 + PI1 Pulse width and G2' G2
Vfb1 + Pulse width and G2
Vfb1 frequency controller G3'
frequency controller G3' G3
(PWFC) G3
+ T (PWFC)
Vout2** + - PI2 T G4'
G4
Vout2 PI2 G4'
- G4
Vfb2
Vfb2
Figure
Figure 3.
3. Control
Control block
block diagram
diagram of
of proposed
proposed circuit.
circuit.
Figure 3. Control block diagram of proposed circuit.
Figure 4 shows the PWFC principle of switching the signal generation. The output signals from
Figure 4 shows the PWFC principle of switching the signal generation. The output signals from
the PWFC part are G1′, with a variable frequency and a constant duty cycle of 0.5; G3′, which is
the PWFC part are G1′, with a variable frequency and a constant duty cycle of 0.5; G3′, which is
phase-shifted from G1′ by δ; and G2′ and G4′, which are inverted versions of G1′ and G3′,
respectively. A sawtooth wave with an upper limit of the crest value set by αT is generated by a
Figure
counter 4 shows
inside the PWFC
the PWFC principle
to generate of signals.
these switching Thisthesawtooth
signal generation. The output
wave counter signals
decreases fromfrom
the
the PWFC part are G1 0 , with a variable frequency and a constant duty cycle of 0.5; G30 , which is
upper limit defined by αT and when the counter reaches zero it is set to the upper limit again. As
phase-shifted fromof 0 by δ; and G20 and G40 , which are inverted versions of G10 and G30 , respectively.
G1the
the decrease ratio counter corresponds to the clock period (TCLK) of the FPGA and remains
constant, the period of the upper
A sawtooth wave with an limitwave
sawtooth of the crest
Tsaw value setfsaw
(frequency by) α is generated
isTdefined by αTby a counter
. This inside the
is the period Ttx
(frequency ftx) that is necessary for the control. Furthermore, ftx is the switching frequency ofdefined
PWFC to generate these signals. This sawtooth wave counter decreases from the upper limit G1′ to
by αand
G4′ T and when the as
is expressed counter reaches zero it is set to the upper limit again. As the decrease ratio of
the counter corresponds to the clock period (TCLK ) of 1
the FPGA and remains constant, the period of
𝑓
the sawtooth wave Tsaw (frequency fsaw ) is definedby = α, . This is the period Ttx (frequency ftx ) that(4)is
𝑇 TCLK T
0 0
necessary for the control. Furthermore, ftx is the switching frequency of G1 to G4 and is expressed as
in which the possible range for αT is
1 1 1
≤ 𝑇 ≤ ,
ftx = . (5)(4)
fMAX TCLK αT TCLK
fmin TCLK
In thethe
in which above,
possible and ffor
fMAXrange min are the maximum and minimum values of the switching frequency,
αT is
respectively. By turning a signal on when the counter reaches the upper limit (αT) and off when the
1
counter reaches half of the upper limit (αT/2), it≤isαpossible 1to generate rectangular waveforms with
T ≤ . (5)
a frequency corresponding to αT and aMAXf T
dutyCLK f
cycle of 0.5. min TCLK
This signal is designated as the G1′ signal.
Figure4.
Figure Principleof
4.Principle ofField
FieldProgrammable
ProgrammableGate
GateArray
ArrayPWFC
PWFCfunction.
function.
In the G1′
While above, fMAX and G3′
is generated, fmin is
aregenerated
the maximum and minimum
by a comparison of αvalues of the switching frequency,
δ and the sawtooth wave counter.
respectively.
By turning G3′Byon turning
when athe
signal on when
sawtooth the counter
waves become reaches
smaller the upper
than limit
αδ and (αT ) and
turning offwhen
it off when the
the
same amount of time since G1′ was turned on has elapsed, G3′ becomes a signal that isa
counter reaches half of the upper limit (αT/2 ), it is possible to generate rectangular waveforms with
δ. αBecause
frequency corresponding 0 signal.
phase-shifted from G1′ byto T and a the
dutyrange
cycleof ofδ0.5. Thisthe
where signal is designated
control as the G1
holds is between 0° and 180°,
While G1 0 is generated, G30 is generated by a comparison of α and the sawtooth wave counter.
the possible range of αδ is δ
By turning G30 on when the sawtooth wavesbecome smaller than αδ and turning it off when the same
amount of time since G10 was turned on haselapsed,
𝑇
≤  ≤ G3𝑇 .0 becomes a signal that is phase-shifted from (6)
Theδ.switching
G10 by of δtowhere
Because the rangeG1′ theobtained
control holds is between ◦ and 180◦ , the possible range of
signals G4′ are by expressing the0 inverted signals of G1′ and G3′
αδG2′
as is and G4′, respectively. As illustrated in Figure 4, Vtxp,’ which is on the primary side voltage of
αT
the transformer generated by G1′ to G4′, Dtx 2and ≤α (=α1/f
Tδtx ≤ T .tx) change according to the input values (6)
of
The switching signals G10 to G40 are obtained by expressing the inverted signals of G10 and G30
as G20 and G40 , respectively. As illustrated in Figure 4, Vtxp ,’ which is on the primary side voltage of
the transformer generated by G10 to G40 , Dtx and Ttx (=1/ftx ) change according to the input values of
αT and αδ . However, although ftx is determined uniquely by αT , Dtx is not determined uniquely by αδ ,
because the sawtooth shape determined by αT is calculated by comparison with the counter.
3. Verification of Proposed Method Using Actual Circuit
3.1. Circuit Specifications

The specifications, circuit diagram and outer appearance of the actual circuit created to verify
the proposed control method are presented in Table 1 and Figure 5, respectively. The output power
of the Vout1 and Vout2 sides are expressed as Pout1 and Pout2 , respectively. The maximum value of the
total output power, Pout1 + Pout2 , was set to 1 kW and the maximum value of Pout2 was set to 500 W.
The input voltage Vin was set to 300 V, whereas the target values of the output voltages Vout1 and Vout2
were set to 48 V and 12 V, respectively. The minimum and maximum switching frequencies, fmin and
fMAX , were set to 50 kHz and 100 kHz, respectively and the FPGA used was a XC7K70T-1FBG484C
with a clock frequency (fCLK ) of 200 MHz (TCLK = 5 ns). When substituting the values of fmin , fMAX and
TCLK into Equation (5), αT can take values between 2000 and 4000. As αT is an integer, ftx and |Zout2 |
could take 2001 possible values under the verification control conditions. Proportional gains and time
constants of PI1 and PI2 were K1 = 2.5, K2 = 0.5, τ1 =3 µs, τ2 = 8 µs, respectively.
Table 1. Specifications of experimental circuit.
Parameter Value
Pout1 + Pout2 (MAX) 1 kW
Pout2 (MAX) 500 W
Vin 300 V
Vout1 48 V
Vout2 12 V
fswmin 50 kHz
fswMAX 100 kHz
FPGA XC7K70T-1FBG484C
fCLK (TCLK ) 200 MHz (5 ns)
K1 2.5
K2 0.5
τ1 3 µs
τ2 8 µs
Cin 330 µF
S1, S2, S3, S4 SCT3030AL (ROHM)
D11, D12, D13, D14, D21, D22, D23, D24 FFSH4065A (ON Semiconductor)
Transformer turn ratio N1:N2 = 20:5
Lsr 4.5 µH
Csr 560 nF
Lout1 7.3 µH
Lout2 7.0 µH
Cout1 44 µF
Cout2 188 µF
f0 100.3 kHz
fmin and fMAX, were set to 50 kHz and 100 kHz, respectively and the FPGA used was a
XC7K70T-1FBG484C with a clock frequency (fCLK) of 200 MHz (TCLK = 5 ns). When substituting the
values of fmin, fMAX and TCLK into Equation (5), αT can take values between 2000 and 4000. As αT is an
integer, ftx and |Zout2| could take 2001 possible values under the verification control conditions.
Proportional gains and time constants of PI1 and PI2 were K1 = 2.5, K2 = 0.5, τ1 =3 µs, τ2 = 8 µs,
World Electric Vehicle Journal 2020, 11, 72
respectively. 7 of 20
(a)
(b) (c)
Figure
Figure 5. Experimental
5. Experimental circuitdiagram
circuit diagramand
and setup:
setup: (a)
(a)Main
Maincircuit diagram,
circuit (b) (b)
diagram, Main circuit
Main with with
circuit
control circuit; (c) Main circuit without control circuit.
control circuit; (c) Main circuit without control circuit.
The input capacitor Cin was an aluminum electrolytic capacitor of 330 µF, the switching devices
of the primary side H-bridge circuit (S1 to S4) were SiC MOSFET (SCT3030AL, ROHM) and the
eight diodes of the secondary side diode bridge were SiC Schottky barrier diodes (FFSH4065A,
ON Semiconductor). Because this circuit was designed to verify the proposed control method,
the breakdown voltage and current capacity of these devices were substantially larger than necessary.
The turn ratio of the transformer was 20:5. The parameters of the elements of the series resonant filter,
Lsr and Csr , were 4.5 µH and 560 nF, respectively. The output smoothing inductors were Lout1 = 7.3 µH
and Lout2 = 7.0 µH, the output capacitor Cout1 was 88 µF with four ceramic capacitors of 22 µF in
parallel and Cout2 was 188 µF with four ceramic capacitors of 47 µF in parallel. The values of Cin ,
Cout1 and Cout2 are nominal values and the values of Lsr , Lout1 and Lout2 are calculated by using the
following equation:
di
dt
L=. (7)
V
In the above, di/dt is the rate of current change and V is the voltage across the inductor. Both di/dt
and V are obtained by the experimental measurement. The data range both parameters are constant is
used for the calculation.
The resonant frequency of the series resonant filter, f 0 , could be calculated as 100.3 kHz according
to the following equation:
1
f0 = √ . (8)
2π Lsr Csr
Each value of Table 1 was substituted into Equations (1) and (2) to calculate Zsr and Zsm , which were
then substituted into Equation (3). The result is presented in Figure 6. In this case, it was assumed that
Rout2 → ∞. As indicated in Figure 6, the resonant frequency of the Vout2 -side circuit was approximately
100 kHz. It can be observed that this value was the resonant frequency of the resonant filter and it
was not affected by the output smoothing LC filter. This is because the resonant frequency of the
World Electric
was far from Vehicle
100.3Journal
kHz. 2020, 11, x
Moreover, the Q value of the output smoothing LC filter was less than of
8 10%21
of the Q value of the series resonant filter (assuming that both filters had the same line resistance).
output
was far smoothing
from 100.3 LC kHz. filter (Lout2 , Cthe
Moreover, out2Q) was
valueapproximately
of the output4.4 kHz, which
smoothing was far
LC filter wasfrom
less100.3
than kHz.
10%
As the resonant frequency required for control was approximately 100 kHz, in the operating
Moreover,
of the Qofvalue
the Q value of theresonant
the series output smoothing LC filter
filter (assuming was
that lessfilters
both than 10%
hadof thethe Q value
same line of the series
resistance).
frequency range between 50 kHz and 100 kHz, the impedance of the Vout2-side circuit decreased
resonant
As filter (assuming
the resonant frequency thatrequired
both filters
for had the same
control line resistance).100
was approximately As kHz,
the resonant
in the frequency
operating
monotonically as the frequency of the transformer voltage (ftx) increased, which enabled Vout2 to be
required for
frequency control
range was approximately
between 50 kHz and 100 100 kHz,
kHz, the
in the operatingof
impedance frequency rangecircuit
the Vout2-side between 50 kHz
decreased
controlled by ftx, as mentioned previously. The reason for the monotonic decrease instead of an
and 100 kHz, the impedance
monotonically as the frequency of the of the V out2transformer voltage (ftx) increased, which enabled Vout2 of
-side circuit decreased monotonically as the frequency to the
be
increase is that the volume of Lout1 and Lout2 could be reduced with higher frequency when a large
transformerby
controlled voltage
ftx, as (fmentioned
tx ) increased, which enabled
previously. The Vreason
out2 to be
forcontrolled by ftx , as
the monotonic mentioned
decrease previously.
instead of an
current passed (Zout2 was small).
The reason
increase for the
is that themonotonic
volume ofdecrease
Lout1 and instead of an be
Lout2 could increase
reduced is that thehigher
with volume of Lout1 and
frequency whenLout2a could
large
be reduced
current passedwith(Zhigher
out2 wasfrequency
small).
30 when a large current passed (Zout2 was small).
25
30
(Ω) (Ω)
20
25
Impedance
15
20
Impedance
10
15
5
10
0
50 25 50 75 100 125 150
Frequency (kHz)
0
0 25 50 75 100 125 150
Figure 6. Zout2–f characteristics of Vout2-side circuit.
Frequency (kHz)
Figure
Figure 6.6.ZZout2 –f characteristics
out2–f characteristics of Vout2
of V -sidecircuit.
circuit.
As described above, the change rate of impedance by-side
out2 the frequency change and resonant
frequency can
As described be calculated using Equation (3) and Figure 6. The resonant frequency is thefrequency
upper or
As describedabove, above,thethe change
change raterate
of impedance
of impedanceby theby frequency change and
the frequency changeresonant
and resonant
lower
can belimit of the using
calculated operatingEquationfrequency.
(3) andFurthermore,
Figure theresonant
number frequency
of possibleis frequency values is
frequency can be calculated using Equation (3) and6.Figure
The 6. The resonant frequencythe upper or lower
is the upper or
defined by
limit oflimit Equation
the operating (5). If the
frequency. operating
Furthermore, frequency is too
the number high, the core
of possible losses
frequency and switching
values isvalues losses
defined
lower of the operating frequency. Furthermore, the number of possible frequency is
increase,
by Equation whereas
(5). Ififthe
it isoperating
too low, frequency
the volumeisoftoo thehigh,
magnetic
the core
core increases.
losses and Moreover,
switching if theincrease,
losses change
defined by Equation (5). If the operating frequency is too high, the core losses and switching losses
rate of the
whereas impedance
ifwhereas
it is tooiflow, relative to the frequency change increases.
is excessively high and anchange
FPGA ratewithout a
increase, it isthe
toovolume
low, theofvolume
the magnetic of the core Moreover,
magnetic core increases. if the
Moreover, of the
if the change
high clock
impedance frequency is
relative to relativeused,
the frequency the impedance values that it can take are not continuous and the
rate of the impedance to the change
frequency is excessively high and an
change is excessively FPGA
high andwithout
an FPGA a high
withoutclock a
control
frequency resolution decreases. However, if the change rate of the impedance relative to the frequency
high clockisfrequency
used, the impedance
is used, thevalues that it can
impedance takethat
values are not continuous
it can take areand not the control resolution
continuous and the
change
decreases.is excessively
However, ifsmall,
the change the control
rate ofifresolution
the increases but ifthethefrequency
operatingchange frequency range is
control resolution decreases. However, theimpedance
change rate relative
of the toimpedance relative to the is excessively
frequency
not expanded,
small, the the power
control resolution range that can be controlled by the V out2-side circuit becomes narrower.
change is excessively small, increases
the control butresolution
if the operating frequency
increases range
but if the is not expanded,
operating frequencythe power
range is
Therefore,
range that for
can the
be proposed
controlled control
by the V method-side to work
circuit as intended,
becomes it
narrower. is necessary
Therefore, to select
for the the most
proposed
not expanded, the power range that can be controlled by the Vout2-side circuit becomes narrower.
out2
appropriate
control method resonant
to work frequency,
as intended, operating frequency
it is necessary range,
to select thefrequency–impedance
most characteristics
Therefore, for the proposed control method to work as intended, it appropriate
is necessaryresonant
to selectfrequency,
the most
and FPGA.
operating frequency
appropriate resonantrange,frequency,frequency–impedance
operating frequency characteristics and FPGA.
range, frequency–impedance characteristics
and
3.2. FPGA.
3.2. Static
Static Characteristics
Characteristics
Figure
3.2. Static
Figure 77 presents
presents the
Characteristicstheoutput
outputvoltages
voltagesVVout1 and VVout2
out1 and out2 and output currents
and output currents IIout1
out1 and
and IIout2
out2, , with
with aa
total
total output
output ofof 1,037
1,037 W
W (P(Pout1 =461
out1 = 461W W and
and PPout2 = =
576 W),
576 W),from
from power-up
power-up until
until reaching
reaching a
a steady
steady state.
state.
Figure 7 presents the output voltages out2 Vout1 and Vout2 and output currents Iout1 and Iout2, with a
The measurement devices used in the actual verification are listed
The measurement devices used in the actual verification are listed in Table 2. in Table 2.
total output of 1,037 W (Pout1 = 461 W and Pout2 = 576 W), from power-up until reaching a steady state.
The measurement devices used60in the actual verification are listed in Table 2.
Vout1
(V) (V)
50
40 Vout2
VoltageVoltage
60
30 Vout1
50
20 Vout2
40
(A) Output
10
30
0
20
(A) Output
10
60
0 Iout1
50
CurrentCurrent
Iout2
40
60
30 Iout1
50
20 Iout2
Output Output
40
10
30
2000.0 0.2 0.4 0.6 0.8 1.0
10
Time (s)
0
0.0 0.2 0.4 0.6 0.8 1.0
Dual port
Figure 7. Dual port output
output
Time (s) waveforms.
waveforms.
Figure 7. Dual port output waveforms.

Measuring instruments.
Table 2. Measuring
Table instruments.
Instrument
Instrument Model
ModelNumber
Number
Oscilloscope HDO6104A-MS (TELEDYNE)
Oscilloscope HDO6104A-MS (TELEDYNE)
Voltage differential
Voltage differentialprobe
probe 700924
700924(YOKOGAWA)
(YOKOGAWA)
Current probe (<30
Current probe (<30 A) A) TCP312A
TCP312A(Tektronix)
(Tektronix)
Currentprobe
Current probe(>30
(>30 A)
A) TCP303
TCP303(Tektronix)
(Tektronix)
Deskew calibration
Deskew calibration source
source DCS025
DCS025(TELEDYNE)
(TELEDYNE)
The voltage and current of both outputs were adjusted to constant values and steady operation
The voltage and current of both outputs were adjusted to constant values and steady operation
was established within 0.5 s following power-up. The averages of the adjusted voltages Vout1 and
was established within 0.5 s following power-up. The averages of the adjusted voltages Vout1 and Vout2
Vout2 were 48.0 V and 12.0 V, respectively, as per the target values. The ripple voltages in the steady
were 48.0 V and 12.0 V, respectively, as per the target values. The ripple voltages in the steady state,
state, Vout1 and Vout2, were both ±0.6 V, whereas the ripple currents, Iout1 and Iout2, were ±0.2 A and ±0.8
Vout1 and Vout2 , were both ±0.6 V, whereas the ripple currents, Iout1 and Iout2 , were ±0.2 A and ±0.8 A,
A, respectively. The ripple current Iout2 was larger because the resolution of TCP303 used to measure
respectively. The ripple current Iout2 was larger because the resolution of TCP303 used to measure Iout2
Iout2 was lower than that of the TCP312A used to measure Iout1. These results indicate that the
was lower than that of the TCP312A used to measure Iout1 . These results indicate that the proposed
proposed control method can produce an output of 1 kW in an actual circuit.
control method can produce an output of 1 kW in an actual circuit.
The manner in which the voltage and current increased in this experiment was not a result of
The manner in which the voltage and current increased in this experiment was not a result of
the proposed control method but rather, because of the voltage increase slew rate of the DC power
the proposed control method but rather, because of the voltage increase slew rate of the DC power
supply ZX-1600H used in the verification. Furthermore, the control parameters of the proposed
supply ZX-1600H used in the verification. Furthermore, the control parameters of the proposed
method (proportional gain of the time constant of the PI calculation part) were only optimized for
method (proportional gain of the time constant of the PI calculation part) were only optimized for
the disturbance response, which is detailed later. This is because, if this circuit is used as designed,
the disturbance response, which is detailed later. This is because, if this circuit is used as designed,
load changes will occur more frequently than power increases. The control of a circuit with a power
load changes will occur more frequently than power increases. The control of a circuit with a power
supply voltage applied from the start is a topic for future research.
supply voltage applied from the start is a topic for future research.
3.3.
3.3. Operation
Operation Points
Points
The
The circuit
circuit operation
operation points
points used
used in
in the
the simulation
simulation andand verification
verificationare are illustrated
illustratedin inFigure
Figure8.8.
Six
Six operation points of 154 W, 285 W, 456 W, 568 W, 740 W and 853 W were prepared on the Pthe
operation points of 154 W, 285 W, 456 W, 568 W, 740 W and 853 W were prepared on Pout1
out1 side
side using inductive resistance, whereas four operation points of 142 W, 268
using inductive resistance, whereas four operation points of 142 W, 268 W, 394 W and 499 W were W, 394 W and 499 W
were prepared
prepared on the P on the Pout2 side using non-inductive resistance. The tests and analysis were
out2 side using non-inductive resistance. The tests and analysis were conducted at a
conducted
total of 18 locations wherelocations
at a total of 18 where power
the total output the total output
Ptotal (Pout1power
+ Pout2P)total
was (Pout1
less+ than
Pout2)1000
was W,lesswhich
than were
1000
W, which were defined as operation points. In the Sections 3.4–3.6, 4.2, and
defined as operation points. In the Section 3.4, Section 3.5, Section 3.6, Section 4.2, and Section 4.3,4.3, the numbers
indicated
the numbersin Figure 8 areinused
indicated to 8denote
Figure the to
are used operation
denote the points.
operation points.
600
#16 #17 #18
500
#12 #13 #14 #15
400
Pout2 (W)
300 #7 #8 #9 #10 #11
200
#1 #2 #3 #4 #5 #6
100
0
0 100 200 300 400 500 600 700 800 900 1000
Pout1 (W)
Figure 8.
Figure Measured operation
8. Measured operation points.
points.
3.4. Analysis
3.4. Analysis of
of Steady
Steady Operation
Operation
In the
In the simulation,
simulation, thethe waveform
waveform of of each
each part
part of
of the
the circuit
circuit in
in steady
steady operation
operation waswas calculated
calculated
and an analysis was performed on each operation point. PSIM (v. 12.04) was
and an analysis was performed on each operation point. PSIM (v. 12.04) was used for the used for the simulation.
Table 3 lists Table
simulation. the specifications of simulation circuit.
3 lists the specifications The values
of simulation displayed
circuit. in Table
The values 3 were same
displayed as the
in Table 3
experimental
were same asspecifications listedspecifications
the experimental in Table 1 except for the
listed switching
in Table devices.
1 except All of
for the the switching
switching devices
devices. All
World Electric Vehicle
World Electric Vehicle Journal
Journal 2020,
2020, 11,
11, 72
x 10
10of
of 21
20
of the switching devices and the transformer were ideal and there were no parasitic resistance,
and the transformer
inductance were ideal
and capacitance andsimulation
in the there werecircuit.
no parasitic resistance, inductance and capacitance in
the simulation circuit.
Table 3. Specifications of simulation circuit.
Table 3. Specifications of simulation circuit.
Parameter Value
ParameterVin Value
300 V
VinVout1 48
300VV
Vout1Vout2 1248VV
Vout2fswmin 50 12
kHzV
fswmin
fswMAX 50
100 kHzkHz
fswMAX
fCLK (TCLK) 200 MHz100 kHz(5 ns)
fCLK (TCLKK1 ) 200 MHz2.5 (5 ns)
K1 K2 2.5
0.5
K 2 τ1 0.5
3 µs
τ1 τ2 83µsµs
τ2 Cin 8
330 µFµs
Cin 330 µF
S1, S2, S3, S4 Ideal devices
S1, S2, S3, S4 Ideal devices
D11, D12, D13, D14, D21, D22, D23, D24 Ideal devices
D11, D12, D13, D14, D21, D22, D23, D24 Ideal devices
Lsr Lsr 4.5
4.5µHµH
Csr C sr 560
560nFnF
Lout1Lout1 7.3
7.3µHµH
Lout2Lout2 7.0
7.0µHµH
Cout1Cout1 4444µFµF
Cout2Cout2 188µF
188 µF
These
These analysis
analysis results refer to
results refer to the
the operation
operation mode
mode of of the
the secondary
secondary side side circuit
circuitwhen
whenPPout2 out2 was
was
maintained constant and P
maintained constant and Pout1 was changed (operation points #01, #02, #03, #04, #05 and #06) and
out1 was changed (operation points #01, #02, #03, #04, #05 and #06) and
when
when P Pout1
out1 was
wasmaintained
maintainedconstant constantand andPPout2 was
out2 waschanged
changed (operation
(operation points
points #01,
#01,#07,
#07,#12
#12 and
and #16).
#16).
Figure
Figure 99 indicates
indicates the the voltage
voltage and and current
current direction
direction of of each
each part
part used
used to define the
to define the operation
operation
modes,
modes, whereas Table 4 lists the operation modes of the secondary side circuit in the half cycle
whereas Table 4 lists the operation modes of the secondary side circuit in the half cycle inin aa
steady statebased
steady state basedonon thethe voltage
voltage andand current
current directions
directions of Figure
of Figure 9. As in
9. As shown shown
Table in Table
4, the 4, the
operation
operation
modes were defined by the secondary side voltage and current of the transformer (Vtxs and I(V
modes were defined by the secondary side voltage and current of the transformer txs ),
txs
and Itxs), thefrom

the current current from the transformer
the transformer to the diodetobridge
the diode
on the bridge on the
Vout1 -side Vout1-side
circuit (IrecA circuit (I),
and IrecB recA
theand IrecB),
current
the current of L (I ), the return current of the V -side circuit (I ), the
of Lout1 (ILout1 ), the return current of the Vout1 -side circuit (Iret1 ), the currents of the series resonant
out1 Lout1 out1 ret1 currents of the series
resonant
filters (IsrAfilters
and I(I srA and IsrB), the current of Lout2 (ILout2), the return current of the Vout2-side circuit (Iret2)
srB ), the current of Lout2 (ILout2 ), the return current of the Vout2 -side circuit (Iret2 ) and the
and the circulating
circulating current (Icir current (Icir) that
) that flowed flowedthe
between between
GND ofthe both GND of both
outputs. outputs.
In Table 4, “+”Inrepresents
Table 4, “+” the
represents
positive direction, “−” denotes the negative direction and “0” is the condition of no voltage appliedno
the positive direction, “−” denotes the negative direction and “0” is the condition of or
voltage
no current applied
flowing.or no current flowing.
Figure 9.
Figure Definition of
9. Definition of voltage
voltage and
and current
current directions.
directions.
Table 4. Definition of operation modes.
Voltage/Current 1 2 3 4 5 6 7 8 9 10 11
Vtxs + + + + + 0 0 0 0 0 0
Itxs + + + + + + + + − − −
IrecA + + + + + + + + + + +
IrecB − − − − − − − − − − 0
ILout1 + + + + + + + + + + +
Iret1 + + + + + + + + + + 0
IsrA + + + + − + − − − − −
IsrB − − + + + + + + + + +
ILout2 + + + + + + + + + + +
Iret2 + + + 0 + + + + + + +
Icir − + + + + + + − + − −
There were a total of 11 operation modes for the operation points of the analysis. Table 5 lists the
possible operation modes for each operation point as indicated in Table 5, for each operation point,
several modes were used and others were not, which created a large variety of current paths. As an
example, Figure 10 depicts the simulation waveform of Vtxs and each current at operation points #04
and #12. The both waveforms of #04 and #12 are divided into 8 modes based on the definition of
Table 4, respectively. The operation modes 3, 6 and 9 were not used at operation point #04 and the
modes 4, 5 and 8 were not used at #12 as shown in Table 5. Therefore, it is difficult to explain the
circuit operation by the 11 operation modes. However, by focusing on the charging condition of Lout1 ,
the 11 operation modes could be categorized into three groups (A, B and C). The changes in Dtx and ftx
caused by the changes in the operation points can be explained by these three operation modes.
Table 5. Operation modes and measurement points.
Operation Mode
Operation Point
1 2 3 4 5 6 7 8 9 10 11
#01 # # # # #
#02 # # # # # # #
#03 # # # # # #
#04 # # # # # # # #
#05 # # # # # # # #
#06 # # # # # # # #
#07 # # # # # # #
#12 # # # # # # # #
#16 # # # # # # #
• Group A: Lout1 is charged (modes 1 to 5)
In this mode, Vtxs is positive. As an example, Figure 11a presents the current path in mode 2.
The transformer voltage works as the voltage source and Lout1 is charged by the following path:
Transformer → D11 → Zsm1 → D14 → Transformer.
• Group B: Lout1 discharges (modes 6 to 10)
In this mode, Vtxs is zero and Iret1 is flowing. As an example, the current path in mode 7 is
illustrated in Figure 11b. When Lout1 is discharged, its discharge current returns along the following
path: Zsm1 → D14 → Transformer → D11 →Zsm1 .
#04 and the modes 4, 5 and 8 were not used at #12 as shown in Table 5. Therefore, it is difficult to
explain the circuit operation by the 11 operation modes. However, by focusing on the charging
condition of Lout1, the 11 operation modes could be categorized into three groups (A, B and C). The
changes in Dtx and ftx caused by 5.
Table the changesmodes
Operation in theand
operation pointspoints.
measurement can be explained by these three
operation
World Electricmodes.
Vehicle Journal 2020, 11, 72 12 of 20
Operation Mode
Operation Point
1 2 3 4 5 6 7 8 9 10 11
operation mode
#01 ○ ○ 1 2
○ 3 6 7operation
9 10
mode
○ ○11
1 2 4 5 7 8 10 11
80 #02 ○ ○ ○ ○ ○ ○ ○
Vtxs Vtxs
Vtxp (V), Itxs (A)
40 #03 ○ ○ Itxs ○ ○ ○ ○ Itxs
0 #04 ○ ○ ○ ○ ○ ○ ○ ○
-40 #05 ○ ○ ○ ○ ○ ○ ○ ○
-80
40 #06 ○ ○ IrecA ○ ○ ○ ○ ○ ○ IrecA
20 #07 ○ ○IrecB ○ ○ ○ ○ ○ IrecB
IrecA, IrecB (A)
0 #12 ○ ○ ○ ○ ○ ○ ○ ○
-20
#16 ○ ○ ○ ○ ○ ○ ○
-40
40
ILout1 ILout1
• 30
ILout1, Iret1 (A)
Group A: Lout1 is charged (modes 1 to 5) Iret1 Iret1

20
10
In this mode, Vtxs is positive. As an example, Figure 11a presents the current path in mode 2.
0
The transformer
50 voltage works as the voltage Isource and Lout1 is charged by the following path:
srA
Transformer25→ D11 → Zsm1 → D14 → Transformer. I srB

IsrA, IsrB (A)
0 IsrA
• Group B:
-25
Lout1 discharges (modes 6 to 10) IsrB
-50
In this mode,
50 Vtxs is zero and Iret1 is flowing. As an example, the current path in mode 7 is
40 I Lout2
ILout2, Iret2 (A)
illustrated in30Figure 11b. When Lout1 is discharged,

I its discharge current returns along
ret2
I
the following
Lout2
path: Zsm1 → 10D14 → Transformer → D11 →Zsm1.
20 I ret2
0
• Group C: The charge/discharge of Lout1 depends on the resonant filter voltage (mode 10)
20
10
Figure 11c depicts the current path of mode 10. In this mode, Iret1 and IrecB are zero. The return
Icir (A)
0
current from-10Zsm1 becomes a circulating current (Icir) and moves around the return current of the Vout2
side (Iret2). This
-20 circulating current Icir flows because the GND of the Vout1-side and Vout2-side circuits
0 2 4 6 8 0 1 2 3 4 5 6
are common and the return path of the Vout2-side circuit contains ZsrA Time
Time (μs) or (μs)
ZsrB. The circulating current
of this mode flows according(a) to the state of ZsrA and ZsrB. The current path (b) involved in Lout1 is Zsm1 →
D22 →ZsrA → D11 →Zsm1. When the both-end voltage of ZsrA (VsrA) exhibits the relationship of VsrA >
Figure
Figure10. Waveforms
Waveformsofoffor half
halfperiod:
period:(a) measurement
measurementpoints
points#04;
#04;(b)
(b)measurement
measurementpoints
points#12.
Vout1, Lout1 is10.
charged by ZsrAfor
and when VsrA(a)
<V out1, Lout1 discharges.
#12.
(a) (b) (c)

Figure 11.
11. Current
Current pathpathofofexperimental
experimentalcircuit
circuit
in in each
each operation
operation mode
mode (the(the red indicates
red line line indicates the
the path
path related
related to ):Lout1):
to Lout1 (a) Mode
(a) Mode 2; (b) Mode
2; (b) Mode 7; (c) Mode
7; (c) Mode 10. 10.
• Group
Figure C: 12 The charge/discharge
presents the occupancy of Ltime
out1 depends on the resonant
and corresponding filter voltage
frequencies (mode
of these three10)
modes at
each Figure
operation 11c point.
depictsWhen Pout2 was
the current constant
path of mode and
10.PIn
out1 changed (Figure 12a), the time occupied by
this mode, Iret1 and IrecB are zero. The return
mode A increased (D tx increased) and ftx decreased (Ttx increased) as Pout1 increased. The increase in
current from Zsm1 becomes a circulating current (Icir ) and moves around the return current of the Vout2
D tx was caused by the increase in Pout1 and the decrease in ftx occurred to prevent an increase in the
side (Iret2 ). This circulating current Icir flows because the GND of the Vout1 -side and Vout2 -side circuits
power supply andtothe
thereturn
Vout2-side circuit
the Vcaused by the increase in Dtx. However, when Pout1 was
are common path of out2 -side circuit contains ZsrA or ZsrB . The circulating current
constant and Pout2 changed (Figure 12b), Pout2 increased as Ttx decreased (ftx increased) but few
of this mode flows according to the state of ZsrA and ZsrB . The current path involved in Lout1 is Zsm1
changes occurred in the percentages of the three operation modes (changes in Dtx), regardless of the
→ D22 →ZsrA → D11 →Zsm1 . When the both-end voltage of ZsrA (VsrA ) exhibits the relationship of
changes in Pout2. This indicates that the impedance change of the Vout2-side circuit caused by the
VsrA > Vout1 , Lout1 is charged by ZsrA and when VsrA < Vout1 , Lout1 discharges.
frequency change played a dominant role in the changes in Pout2.
Figure 12 presents the occupancy time and corresponding frequencies of these three modes at each
operation point. When Pout2 was constant and Pout1 changed (Figure 12a), the time occupied by mode
A increased (Dtx increased) and ftx decreased (Ttx increased) as Pout1 increased. The increase in Dtx was
caused by the increase in Pout1 and the decrease in ftx occurred to prevent an increase in the power
supply to the Vout2 -side circuit caused by the increase in Dtx . However, when Pout1 was constant and
Pout2 changed (Figure 12b), Pout2 increased as Ttx decreased (ftx increased) but few changes occurred
in the percentages of the three operation modes (changes in Dtx ), regardless of the changes in Pout2 .
This indicates that the impedance change of the Vout2 -side circuit caused by the frequency change
played a dominant role in the changes in Pout2 .
group A group B group C group A group B group C
Frequency (kHz) Frequency (kHz)

Pout1 500 250 167 125 100 83 71 63 Pout2 500 250 167 125 100 83 71 63
#01 (154W) #01 (140W)
#02 (282W)
load condition
load condition
#07 (283W)
#03 (463W)
#04 (570W) #12 (427W)
#05 (747W)
#16 (581W)
#06 (854W)
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
Time (μs) Time (μs)
(a) (b)
Figure 12. Occupied time and frequency of three operation modes: (a) Pout1 out1changes
changesfrom
from 154
154 W
W to
853 W (Pout2
out2 ==142
142W);
W);(b)
(b)PPout2 changes
out2 from
changes 140
from W
140 to
W 581
to W
581 (P
W (P
out2 =
out2 =
154 W).
154 W).
3.5. Comparative
3.5. Comparative Evaluation
Evaluation of
of Simulation
Simulation and
and Measured
Measured Results
Results
Figure 13
Figure 13 depicts
depicts the the measured
measured and and simulation
simulation waveforms
waveforms of of each
each part
part atat operation
operation points
points #01,
#01,
#06 and
#06 and #16
#16 inin steady
steady operation.
operation. From From the the top,
top, Figure
Figure 13 13 presents
presents thethe voltages
voltages of of the
the primary
primary and and
secondary sides of the transformer
secondary sides of the transformer (Vtxp (V and V
txpand Vtxstxs ), the currents of the primary and
), the currents of the primary and secondary sides secondary sides
of
of the
the transformer
transformer (Itxp(Iand Itxs), Ithe
txp and txs ), both-end
the both-end voltages
voltages of D11of and
D11 D12and (V D12 (Vd11Vd12
d11 and
and Vd12L),
), the the Lout1
out1 current
current
and and current
output output current
(ILout1 and(ILout1 theIseries
Iout1),and out1 ), the series resonant
resonant filter currents
filter currents (IsrA and (I IsrB IsrB ), the
andseries
), the
srA series
resonant
resonant filter voltages
filter voltages (VsrA and VsrA (V and V
srB), the both-end
srB ), the both-end voltages of D21 and
voltages of D21 and D22 (Vd21 andd21 D22 (V and V
Vd22), thed22 ), the Lout2
Lout2 current
current
and and output
output currentcurrent (ILout2
(ILout2 and Iout2and
) and Iout2the
) and the circulating
circulating current current (Icir ). According
(Icir). According to Figure
to Figure 13,
13, the
the measured and simulation waveforms of #01, #06 and #16 were
measured and simulation waveforms of #01, #06 and #16 were all very close, which confirms that all very close, which confirms that
the verification
the verification circuit
circuit operated
operated as as designed.
designed. The The errors
errors inin D
Dtx and ftx,, the
tx and ftx
the voltage
voltage surge
surge that
that only
only
appeared in
appeared in the
the measured waveforms and
measured waveforms and thethe ringing
ringing resulting
resulting from
from it it were
were all all caused
caused by by wiring
wiring
resistance, parasitic inductance and floating capacitance, which
resistance, parasitic inductance and floating capacitance, which were not included in the were not included in the simulation.
Figures 14 and 15 present the relationships between Dtx and Pout1 and ftx and Pout2 , respectively,
simulation.
in steady operation for the measurement and simulation. In addition, the difference between the
experimental results and the simulation results for Figures 14 and 15 are depicted in Figure 16.
Figures 14–16 indicate the experimental tests are operated by larger Dtx and lower ftx than the
simulation tests under all load conditions. The reason for the larger Dtx is that Dtx compensates for
Vout1 decreased by the conduction losses of parasitic resistance in the actual circuit and the reason for
the lower ftx is that ftx controls increasing Vout2 with increasing Dtx . Although these errors appeared,
it can be observed that the values of Dtx and ftx at all operation points in steady operation were
close to the simulation results. Therefore, the verification circuit also operated as per the simulation
analysis at other operation points that are not shown in the waveforms of Figure 13. This is a further
demonstration of the efficacy of the proposed control method.
Itxp Itxs txp txs
60 Itxp Itxs Itxp Itxs txp txs
60 Itxp Itxs
Itxp, Itxs (A)

ILout2, Iout2 (A) Vd21, Vd22 (V) Vsr1, Vsr2 (V) Isr1, Isr2 (A) ILout1, Iout1 (A) Vd11, Vd12 (V) Itxp, Itxs (A)
30
30
0
0
-30
-30
-60
-60
Vd11 Vd12 Vd11 Vd12 200 Vd11 Vd12 Vd11 Vd12 Vd11 Vd12
200
ILout1, Iout1 (A) Vd11, Vd12 (V)

Vd11 Vd12 160
160
120
120
80
80
40
40
0
0
ILout1 Iout1 ILout1 Iout1 ILout1 I
World Electric
24 Vehicle
I Journal
I 2020, 11, 72 Lout1 out1
24 14 of 20
out1
World Electric
18 Vehicle Journal 2020, 11, x 18 14 of 21
12
12
ILout1 Iout1 6
6 ILout1 Iout1
0
0 IsrA IsrB IsrA IsrB
IsrA IsrB 60 IsrA IsrB IsrA IsrB
sr2 (A)
60 IsrA IsrB
300
30
300 30
Vtxp, IVsr1txs, I(V)

Vtxp, Vtxs (V)
0
150
150 0
-30
-30 0
0 Vtxp Vtxp -60 Vtxp Vtxp Vtxp
-60 Vtxp -150
-150 VsrA VtxsVsrB VsrA VVtxs
240 VsrA VsrBVtxs VsrA VsrB Vtxs VsrA VsrB Vtxs
240
, Vsr2 (V)
VsrA Vtxs VsrB
srB -300
160
-300 160 Itxp Itxs Itxp Itxs
Itxp Itxs 60
80 Itxp Itxs Itxp Itxs
60 80 Itxp Itxs
Itxp, IVtxssr1(A)
ILout2, Iout2 (A) Vd21, Vd22 (V) Vsr1, Vsr2 (V) Isr1, Isr2 (A) ILout1, Iout1 (A) Vd11, Vd12 (V) Itxp, Itxs (A)
30
0
30 0
0 -800
-80 -30
-30 Vd21 Vd22 240
Vd21 Vd22
, Vd22 (V)
240 -60 Vd21 Vd22 Vd21 Vd22 Vd21 Vd22
-60 Vd21 Vd22
180
180 Vd11 Vd12 Vd11 Vd12 200 Vd11 Vd12 Vd11 Vd12 Vd11 Vd12
200 120
Vd21(V)
120 Vd11 Vd12 160
160 60
60 120
d11, Vd12
120 0
0 80
80 48 ILout2 Iout2
, Iout2V(A)
48 ILout2 Iout2 40 ILout2 Iout2
40 ILout2 Iout2
360
0 36 ILout2 Iout2
24
I ILout2 IIout2
(A)
24 Lout1 out1 24 ILout1 Iout1 ILout1 Iout1
24 ILout1 Iout1
ILout2
12
12 18
ILout1, Iout1
18 0
0 12
12 106
10 ILout1 Iout1
6 ILout1 Iout1
Isr1, Isr2 (A)Icir (A)

00
Icir (A)
0 0 IsrA IsrB IsrA IsrB

IsrA IsrB 60
-10 IsrA IsrB IsrA IsrB
60 -10 IsrA IsrB
30
-20
30 -20 0 5 10 15 20 0 5 10 15 20 0 5 10 15 20 0 5 10 15 20 0 5 10 15 20
0 0 5 10 15 20
-30
-30
-60
-60
Time (μs) Time
VsrA (μs)
VsrB Time
VsrA
(μs) VsrB
240 Time (μs)
VsrA VsrB Time (μs)
VsrA VsrB Time (μs)VsrA VsrB
240
ILout2, Iout2 (A) Vd21, Vd22 (V) Vsr1, Vsr2 (V)

VsrA
#01 VsrB #01 #16 160 #01 #01 #01
160
80
80
0
(a) 0 (b)
-80
-80
240 Vd21 Vd22
240 Vd21 Figure
V 13. Waveforms
d22
V V of proposed circuit: (a) Experimental
d21
180
V results;
d22 V (b) Simulation
V Vresults. d21 d22 d21 d22 Vd21 Vd22
180
120
120
60
60
0
Figures 14 and 15 present the relationships between Dtx and Pout1 and ftx and Pout2, respectively, 0
I I I I I I 48
48 Lout2 out2 Lout2 out2 Lout2 out2
in steady
36
I operation
I for the measurement and simulation. In addition, the difference between the Lout2 out2
36
I 24 Lout2 Iout2
experimental results and the simulationI results
24 I
for Figures 14 and 15 are depicted in Figure 16. Lout2 out2
12
12
0
Figures 14–16 indicate the experimental tests are operated by larger Dtx and lower ftx than the
0
10
10
simulation tests under all load conditions. The reason 0for the larger Dtx is that Dtx compensates for
Icir (A)
Icir (A)
0
-10
Vout1 decreased by the conduction losses of parasitic resistance
-10
-20
in the actual circuit and the reason
-20 0 5 10 15 20 0 5 10 15 20 0 5 10 15 20 0 5 10 15 20 0 5 10 15 20
for0 the
5 10lower
15 20 ftx is that ftx controls increasing Vout2 with increasing Dtx. Although these errors
appeared,
Time (μs) it can be observed
Time (μs) that the values
Time (μs)of Dtx and ftxTime
at all
(μs)operation pointsTime (μs)in steady operation
Time (μs)
were#01close to the simulation #01 #16
results. Therefore, #01
the verification circuit also#01operated as per#01the
simulation analysis (a)at other operation points that are not shown in the waveforms (b) of Figure 13. This
is a further demonstration of the efficacy of the proposed control method.
Figure13.
Figure 13.Waveforms
Waveformsof of proposed
proposed circuit:
circuit: (a)
(a) Experimental
Experimentalresults;
results;(b)
(b)Simulation
Simulationresults.
results.
Figures 14 and 15 present the relationships between Dtx and Pout1 and ftx and Pout2, respectively,
65
Duty of transformer voltage (%)
65
in steady operation for the measurement#6 and simulation. In addition, the difference #6 between the
60 60 #5
#5
experimental 55
results and the simulation results for Figures 55 14 and 15 are depicted in Figure 16.
#4 #4
Figures 14–16 50 indicate the#3 experimental
#10 #11 tests are operated50 by larger#3 Dtx #10and #11
lower ftx than the
#9 45for the larger Dtx#9is #15
simulation45tests under #2 all load conditions.
#15 The reason that D tx compensates for
#2 #14
40 #8 conduction#14 Pout2 of
≈ 140W 40 Pout2 ≈ 140W
Vout1 decreased #1by the losses parasitic resistance
#1 in
#8 the actual
#18 circuit and the reason
Pout2 ≈ 283W
#18 P
# out2 ≈ 283W 35 #7 #
35 #7 #13
for the lower ftx is that #13 ftx controls increasing Vout2 with
Pout2 ≈ 427W 30 #12
increasing
#17
Dtx. Although these errors
Pout2 ≈ 427W
30 #12 #17
appeared, it can #16 be observed that the values Pout2 ≈ 581W at all operation points inPout2
of Dtx and25ftx#16 ≈ 581W
steady operation
25 0 100 200 300 400 500 600 700 800 900 1000
0 100 200 300 400 500 600 700 800 900 1000
were close to the simulation Pout1
World Electric Vehicle Journal 2020,
results.
11,(W)
x
Therefore, the verification circuit
Pout1
also
(W) operated as per the
15 of 21
simulation analysis at other operation points that are not shown in the waveforms of Figure 13. This
is a further
Figuredemonstration
14. Results of Dtxof(a)the
for efficacy
each of thepoint:
measurement proposed control method.
(a) Experimental (b) (b) Simulation results.
results;
Figure 14. Results of Dtx for each measurement point: (a) Experimental results; (b) Simulation results.
95
95 65 #12 #16
(kHz) (%)
65
#12
#13 #6 #16 9060 #7 #13 #6
#17
60 90 #7 #14 #5 #18
Frequency voltage
#14 #5 #8
#8 #17#18 8555 #9 #15
Frequency (kHz)
55 85 #9 #4 #15 #4 Pout1 ≈ 154W

#11
Pout1 ≈ 154W 8050
50 #3 #10 #3 #10 Pout1 #11
Duty of transformer
80 ≈ 282W
#9 Pout1 ≈ 282W 7545
#1 #10
45 #1 #10 #15 #2 #11 #9 #15 Pout1 ≈ 463W
#2#2
75 Pout1 ≈ 463W
#11 #3 #2 #14 P#out1 ≈Pout2
570W
40 #3#8 #14 Pout2 7040 ≈ 140W
70
#1 P#out1≈≈140W
570W #1
#4 #8 #18
#4 #18 Pout1#≈Pout2
747W ≈ 283W
35 #7 #Pout2
Pout1≈≈283W
747W 6535 #5
#7 #13
65 #5 #13 #6 Pout1 ≈Pout2
854W ≈ 427W
#6 Pout2
Pout1≈≈427W #12 #17
30 #12 #17 854W 6030
60 P500 #16
100 200 300 400 500 Pout2 600≈ 581W
#16 100 200 300 400 out2 ≈ 581W
600 25
25
Pout2 600
(W) 700 800 900 1000 0 100 200 300 Pout2 (W)
400 500 600 700 800 900 1000
0 100 200 300 400 500
Pout1 (W) Pout1 (W)
(a) (b)
(a) (b)
Figure 15. Results of ftx for each measurement point: (a) Experimental results; (b) Simulation results.
Figure 15. Results of ftx for each measurement point: (a) Experimental results; (b) Simulation results.
5 -5
r voltage (%)
4 -4
(kHz)
3 -3
60 100 200 300 400 500 600
100 200 300 400 500 600 Pout2 (W)
Pout2 (W)
(a) (b)
World Figure 15. Results

Electric Vehicle Journalof2020,
ftx for
11,each
72 measurement point: (a) Experimental results; (b) Simulation results.15 of 20
5 -5

4 -4
Frequency (kHz)
3 -3
2 -2
1 -1
0 0
#1 #2 #3 #4 #5 #6 #7 #8 #9#10#11 #12#13#14#15 #16#17#18 #1 #2 #3 #4 #5 #6 #7 #8 #9#10#11 #12#13#14#15 #16#17#18
Measurement points Measurement points
(a) (b)
Figure
Figure 16.
16. Results
Results of subtract thethesimulation
simulationresults
resultsfrom
fromthe
the experimental
experimental results
results forfor each
each measurement
measurement point:
point: (a) results of D(a)
tx ;results
(b) results tx; f(b)
of Dof tx . results of ftx.
3.6. Dynamic
3.6. DynamicCharacteristics
Characteristics
Figures 17
Figures 17 and
and1818present
present thetheoutput
outputvoltage, measured
voltage, current
measured waveform
current and simulation
waveform results
and simulation
when P was maintained constant at
out2 Pout2 was maintained constant at 140 W and
results when 140 W and P was switched between 285
out1Pout1 was switched between 285 W andW and 568568W
(#02
W andand
(#02 #04 #04
werewere switched) and when
switched) Pout1 was
and when Pout1maintained constant
was maintained at 286 Watand
constant 286Pout2
W andwas Pswitched
out2 was
between 270 W and 393 W (#08 and #13 were switched), respectively.
switched between 270 W and 393 W (#08 and #13 were switched), respectively. Under any Under any condition of condition
Figures 17
and
of 18, within
Figures 17 and8 ms18,after the8output
within ms after power was switched,
the output power wasbothswitched,
of the output
both voltages were voltages
of the output adjusted
to their
were respective
adjusted values
to their prior to values
respective the switch.
priorIntothe
themeasured
switch. Inwaveforms
the measured of Figure 17, an overshoot
waveforms of Figure
with a peak value of around 2 V appeared in both output
17, an overshoot with a peak value of around 2 V appeared in both output voltages V out1 and V out2 and
voltages anand
Vout1 error of
Vout2
approximately
and 0.5 V occurred 0.5
an error of approximately in the steady value
V occurred Vout1 value
in theofsteady in the ofmeasured waveform
Vout1 in the measured ofwaveform
Figure 18.
However,
of Figure
World overall,
Electric 18. the
However,
Vehicle measured
Journal 2020,overall,
11, x and
the measured and simulation waveforms were verythat
simulation waveforms were very close, confirming ofthe
close,
16 21
dynamic characteristics of the proposed control method were valid.
confirming that the dynamic characteristics of the proposed control method were valid.
(a) (b)
Figure 17. Results
Resultsofof Pout1
Pout1 dynamic response
dynamic test test
response when Pout2 =Pout2
when = 140
140 W: (a) Experimental results; (b)
W: (a) Experimental results;
(b) Simulation
Simulation results.
results.
(a) (b)
Figure 17. Results of Pout1 dynamic response test when Pout2 = 140 W: (a) Experimental results; (b)
Simulation
World Electric results.
Vehicle Journal 2020, 11, 72 16 of 20
(a) (b)
Figure
Figure 18.18.Results
ResultsofofPPout2
out2 dynamic
dynamicresponse
responsetest
testwhen
whenPout1 = W:
= 286
Pout1 286(a)
W:Experimental results;
(a) Experimental (b)
results;
(b)Simulation
Simulationresults.
results.
4. Evaluation of Efficiency and Losses
4. Evaluation of Efficiency and Losses
4.1. Measurement Method
4.1. Measurement Method
To evaluate the efficiency and losses of the verification circuit, the input/output power (Pin, Pout1
and To evaluate
Pout2 the efficiency
) was measured withand a losses
WT1800 of the verification
power circuit,
analyzer. the input/output
Furthermore, powerand
the voltage Pout1 and
(Pin ,current of
Pthe ) was measured
out2transformer withside
primary a WT1800 power
(Vtxp, Itxp ), the analyzer.
voltage andFurthermore,
current of thethe transformer
voltage and secondary
current of side the
transformer primary
(Vtxs, Itxs) and the voltage txp , Itxp
side (Vand ), the voltage
current of the and current
resonant of the
filter of transformer
each series secondary
(VsrA, VsrB, side
IsrA, (V Itxs )
) ,were
IsrBtxs
and the voltage
measured usingand
thecurrent of the resonant
instruments listed in filter
Tableof2.each
Theseries
points(Vof , VsrB , IsrA , IsrB )are
srAmeasurement were measured
illustrated in
using
Figurethe 19.instruments listed in Table 2. The points of measurement are illustrated in Figure 19.
Figure 19.Points
Figure19. Pointsand
andloss
losspositions
positionsof
ofexperimental
experimentaltest.
test.
The efficiency η of the measured power was calculated according to the following equation:
Pout1 + Pout2
= . (9)
Pin
For the measured voltage and current, the power of the primary side of the transformer (Ptxp),
power of the secondary side of the transformer (Ptxs) and power of the resonant filters (PsrA and PsrB)
were calculated using the following equation:
The efficiency η of the measured power was calculated according to the following equation:
Pout1 + Pout2
η= . (9)
Pin
For the measured voltage and current, the power of the primary side of the transformer (Ptxp ),
power of the secondary side of the transformer (Ptxs ) and power of the resonant filters (PsrA and PsrB )
were calculated using the following equation:
40T
1 X
P= v(t)i(t)∆T n = 6, 7, 8, 9. (10)
40T
0
In the above, n is the number of cycles contained in the 100 µs measured, T is the length of a
cycle, v(t) and i(t) are the measured voltage and current, respectively and ∆T is the time interval of
the oscilloscope of 0.1 ns. Owing to the conditions of the measuring system, each series of data was
obtained with three or four measurements, which could produce errors in the measurement results.
4.2. Efficiency Characteristics

Figure 20 depicts the efficiency at each operation point with Pout1 on the x-axis. The lowest
efficiency of 68.3% was registered at point #16, where Pout1 was the minimum and Pout2 was the
maximum. Meanwhile, the maximum efficiency was 88.9% at point #06, where Pout1 was the maximum
and Pout2 was the minimum. When Pout2 was constant, the efficiency increased along with Pout1 ,
regardless of the value of Pout2 , indicating that the load losses caused by Pout2 and other fixed losses
were larger than the load losses related to Pout1 . However, when Pout1 was constant, the overall
efficiency decreased as Pout2 increased, regardless of the value of Pout1 . This indicates that the load
losses related to Pout2 were larger than those caused by Pout1 and other fixed losses. Therefore, the load
World of Pout2
lossesElectric had
Vehicle a significant
Journal 2020, 11, x impact on the efficiency of this circuit. 18 of 21
90
#5 #6
85 #4
Total efficiency (%)
#3
#11
#2 #10
80 #9
#1 #8 #15
#14
75 Pout2 ≈ 142W
#7 #13 #18 P#out2 ≈ 268W
70 #12 #17 Pout2 ≈ 394W
#16 Pout2 ≈ 499W
65
0 100 200 300 400 500 600 700 800 900 1000
Pout1 (W)
Figure 20.
Figure Results of
20. Results of efficiency
efficiency measurements.
measurements.
4.3. Loss Analysis

4.3. Loss Analysis
To analyze the loss points, loss separation was performed when the ratio of P to the total
To analyze the loss points, loss separation was performed when the ratio of Pout1 out1 to the total
output power (Pout1 + Pout2 ) was the maximum (#06), when the ratio of Pout2 was the maximum (#16)
output power (Pout1 + Pout2) was the maximum (#06), when the ratio of Pout2 was the maximum (#16)
and under intermediate conditions (#10). For the power at each part obtained by the measurement and
and under intermediate conditions (#10). For the power at each part obtained by the measurement
calculation, the losses at the inverter (Winv ), transformer (Wtx ), series resonant filter (Wsr ) and rectifier
and calculation, the losses at the inverter (Winv), transformer (Wtx), series resonant filter (Wsr) and
circuit (Wrec ), as well as the total loss (Wtotal ), were calculated using the equation shown in Table 6.
rectifier circuit (Wrec), as well as the total loss (Wtotal), were calculated using the equation shown in
The results are illustrated in Figure 21. The left axis indicates the losses and the right axis represents
Table 6. The results are illustrated in Figure 21. The left axis indicates the losses and the right axis
the ratio of Pout2 to the total output power.
represents the ratio of Pout2 to the total output power.
Table 6. Loss calculations.
Part Symbol Equation

Total loss Wtotal Pin − (Pout1 + Pout2)
Inverter loss Winv Pin − Ptxp
Transformer loss Wtx Ptxp − Ptxs
Table 6. Loss calculations.
Part Symbol Equation

Total loss Wtotal Pin − (Pout1 + Pout2 )
Inverter loss Winv Pin − Ptxp
Transformer loss Wtx Ptxp − Ptxs
Resonant filter loss Wsr Pr1 + Pr2
Rectifier circuit loss
World Electric Vehicle Journal 2020, 11, x
Wrec Wtotal − (Winv + Wtx + W sr ) 19 of 21
400 100
Rectifier circuit loss
350 Resonant filter loss 132
80
300 Transformer loss
rate of Pout2 (%)

Power loss (W)
Inverter loss
250 60
200
→
72
125 40
150
24.4
100 25.4 45.5
43.6 41.1 20
50 34.4
51.1 46.1 62.1
0 0
#06 #10 #16
Measurement points
Figure 21. Loss analysis results.
As indicated
Given that Winv inandFigure
Wtx 21,
at #06 Wtotal values
the(which exhibited at the
the operation points were
highest efficiency) 144 Wfor
accounted (#06),
more 198thanW
(#10)
half of and 360, it
Wtotal Wis(#16), whereas
possible the ratios
to increase Pout2 wereefficiency
theofmaximum 14.4% (#06),by 32.5%
reducing (#10) and
Winv and 76.7%
Wtx.(#16).
It is
Therefore, W
necessary to select total increased as the ratio
switching devices that suit of P increased. Figure 15 demonstrates that,
out2the operation specifications to reduce Winv, whereas as the ratioa
of
corePout2
with low lossftxshould
increased, also increased
be selected and,andsimultaneously,
the core structure the impedance the Vout2 side
needs to beofoptimized decreased
to reduce Wtx.
and the value of the filter current increased. As a result, the currents
However, as the efficiency was the lowest when the ratio of Pout2 was the maximum (#16), Wsr and of the inverter, transformer and
rectifier
Wrec, whichcircuit
were increased,
producedaswhen did thetheconduction
current of the losses
Vout2of each
-side part. increased,
circuit Moreover,limited
the switching losses
the efficiency
of
of the
the inverter
proposed and rectifier
circuit. circuit increased,
Therefore, reducing as did two
these the core losses
values canof the transformer
effectively improve andtheinductor.
overall
Therefore, as f increased, the losses of all parts increased; however, the
efficiency of the circuit. Decreasing the peak value of the resonant filter current has been suggested
tx fact that the increase ratio of
W and W
assra possible was larger than that
rec means of reducing the Qinv of W and W and the total output power decreased
value oftxthe series resonant filter but decreasing the Q value as the ratio of
P out2 increased,
means decreasing indicates that thereofwas
the sensitivity the little
impedance in Winv and
changechanges to theWtxfrequency Wsr and W
, whereas changes. increased
Inrecthis case, it
at the three operation points, as illustrated in Figure 21.
will be necessary to expand the operating frequency range to offset the amount of impedance
change.Given that Winvifand
However, the W tx at #06
range (which exhibited
is expanded the highest efficiency)
to the high-frequency side, an accounted
increasedforloss morewillthanbe
half of W , it is possible to increase the maximum efficiency by reducing
caused by the higher frequencies, as mentioned previously. Furthermore, if it is expanded to the
total W inv and W tx . It is necessary
to select switching
low-frequency devices
side, that suitof
the problem thea operation specifications
volume increase in thetocore
reduce Winv
of the , whereas a core
transformer and with
inductorlow
loss
will should be selecteditand
occur. Therefore, the core structure
is necessary to determineneeds thetooptimal
be optimized to reduce Wtx . However, as the
conditions.
efficiency was the lowest when the ratio of Pout2 was the maximum (#16), Wsr and Wrec , which were
produced
5. Conclusionswhen the current of the Vout2 -side circuit increased, limited the efficiency of the proposed
circuit. Therefore, reducing these two values can effectively improve the overall efficiency of the circuit.
This paper has presented a new method to control isolated single-input, dual-output DC/DC
Decreasing the peak value of the resonant filter current has been suggested as a possible means of
converters that are designed to be installed in EVs, PHVs and FCVs. The proposed method involves
reducing the Q value of the series resonant filter but decreasing the Q value means decreasing the
dual voltage control by the duty cycle and frequency, which is realized by inserting parts with
sensitivity of the impedance changes to the frequency changes. In this case, it will be necessary to
frequency-impedance characteristics into the circuit. To verify its efficacy, the proposed control
expand the operating frequency range to offset the amount of impedance change. However, if the range
method was applied to an actual circuit in which a series resonant filter was inserted in one of the
is expanded to the high-frequency side, an increased loss will be caused by the higher frequencies,
diode bridge smoothing circuits that were connected in parallel to the secondary side of the
as mentioned previously. Furthermore, if it is expanded to the low-frequency side, the problem of a
transformer.
volume increase in the core of the transformer and inductor will occur. Therefore, it is necessary to
The results of the static characteristics indicate that two output voltages were adjusted to their
determine the optimal conditions.
respective target values 48 V and 12 V for the maximum output power 1037 W (Pout1 = 461 W, Pout2 =
576Conclusions
5. W). The dynamic characteristics results show that when switching each output power, it
recovered to a steady state within 8 ms after the switching of the operation point. The circuit
This paper has presented a new method to control isolated single-input, dual-output DC/DC
behaviors at the different load conditions are analyzed by the simulation of the ideal circuit and the
converters that are designed to be installed in EVs, PHVs and FCVs. The proposed method involves
simulation waveforms were close to the experimental waveforms. These results demonstrated the
validity of the proposed control method.
The efficiency of the circuit varied between 68.3% and 88.9%. The loss separation analysis
indicated that the losses in the series resonant filter and diode bridge smoothing circuit account for
71% of the total loss and restricted the efficiency. The maximum efficiency of the circuit can be
dual voltage control by the duty cycle and frequency, which is realized by inserting parts with
frequency-impedance characteristics into the circuit. To verify its efficacy, the proposed control method
was applied to an actual circuit in which a series resonant filter was inserted in one of the diode bridge
smoothing circuits that were connected in parallel to the secondary side of the transformer.
The results of the static characteristics indicate that two output voltages were adjusted to their
respective target values 48 V and 12 V for the maximum output power 1037 W (Pout1 = 461 W,
Pout2 = 576 W). The dynamic characteristics results show that when switching each output power,
it recovered to a steady state within 8 ms after the switching of the operation point. The circuit
behaviors at the different load conditions are analyzed by the simulation of the ideal circuit and the
simulation waveforms were close to the experimental waveforms. These results demonstrated the
validity of the proposed control method.
The efficiency of the circuit varied between 68.3% and 88.9%. The loss separation analysis indicated
that the losses in the series resonant filter and diode bridge smoothing circuit account for 71% of
the total loss and restricted the efficiency. The maximum efficiency of the circuit can be effectively
increased by reducing the losses in the inverter and transformer because these losses constitute 66% of
the total loss.
Our goal for future research is to examine the following points that were not covered in this study:
controlling the circuit with a power supply voltage applied; improving the efficiency by considering
modifications in the main circuit; and selecting the parts and designing the layout with the aim
of miniaturization.
Author Contributions: Conceptualization, K.S., T.N.; methodology, K.S., Y.M. and T.N.; software, Y.M.; validation,
Y.M., T.N.; formal analysis, Y.M.; investigation, Y.M.; data curation, Y.M.; writing—original draft preparation,
Y.M.; writing—review and editing, Y.M., T.N.; supervision, T.N.; project administration, N.T., M.I. All authors
have read and agreed to the published version of the manuscript.
Funding: This research received no external funding.
Conflicts of Interest: The authors declare no conflict of interest.
References
1. IEA—International Energy Agency. CO2 Emissions from Fuel Combustion: Overview. Available online:
https://www.iea.org/reports/co2-emissions-from-fuel-combustion-overview (accessed on 28 September 2020).
2. IEA—International Energy Agency. Global EV Outlook 2020. Available online: https://www.iea.org/reports/
global-ev-outlook-2020 (accessed on 28 September 2020).
3. Krismer, F.; Kolar, J.W. Efficiency-Optimized High-Current Dual Active Bridge Converter for Automotive
Applications. IEEE Trans. Ind. Electron. 2012, 59, 2745–2760. [CrossRef]
4. Hou, R.; Magne, P.; Bilgin, B.; Emadi, A. A topological evaluation of isolated DC/DC converters for Auxiliary
Power Modules in Electrified Vehicle applications. In Proceedings of the 2015 IEEE Applied Power Electronics
Conference and Exposition (APEC), Charlotte, NC, USA, 15–19 March 2015.
5. Rhodes, K.; Kok, D.; Sohoni, P.; Perry, E.; Kraska, M.; Wallace, M. Estimation of the Effects of Auxiliary Electrical
Loads on Hybrid Electric Vehicle Fuel Economy; SAE Technical Paper 2017-01-1155; SAE International: Pittsburgh,
PA, USA, 2017.
6. Adriano, S.; Chiara, F.; Fabrizio, Z.; Alessandro, D.; Fabio, O.; Annalisa, D. Experimental Analysis of the
Auxiliaries Consumption in the Energy Balance of a Pre-series Plug-in Hybrid-electric Vehicle. Energy Procedia
2014, 45, 779–788. [CrossRef]
7. Teratani, T. Impact of DC48V on Automotive Power Supply Systems—Comparison with DC42V and Future
View under DC60V. IEEJ Trans. Ind. Appl. 2015, 135, 892–897. [CrossRef]
8. Hayslett, S.; Maanen, K.V.; Wenzel, W.; Husain, T. The 48-V Mild Hybrid: Benefits, Motivation, and the
Future Outlook. IEEE Electrif. Mag. 2020, 8, 11–17. [CrossRef]
9. Chen, G.; Deng, Y.; Dong, J.; Hu, Y.; Jiang, L.; He, X. Integrated Multiple-Output Synchronous Buck Converter
for Electric Vehicle Power Supply. IEEE Trans. Veh. Technol. 2017, 66, 5752–5761. [CrossRef]
10. Kim, T.; Baek, S. Multiple bus motor drive based on a single inductor multi output converter in 48 V electrified
vehicles. In Proceedings of the 2017 IEEE International Electric Machines and Drives Conference (IEMDC),
Miami, FL, USA, 21–24 May 2017.
11. Kim, T.; Kwak, S. A Flexible Voltage Bus Converter for the 48-/12-V Dual Supply System in Electrified
Vehicles. IEEE Trans. Veh. Technol. 2017, 66, 2010–2018. [CrossRef]
12. Dao, N.D.; Lee, D.; Phan, Q.D. High-Efficiency SiC-Based Isolated Three-Port DC/DC Converters for Hybrid
Charging Stations. IEEE Trans. Power Electron. 2020, 35, 10455–10465. [CrossRef]
13. Tang, Y.; Lu, J.; Wu, B.; Zou, S.; Ding, W.; Khaligh, A. An Integrated Dual-Output Isolated Converter for
Plug-in Electric Vehicles. IEEE Trans. Veh. Technol. 2018, 67, 966–976. [CrossRef]
14. Inoue, S.; Itoh, K.; Ishigaki, M.; Sugiyama, T.; Sugai, M. An isolated three-port DC-DC converter with high
power density in 10 cm × 5cm × 0.8 cm card size for flexible automotive systems. In Proceedings of the 2016
IEEE Energy Conversion Congress and Exposition (ECCE), Milwaukee, WI, USA, 18–22 September 2016.
15. Matsushita, Y.; Noguchi, T.; Kimura, O.; Sunayama, T. Current-doubler based multiport DC/DC converter
with galvanic isolation. In Proceedings of the 2017 IEEE 12th International Conference on Power Electronics
and Drive Systems (PEDS), Honolulu, HI, USA, 12–15 December 2017.
16. Noguchi, T.; Shimizu, K.; Matsushita, Y. Dual-port output control of isolated DC/DC converter focusing on
duty cycle and frequency of primary inverter. In Proceedings of the 2017 IEEE 12th International Conference
on Power Electronics and Drive Systems (PEDS), Honolulu, HI, USA, 12–15 December 2017.
17. Jones, E.A.; Rooij, M.; Biswas, S. GaN Based DC-DC Converter for 48 V Automotive Applications.
In Proceedings of the 2019 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia
(WiPDA Asia), Taipei, Taiwan, 23–25 May 2019.
18. Martines-Heredia, J.M.; Colodro, F.; Mora-Jiménez, J.L.; Remujo, A.; Soriano, J.; Esteban, S. Development of
GaN Technology-Based DC/DC Converter for Hybrid UAV. IEEE Access 2020, 8, 88014–88025. [CrossRef]
19. Mitova, R.; Ghosh, R.; Mhaskar, U.; Klikic, D.; Wang, M.; Dentella, A. Investigations of 600-V GaN HEMT and
GaN Diode for Power Converter Applications. IEEE Trans. Power Electron. 2014, 29, 2441–2452. [CrossRef]
20. Huang, X.; Lee, F.C.; Li, Q.; Du, W. High-Efficiency GaN-Based Interleaved CRM Bidirectional Buck/Boost
Converter with Inverse Coupled Inductor. IEEE Trans. Power Electron. 2016, 31, 4343–4352. [CrossRef]
21. Rahmani, F.; Niknejad, P.; Agarwal, T.; Barzegaran, M. Gallium Nitride Inverter Design with Compatible
Snubber Circuits for Implementing Wireless Charging of Electric Vehicle Batteries. Machines 2020, 8, 56.
[CrossRef]
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional
affiliations.
© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access
article distributed under the terms and conditions of the Creative Commons Attribution
(CC BY) license (http://creativecommons.org/licenses/by/4.0/).

Control of Dual-Output DC Duty Cycle and Frequency

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Control of Dual-Output DC Duty Cycle and Frequency

Uploaded by

Copyright:

Available Formats

Article

Control of Dual-Output DC/DC Converters Using

1.1. Research Motivations

World Electric Vehicle Journal 2020, 11, 72; doi:10.3390/wevj11040072 www.mdpi.com/journal/wevj

1.2. Literature Review

2. Overview of Proposed Control Method and Main Circuit Configuration

2.1. Overview of Proposed Control Method and Main Circuit Configuration

Figure 2. Circuit configuration for applying proposed control method.

3. Verification of Proposed Method Using Actual Circuit

3.1. Circuit Specifications

Table 1. Specifications of experimental circuit.

Figure 7. Dual port output waveforms.

300 #7 #8 #9 #10 #11

and Itxs), thefrom

Table 4. Definition of operation modes.

Table 5. Operation modes and measurement points.

• Group A: Lout1 is charged (modes 1 to 5)

• Group B: Lout1 discharges (modes 6 to 10)

Group A: Lout1 is charged (modes 1 to 5) Iret1 Iret1

Transformer25→ D11 → Zsm1 → D14 → Transformer. I srB

illustrated in30Figure 11b. When Lout1 is discharged,

(a) (b) (c)

group A group B group C group A group B group C

Frequency (kHz) Frequency (kHz)

#01 (154W) #01 (140W)

#04 (570W) #12 (427W)

Itxp, Itxs (A)

ILout1, Iout1 (A) Vd11, Vd12 (V)

Vtxp, IVsr1txs, I(V)

Isr1, Isr2 (A)Icir (A)

0 0 IsrA IsrB IsrA IsrB

ILout2, Iout2 (A) Vd21, Vd22 (V) Vsr1, Vsr2 (V)

55 85 #9 #4 #15 #4 Pout1 ≈ 154W

World Figure 15. Results

Duty of transformer voltage (%)

4.2. Efficiency Characteristics

4.3. Loss Analysis

Table 6. Loss calculations.

Part Symbol Equation

Table 6. Loss calculations.

Part Symbol Equation

rate of Pout2 (%)

Figure 21. Loss analysis results.

You might also like