VLSI Lab Manual

VIDYA JYOTHI INSTITUTE OF TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
EMBEDDED AND VLSI LABORATORY

[For students admitted in the Academic Year: 2018 onwards]
Regulations : R 2018 / R2020
Class : III Year II Semester (ECE)
Prepared by
Mr. Sandeep
Assistant Professor
JUNE 2018
EMBEDDED LAB MANUAL R18 & R20
Vision
The Electronics & Communication Engineering department intends to be a leader in
creating the high quality engineers in the field of electronics and associated
technologies to cater to national and global technological needs promoting the human
prosperity and wellbeing.
Mission
 Providing an infrastructural and conducive environment to the students, faculty and
researchers for attaining domain knowledge and expertise in electronics &
communication engineering.
 Enable the students to develop into outstanding professionals with high ethical standards
capable of creating, developing and managing global engineering enterprises.
 Inculcate the spirit of lifelong learning by interacting with outside world and strengthen
professional, communication skills.
Quality Policy
Our policy is to nurture and build diligent and dedicated community of engineers
providing a professional and unprejudiced environment, thus justifying the purpose of
teaching and satisfying the stake holders.
A team of well qualified and experienced professionals ensure quality education with
its practical application in all areas of the Institute.
Philosophy
The essence of learning lies in pursuing the truth that liberates one from the darkness
of ignorance and Institute of Vidya Jyothi Institute of Technology firmly believes that
education is for liberation. Contained therein is the notion that engineering education
includes all fields of science that plays a pivotal role in the development of world-
wide community contributing to the progress of civilization. This institute, adhering to
the above understanding, is committed to the development of science and technology
in congruence with the natural environs. It lays great emphasis on intensive research
and education that blends professional skills and high moral standards with a sense of
individuality and humanity. We thus promote ties with local communities and
encourage transnational interactions in order to be socially accountable. This
accelerates the process of transfiguring the students into complete human beings
making the learning process relevant to life, instilling in them a sense of courtesy and
responsibility.
2 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

Program Outcomes
PO1 Engineering knowledge: An ability to apply knowledge of basic sciences,
mathematical skills, engineering and technology to solve complex
electronics and communication engineering problems (Fundamental
Engineering Analysis Skills).
PO2 Problem analysis: An ability to identify, formulate and analyze
engineering problems using knowledge of Basic Mathematics and
Engineering Sciences. (Engineering Problem Solving Skills).
PO3 Design/development of solutions: An ability to provide solution and to
design Electronics and CommunicationSystems as per social needs
(Social Awareness)
PO4 Conduct investigations of complex problems: An ability to investigate the
problems in Electronics and Communication field and develop suitable
solutions (Creative Skills).
PO5 Modern tool usage An ability to use latest hardware and software tools to
solve complex engineering problems (Software and Hardware Interface).
PO6 The engineer and society: An ability to apply knowledge of contemporary
issues like health, Safety and legal which influences engineering design
(Social Awareness).
PO7 Environment and sustainability An ability to have awareness on society
and environment for sustainable solutions to Electronics & Communication
Engineering problems (Social awareness).
PO8 Ethics: An ability to demonstrate understanding of professional and ethical resp
PO9 Individual and team work: An ability to work efficiently as an
individual and in multidisciplinary teams (Team Work).
PO10 Communication: An ability to communicate effectively and efficiently both
in verbal and written form (Communication Skills).
PO11 Project management and finance: An ability to develop confidence to
pursue higher education and for life-long learning (Continuing education
awareness).
PO12 Life-long learning: An ability to design, implement and manage the
electronic projects for real world applications with optimum financial
resources (Practical engineering analysis skills).
Program Specific
Outcomes
PSO1 Professional Skills: An ability to understand the basic concepts in
Electronics & Communication Engineering and to apply them to various
areas, like Electronics, Communications, Signal processing, VLSI,
embedded systems etc., in the design and implementation of complex
systems.
PSO2 Problem-solving skills: An ability to solve complex Electronics and
communication Engineering problems, using latest hardware and software
tools, along with analytical skills to arrive cost effective and appropriate
solutions.

EMBEDDED & VLSI LABORATORY
IV B.Tech I Semester
L T P C
0 0 2 1
COURSE OUTCOMES:
At the end of the course the student should be able to
1. Code the ARM cortex M0+ processor instruction set.

2. Articulate the concept of interfacing I/O devices with FRDM kit.
3. Synthesize a Verilog code for digital circuits
4. Devise the digital circuit in CPLD/FPGA
5. Formulate a system design using Embedded and VLSI technologies
Perform any 10 Experiments from each lab:

Embedded System Design Lab:
1. Blinking of LED : Hello World
2. Breath out 2 LEDs
3. Color Circle
4. ADC Potentiometer
5. Analog serial plotter
6. Interface to Accelerometer sensor using FRDM kit
7. Serial port communication using FRDM kit
8. Interface to touch sensor using FRDM kit
9. Radio frequency transmission operation using FRDM kit
10. LED intensity control using touch sensor using FRDM kit
11. Interface and plot LDR using FRDM kit
12. Interface and plot temperature sensor using FRDM kit
VLSI lab:
1. Verification of Logic Gates
2. Verification of Demorgon’s Law
3. Design of 8 to 1 multiplexer
4. Design of 1 to 8 Demultiplexer
5. Design of 2 to 4 Encoder
6. Design of 4-bit comparator
7. Design of 4 bit binary to gray converter
8. Design of full adder using 3 modeling styles
9. Design of flip flops SR, D, JK, and T
10. Design Ripple Counter
11. Design Modulo Counter
12. Design Shift Register
13. Design Inverter using PMOS / NMOS
14. Design of full adder using decoder and multiplexer
15. Design System using finite state Machine

LIST OF EXPERIMENTS WITH PROGRAM OUTCOMES

& PROGRAM SPECIFIC OUTCOMES
Program
Program
S.No. Experiment Specific
Outcomes
Outcomes
Attained
Attained


INSTRUCTIONS TO THE STUDENTS
1. Students are required to attend all labs.
2. Students should work individually in the hardware and software laboratories.
3. Students have to bring the lab manual cum observation book, record etc along
with them whenever they come for lab work.
4. Should take only the lab manual, calculator (if needed) and a pen or pencil to the
work area.
5. Should learn the prelab questions. Read through the lab experiment to familiarize
themselves with the components and assembly sequence.
6. Should utilize 3 hours’ time properly to perform the experiment and to record the
readings. Do the calculations, draw the graphs and take signature from the
instructor.
7. If the experiment is not completed in the stipulated time, the pending work has to
be carried out in the leisure hours or extended hours.
8. Should submit the completed record book according to the deadlines set up by the
instructor.
9. For practical subjects there shall be a continuous evaluation during the semester
for 25 seasonal marks and 50 end examination marks.
10. Out of 25 internal marks, 15 marks shall be awarded for day-to-day work and 10
marks to be awarded by conducting an internal laboratory test.

LAB SYLLABUS
VLSI LABORATORY
S. Date List of Experiments Page Remarks

No. No.
Verification of Logic gates
1.
2. Verification of Demorgon’s law
3. Design of 8-to-1 multiplexer
4. Design of 1-to-8 Demultiplexer
5. Design of 2 to 4 Encoder
6. Design of 4 bit comparator

7. Design of 4 bit binary to gray converter
8. Design of Full adder using 3 modeling styles
9. Design of flip flops: SR, D, JK, T
10. Design of Ripple counter
11. Design of Modulo counter
12. Design of Shift Register
13. Design Inverter using PMOS/NMOS
14. Design of Full adder using decoder and
multiplexer
15. Design system using Finite State Machine

Introduction to Xilinx ISE Software

Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL
designs, which enables the developer to synthesize ("compile") their designs, perform
timing analysis, examine RTL diagrams, simulate a design's reaction to different
stimuli, and configure the target device with the programmer.
In our Lab, the scope is limited to design and analyze the design using test benches &
simulation.
The following is the step by step procedure to design in the Xilinx ISE:
1. New Project Creation

Once the Xilinx ISE Design suite is started, open a new project & enter your
design name and the location path. By default „HDL‟ is selected as the top-level
source type. (If not, please select Top-level source type as „HDL‟)
2. Continue to the next window and check if preferred language is selected as” verilog”

2. Continue to the next window and check if the Preferred Language is selected as „Verilog‟
3. Proceed by clicking „Next‟ and create a „New Source‟ using the „Create New
Source‟Window

DEPARTMENT OF ECE ECAD&VLSI LAB
4. Select the source type as „Verilog Module‟ and input a filename and proceed
to „Next‟.In the next window „Define Module‟ enter the ports.
5. Finish with the New project setup with the „Summary‟ window.

6. Once „Finish‟ is selected a pop-up appears to create the directory. Select „yes‟
7. Then proceed to „Next‟ in the “New Project Wizard‟ to „Add Existing

Sources‟. „Addsource‟ if an existing source is available, If not
proceed to „Next‟ and finish with the „Project Summary‟ window

8. Design Entry and Syntax Check
The ports defined during the „Project Creation‟ are defined as a module in the
„filename.v‟file
9. Input your design (verilog code) within the module definition

10. Select the design from the „Hierarchy„window. In the below window of Processes
„Implement Design „would be orange (in color) ready for implementation
11. Double click on implement design, it turns green (in color) once
the design isimplemented successfully and the Summary report
is displayed.

12. Test-Bench creation, Simulation & Verification
To add a test-bench to the existing design, right click on the „.v‟ file from
the Hierarchywindow and select „New Source‟
13. Select „Verilog Text Fixture‟ from the Select Source Type and name the Test-Bench

14. Continue to „Finish‟ and a test bench is added in the project area
15. Edit the test bench as per your simulation requirements and select
„Behavioral Simulation‟ in the „Design Window‟. In the Processes window
Isim Simulator would be displayed. First Proceed with the Behavioral Check
Syntax

Syntax‟ & check for no errors
16. D
o
u
b
l
e
c
l
i
c
k
o
n
„ 17. Then double click on „Simulate Behavioral Model‟ and the ISIM
B simulator windowwould open. Check for the outputs
e
h
a
v
i
o
r
a
l
C
h
17e DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75
c
k
EXP: 1- HDL CODE TO REALIZE ALL LOGIC GATES
AIM: To develop the source code for logic gates by using VERILOG and obtain the simulation,
Synthesis.
SOFTWARE & HARDWARE:
1. XILINX 7.1i
LOGIC DIAGRAM:
AND GATE: OR GATE:
LOGIC DIAGRAM: TRUTH TABLE: LOGICDIAGRAM TRUTH

TABLE:
A B Y=AB A B Y=A+B
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1
NOT GATE: NAND GATE:

LOGIC DIAGRAM: TRUTH TABLE: LOGICDIAGRAM TRUTH TABLE
A B Y=(AB)’
A Y=A’
0 0 1
0 0 0 1 1
0 1 1 0 1
1 1 0
NOR GATE: XOR GATE:

LOGIC DIAGRAM: TRUTH TABLE: LOGICDIAGRAM TRUTH TABLE:
A B Y=(A+B)’
A B
0 0 1
0 1 0 0 0 0
1 0 0 0 1 1
1 1 0
1 0 1
1 1 0

SOURCE CODE:
module logicgates1(a,b,and1,or1,nand1,nor1,xor1,xnor1,not1);
input a;
input b;
output and1,or1,nand1,nor1,xor1,xnor1,not1;
assign and1=a&b;
assign or1=a|b;
assign nand1=~(a&b);
assign nor1=~(a|b);
assign xor1=a^b;
assign xnor1=~(a^b);
assign not1=~a;
endmodule
TEST BENCH:
module tb_logicgates();
reg a,b;
wire and1,or1,nand1,nor1,xor1,xnor1,not1;
logicgates dut
(.a(a),.b(b),.and1(and1),.or1(or1),.nand1(nand1),.nor1(nor1),.xor1(xor1),.xnor1(xnor1),.not1(not1)
);
initial
begin
a=1'b0;
b=1'b0;
#10
a=1'b0;
b=1'b1;
#10
a=1'b1;
b=1'b0;
#10
a=1'b1;
b=1'b1;
end
initial
begin
$monitor("%time,a=%b,b=%b,and1=%b,or1=%b,nand1=%b,nor1=%b,xor1=%b,xnor1=%b,not1=
%b",$time,a,b,and1,or1,nand1,nor1,xor1,xnor1,not1);
end
endmodule

Simulation Results:
Synthesis RTL Schematic:
RESULT:
Thus the OUTPUT‟s of all logic gates are verified by synthesizing

and simulatingthe VERILOG code.

EXP:2- VERIFICATION OF DEMORGON’S LAW
AIM: To develop the source code for De margan’s theorem by using verilog code and
obatain simulation and synthesis report
Circuit Diagram:
Truth Table:

Verilog source code:
// Verilog code for AND-OR-INVERT gate
module AOI (F, A, B, C, D);

output F; input A, B, C, D;
wire AB, CD, O; // necessary
assign AB = A & B;
assign CD = C & D;
assign O = AB | CD; assign
F = ~O;
Endmodule

Experiment 3- Design of 8-to-1 multiplexer
Aim: The purpose of this experiment is to write and simulate a VERILOG program
for Multiplexers
XILINX 7.1i
Theory:
Multiplexer is a special type of combinational circuit. There are n-data inputs, one output and m
select inputs with 2m = n. It is a digital circuit which selects one of the n data inputs and routes it
to the output. The selection of one of the n inputs is done by the selected inputs. Depending on the
digital code applied at the selected inputs, one out of n data sources is selected and transmitted to
the single output Y. E is called the strobe or enable input which is useful for the cascading. It is
generally an active low terminal that means it will perform the required operation when it is low.
LOGIC DIAGRAM:
Verilog source code: Structural model
modulemux81str(i0,i1,i2,i3,i4,i5,i6,i7,s0, s1,s2,y);
input i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2; wire a,b,c,d,e,f,g,h;
output y;
and g1(a,i7,s0,s1,s2);
and g2(b,i6,(~s0),s1,s2);
and g3(c,i5,s0,(~s1),s2);
and g4(d,i4,(~s0),(~s1),s2);
and g5(e,i3,s0,s1,(~s2));
and g6(f,i2,(~s0),s1,(~s2));
and g7(g,i1,s0,(~s1),(s2));
and g8(h,i0,(~s0),(~s1),(~s2));
or(y,a,b,c,d,e,f,g,h);
endmodule

Simulation Report:

Experiment 4- Design of 1-to-8 Demultiplexer
Aim: The purpose of this experiment is to write verilog code and simulate a
VERILOG program for De-Multiplexers
XILINX 7.1i
Theory:
A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and
distributes it over several outputs. It has only one input, n outputs, m select input. At a time only
one output line is selected by the select lines and the input is transmitted to the selected output line.
module demux18df(in,s0,s1,s2,i0,d1,d2,d3,d 4,d5,d6,d7);

input in,s0,s1,s2;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0 = in & s0 & s1 & s2;
assign d1 = in & (~s0) & s1 & s2;
assign d2 = in & s0 & (~s1) & s2;
assign d3 = in & (~s0) &( ~s1) & s2;
assign d4 = in & s0 & s1 & (~s2);
assign d5 = in & (~s0) & s1 & (~s2);
assign d6 = in & s0 & (~s1) & (~s2);
assign d7 = in & (~s0) & (~s1) & (~s2);
endmodule
Logic Diagram:

Simulation Report:

Experiment 4- Design of 4 to 2 Encoder
Aim: The purpose of this experiment is to write verilog code and simulate a VERILOG
program for De-Multiplexers
XILINX 7.1i
Theory:
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
maximum of 2n input lines and ‘n’ output lines. It will produce a binary code equivalent to
the input, which is active High. Therefore, the encoder encodes 2n input lines with ‘n’ bits. It
is optional to represent the enable signal in encoders
Circuit diagram:
Module enc83df(d0,d1,d2,d3,d4,d5,d6,d7,q0,q 1,q2);

Input d0,d1,d2,d3,d4,d5,d6,d7;
Output q0,q1,q2;
assign q0=d1|d3|d5|d7;
endmodule
Test Bench:

module tb_encoder();
reg [3:0]x;
wire a,b,c;
encoder dut(.x(x),.a(a),.b(b),.c(c));
initial
begin
x=4'b1000;
#10
x=4'b0001;
#10
x=4'b0010;
#10
x=4'b011;
end
initial
begin
$monitor("%t,x=%b;a=%b,b=%b,c=%b",$time,x,a,b,c);
end
endmodule
Simulation Results:
Synthesis Results:
Results: Thus the OUTPUT’s of Encoder is verified by synthesizing and simulating

the VERILOG code

Experiment 5: Design of 4 bit comparator
AIM : To develop the source code for Comparator by using VERILOG and obtained the
simulation, synthesis.
Components used:
1 Xilinx ISE 7.1i Tool
LOGIC DIAGRAM & TRUTH TABLE:
4 BIT COMPARATOR:
LOGIC DIAGRAM: TRUTH TABLE:

X Y Z
A<B 0 1 0
A=B 1 0 0
A>B 0 0 1
SOURCE CODE:
module comparator(a, b, x, y, z);

input [3:0]a;
input [3:0]b;
output x;
output y;
output z;
reg x,y,z;
always@(a or b)
begin
if(a==b)
begin
x=1'b1;
y=1'b0;
z=1'b0;
end
else if (a<b)
begin
x=1'b0;
y=1'b1;
z=1'b0;
end
else
begin

x=1'b0;
y=1'b0;
z=1'b1;
end
end
endmodule
TEST BENCH:
module tb_comparator();
reg [3:0]a;
reg [3:0]b;
wire x,y,z;
comparator dut (.a(a),.b(b),.x(x),.y(y),.z(z));
initial
begin
a=4'b0000;
b=4'b0100;
#10
a=4'b0100;
b=4'b0100;
#10
a=4'b0100;
b=4'b0000;
end
initial
begin
$monitor("%t,a=%b,b=%b,x=%b,y=%b,z=%b",$time,a,b,x,y,z);
end
endmodule
Simulation Results:
RESULT:
Thus the OUTPUT of Comparator are verified by synthesizing and simulating the
VERILOG code

Experiment 7: Design of 4 bit binary to gray converter
AIM : To develop the source code for code converters by using VERILOG and obtained the
simulation, synthesis, place and route and implement into FPGA.
Components used: 1. Xilinx ISE 7.1i Tool
CODE CONVERTER (BINARY TO GRAY):
TRUTH TABLE:
BINA GRAY
RY
0000 0000 LOGIC DIAGRAM:
0001 0001
0010 0011
0011 0010
0100 0110
0101 0111
0110 0101
0111 0100
1000 1100
1001 1101
1010 1111
1011 1110
1100 1010
1101 1011
1110 1001
1111 1000
SOURCE CODE:
module binary2gray(b,g);
input [3:0] b;
output [3:0] g;
assign g[3]=b[3];
assign g[2]=b[3]^b[2];
endmodule
TEST BENCH:
module tb_binary2gray();
reg [3:0]b;

wire [3:0]g;
binary2gray dut (.b(b),.g(g));
initial
begin
b=4'b0000;
#10
b=4'b0001;
#10
b=4'b0010;
#10
b=4'b0011;
#10
b=4'b0100;
#10
b=4'b0101;
#10
b=4'b0110;
#10
b=4'b0111;
#10
b=4'b1000;
#10
b=4'b1001;
#10
b=4'b1010;
#10
b=4'b1011;
#10
b=4'b1100;
#10
b=4'b1101;
#10
b=4'b1110;
#10
b=4'b1111;
end
initial
begin
$monitor("%t,b=%b,g=%b",$time,b,g);
end
endmodule

Simulation result:
RESULT: Thus the OUTPUT’s of Code converters are verified by synthesizing and
simulating the VERILOG code

Experiment 8: Design of Full adder using 3 modeling styles
AIM : To develop the source code for code full adder by using VERILOG and obtained the
simulation, synthesis, place and route and implement into FPGA.
FULL ADDER:
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
SOURCE CODE: 1 1 1 1 1
module fulladdder(a, b, c, s, ca);
input a;
input b;
input c;
output s;
output ca;
wire p,q,r;
assign p=a&b;
assign q=b&c;
assign r=c&a;
assign s=a^b^c;
assign ca =(p|q|r);
endmodule
TEST BENCH:
module tb_fulladdder();
reg a,b,c;
wire s,ca;
fulladdder dut (.a(a),.b(b),.c(c),.s(s),.ca(ca));
initial
begin
a=1'b0;
b=1'b0;
c=1'b0;
#10
a=1'b0;
b=1'b0;

c=1'b1;
#10
a=1'b0;
b=1'b1;
c=1'b0;
#10
a=1'b0;
b=1'b1;
c=1'b1;
#10
a=1'b1;
b=1'b0;
c=1'b0;
#10
a=1'b1;
b=1'b0;
c=1'b1;
#10
a=1'b1;
b=1'b1;
c=1'b0;
#10
a=1'b1;
b=1'b1;
c=1'b1;
end
initial
begin
$monitor("%t,a=%b,b=%b,c=%b,s=%b,ca=%b",$time,a,b,c,s,ca);
end
Simulation results:
RESULT:
Thus the OUTPUT’s of Full Adders is verified by synthesizing and simulating the
VERILOG code.

Experiment 9: Design of flip flops: SR, D, JK, T
AIM: To develop the source code for flip flops by using VERILOG and Obtained the simulation,
synthesis, place and route and implement into FPGA.
I A. SR FLIPFLOP:
LOGIC DIAGRAM TRUTH TABLE:
Q(t) S R Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 X
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 X
SOURCE CODE:
module srflipflop(s,r,clk,clr,q,qbar);
input s;
input r;
input clk;
input clr;
output q;
output qbar;
reg q,qbar;
always@(posedge(clk) or posedge(clr))
begin
if(clr==1'b1)
begin
q=1'b0;qbar=~q;
end
else if(s==1'b0 && r==1'b0)
begin
q=q; qbar=~q;
end
else if(s==1'b0 && r==1'b1)
begin

q= 1'b0; qbar=~q;
end
else if(s==1'b1 && r==1'b0)
begin
q= 1'b1; qbar=~q;
end
else
begin
q=1'bx;
qbar=1'bx;
end
end
endmodule
TEST BENCH:
module tb_srflipflop();
reg s,r,clk,clr;
wire q,qbar;
srflipflop dut (.s(s),.r(r),.clk(clk),.clr(clr),.q(q),.qbar(qbar));
initial
begin
clk=1'b0;
forever #10 clk=~clk;
end
initial
begin
clr=1'b1;
#20
clr=1'b0;
s=1'b0;
r=1'b0;
#20
s=1'b0;
r=1'b1;
#10
s=1'b1;
r=1'b0;
#20
s=1'b1;
r=1'b1;
#100 $stop;
end
initial
begin
$monitor("%t,s=%b,r=%b,clk=%b,clr=%b,q=%b,qbar=%b",$time,s,r,clk,clr,q,qbar);
end
endmodule

Simulation Results:
RESULT: Thus the OUTPUT’s of Flip Flops are verified by synthesizing and simulating the
VERILOG code
Theory:
Flip-flops are synchronous bitable devices. The term synchronous means the output
changes state only when the clock input is triggered. That is, changes in the output occur
in synchronization with the clock. Lab Manual/CSE 27 A flip-flop circuit has two
outputs, one for the normal value and one for the complement value of the stored bit.
Since memory elements in sequential circuits are usually flip-flops, it is worth
summarizing the behavior of various flip-flop types before proceeding further. All flip-
flops can be divided into four basic types: SR, JK, D and T. They differ in the number of
inputs and in the response invoked by different value of input signals. The four types of
flip-flops are defined in the Table 5.1. Each of these flip-flops can be uniquely described
by its graphical symbol, its characteristic table, its characteristic equation or excitation
table. All flip-flops have output signals Q and Q'
Logic Diagram
D- Flip Flop JK Flip Flop
T Flip Flop

S-R Flip Flop Simulation
Dataflow Modelling Structural Modelling Behavioral Modelling

modulesr_df (s, r, q, q_n); module sr_st(s,r,q,q_n); module
sr_beh(s,r,q,q_n);
input s, r; input s, r; input s, r;
output q, q_n; output q, q_n; output q, q_n;
assignq_n = ~(s | q); or g1(q_n,~s,~q); regq, q_n;
assign q = ~(r | q_n); or g2(q,~r,~q_n); always@(s,r)
endmodule endmodule begin
q,n = ~(s|q);
assign q = ~(r | q_n);
endmodule
D Flip Flop
Behavioral Modelling Dataflow Modelling Structural Modelling
Module dff_async_reset( data, clk, module dff_df(d,c,q,q1); module
reset ,q ); input d,c; dff_df(d,c,q,q1)
input data, clk, reset ; output q,q1; ; input d,c;
output q; assign w1=d&c; output
reg q; assign w2=~d&c; q,q1;
always @ ( posedgeclk or negedge q=~(w1|q1); and
reset) q1=~(w2|q); g1(w1,
if (~reset) begin endmodule d,c);
q <= 1'b0; and g2(w2,~d,c);
end nor g3(q,w1,q1);
else begin nor
q <= data; g4(q1,w
end 2,q);
endmodule endmod
ule

JK Flip Flop
Behavioral Modelling Dataflow Modelling Structural Modelling
module jk(q,q1,j,k,c); module jkflip_df (j,k,q,qn); module

output q,q1; input j,k,q; jkflip_st(j,k,q,qn);
input j,k,c; output qn; wire input j,k,q;
reg q,q1; w1,w2; assign output qn;
initial begin q=1'b0; q1=1'b1; end w1=~q; assign and g1(w1,j,~q);
always @ (posedge c) w2=~k; and g2(w2,~k,q);
begin assign qn=(j & w1 | w2 & q); or
case({j,k}) endmodule g3(qn,w1,
{1'b0,1'b0}:begin w2);
q=q; q1=q1; end endmodul
{1'b0,1'b1}: begin e
q=1'b0; q1=1'b1; end
{1'b1,1'b0}:begin
q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin
q=~q; q1=~q1; end
endcase
end
endmodule
T Flip Flop
Structural Modelling Dataflow Modelling
Behavioral Modelling
module t_beh(q,q1,t,c); module t_st(q,q1,t,c); module t_df(q,q,1,t,c);

output q,q1; output q,q1; output q,q1;
inputt,c; input t,c; input t,c;
reg q,q1; wire w1,w2; and g1(w1,t,c,q);
initial assign w1=t&c&q; and g2(w2,t,c,q1);
begin assign w2=t&c&q1; nor g3(q,w1,q1);
q=1'b1; assign q=~(w1|q1); nor g4(q1,w2,q);
q1=1'b0; assign q1=~(w2|q); endmodule
end endmodule
always @ (c)
begin

EXPT NO: Ripple Counter
Aim: To design a 4 bit Ripple counter using Verilog HDL
Schematic Diagram:
We will supply a 1Khz clock signal to the first T Flip Flop, and the rest of the three Flip Flops
will have their clocks from the output (Q) of the previous Flip Flop. The circuit contains 4 T
Flip Flops because we need 4 bit Ripple Counter. T1 has its clock supplied by a Digital source
of 1Khz, and the rest of Flip Flops used previous Flip Flop output as the clock. Input T of all T
flip flops is HIGH (1) so that T Flip Flop toggles input on every clock edge.
Process: We will design the program in Structural modelling. We will do three modules to
implement this counter. The first module is to implement the main program. The second
module is used to implement T flip flop logic and the third to implement D Flip Flop logic.
Program: Save the file separately as DFF, ripple,
module dff (input d,
input clk,
input rstn,
output reg q,
output qn);
always @ (posedge clk or negedge rstn)
if (!rstn)
q <= 0;
else
q <= d;
assign qn = ~q;
endmodule
module ripple ( input clk,

input rstn,
output [3:0] out);
wire q0;
wire qn0;
wire q1;
wire qn1;

wire q2;
wire qn2;
wire q3;
wire qn3;
dff dff0 ( .d (qn0),

.clk (clk),
.rstn (rstn),
.q (q0),
.qn (qn0));

.clk (q0),
.rstn (rstn),
.q (q1),
.qn (qn1));
.clk (q1),
.rstn (rstn),
.q (q2),
.qn (qn2));
.clk (q2),
.rstn (rstn),
.q (q3),
.qn (qn3));
assign out = {qn3, qn2, qn1, qn0};
endmodule
Simulation Results:
Results:

EXPT NO: Modulus Counter
Aim: To design a MOD 9 Counter using Verilog HDL
Schematic Diagram:
Process: Modulus counter counts till N-1 one values of the count value specified. Suppose we
design a MOD 10 counter, the counter counts from 0 to 9 and resets to 0 and the process
continues.
Program:
module modN_ctr
# (parameter N = 10,
parameter WIDTH = 4)
( input clk,
input rstn,
output reg[WIDTH-1:0] out);
always @ (posedge clk) begin
if (!rstn) begin
out <= 0;
end else begin
if (out == N-1)
out <= 0;
else
out <= out + 1;
end
end
endmodule
Simulation Results:
Results

EXPT NO: FINITE STATE MACHINES
Aim: To Design a Mealy and Moore Machine for an edge detector and to analyze the time
required for simulation.
Mealy and Moore Machine :
 In Moore machine, the outputs depend on states only, therefore it is ‘synchronous machine’ and
the output is available after 1 clock cycle . Whereas, in Mealy machine output depends on states
along with external inputs; and the output is available as soon as the input is changed therefore it
is ‘asynchronous machine’
 Mealy machine requires fewer number of states as compared to Moore machine
 Moore machine should be preferred for the designs, where glitches are not the problem in the
systems.
 Mealy machines are good for synchronous systems which requires ‘delay-free and glitch-free’
system, but careful design is required for asynchronous systems. Therefore, Mealy machine can
be complex as compare to Moore machine.
STATE MACHINE DIAGRAM:
Edge detector design using Moore Machine Edge detector design using Mealy Machine
The state diagrams for Mealy and Moore designs respectively. In the output of the system is set to 1,
whenever the system is in the state ‘zero’ and value of the input signal ‘level’ is 1; i.e. output depends on
both the state and the input. Whereas in second diagram, the output is set to 1 whenever the system is in
the state ‘edge’ i.e. output depends only on the state of the system.

Program:
// edgeDetector.v
// Moore and Mealy Implementation
module edgeDetector
(
input wire clk, reset,
input wire level,
output reg Mealy_tick, Moore_tick
);
localparam // 2 states are required for Mealy

zeroMealy = 1'b0,
oneMealy = 1'b1;
localparam [1:0] // 3 states are required for Moore

zeroMoore = 2'b00,
edgeMoore = 2'b01,
oneMoore = 2'b10;
reg stateMealy_reg, stateMealy_next;

reg[1:0] stateMoore_reg, stateMoore_next;
always @(posedge clk, posedge reset)

begin
if(reset) // go to state zero if rese
begin
stateMealy_reg <= zeroMealy;
stateMoore_reg <= zeroMoore;
end
else // otherwise update the states
begin
stateMealy_reg <= stateMealy_next;
stateMoore_reg <= stateMoore_next;
end
end
// Mealy Design
always @(stateMealy_reg, level)
begin
// store current state as next
stateMealy_next = stateMealy_reg; // required: when no case statement is satisfied
Mealy_tick = 1'b0; // set tick to zero (so that 'tick = 1' is available for 1 cycle only)
case(stateMealy_reg)
zeroMealy: // set 'tick = 1' if state = zero and level = '1'
if(level)
begin // if level is 1, then go to state one,

stateMealy_next = oneMealy; // otherwise remain in same state.
Mealy_tick = 1'b1;
end
oneMealy:
if(~level) // if level is 0, then go to zero state,
stateMealy_next = zeroMealy; // otherwise remain in one state.
endcase
end
// Moore Design
always @(stateMoore_reg, level)
begin
// store current state as next
stateMoore_next = stateMoore_reg; // required: when no case statement is satisfied
Moore_tick = 1'b0; // set tick to zero (so that 'tick = 1' is available for 1 cycle only)
case(stateMoore_reg)
zeroMoore: // if state is zero,
if(level) // and level is 1
stateMoore_next = edgeMoore; // then go to state edge.
edgeMoore:
begin
Moore_tick = 1'b1; // set the tick to 1.
if(level) // if level is 1,
stateMoore_next = oneMoore; // go to state one,
else
stateMoore_next = zeroMoore; // else go to state zero.
end
oneMoore:
if(~level) // if level is 0,
stateMoore_next = zeroMoore; // then go to state zero.
endcase
end
endmodule
Simulation Results:
It can be seen that output-tick of Mealy detector is generated as soon as the ‘level’ goes to 1,
whereas Moore design generate the tick after 1 clock cycle. These two ticks are shown with the
help of the two red cursors in the figure. Since, output of Mealy design is immediately available
therefore it is preferred for synchronous designs.

Results:

Experiment 13: Design Inverter using PMOS/NMOS
AIM: To develop the source code for basic logic gates by using VERILOG in switch level
design and obtain the simulation.
Components used: 1. Xilinix 7.1
LOGIC DIAGRAM:
12. A .NOT GATE
TRUTH TABLE:
A Y=A’
0 1
1 0
SOURCE CODE:
module swinv(in , out);
input in;
output out;
supply1 pwr;
supply0 gnd;
pmos(out,pwr,in);
nmos(out,gnd,in);
endmodule
Simulation output:
12.B.NAND GATE:
LOGIC DIAGRAM:
TRUTH TABLE:
A B Y=(AB)’
0 0 1
0 1 1
1 0 1
1 1 0

SOURCE CODE:
module nand1(a, b, out);

input a;
input b;
output out;
wire c;
supply1 pwr;
supply0 gnd;
pmos(out,pwr,a);
pmos(out,pwr,b);
nmos(c,gnd,b);
nmos(out,c,a);
endmodule
Simulation output:

12. C . AND GATE:
LOGIC DIAGRAM:
TRUTH
TABLE:
A B Y=AB
0 0 0
0 1 0
1 0 0
1 1 1
SOURCE CODE:
module and1(a, b, out);

input a;
input b;
output out;
wire c,z;
supply1 pwr;
supply0 gnd;
pmos(z,pwr,a);
pmos(z,pwr,b);
pmos(out,pwr,z);
nmos(c,gnd,b);
nmos(z,c,a);
nmos(out,gnd,z);
endmodule
Simulation output:

12. D .NOR GATE:
LOGIC DIAGRAM:
TRUTH TABLE:
A B Y=(A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
SOURCE CODE:
module nor1(a, b, out);

input a;
input b;
output out;
wire c;
supply1 pwr;
supply0 gnd;
pmos(c,pwr,b);
pmos(out,c,a);
nmos(out,gnd,a);
nmos(out,gnd,b);
endmodule
Simulation output:

12. E. OR GATE:
A B Y=(A+B)’
0 0 0
0 1 1
1 0 1
1 1 1
SOURCE CODE:
module or1(a, b, out);
input a;
input b;
output out;
wire c,z;
supply1 pwr;
supply0 gnd;
pmos(c,pwr,b);
pmos(z,c,a);
pmos(out,pwr,z);
nmos(z,gnd,a);
nmos(z,gnd,b);
nmos(out,gnd,z);
endmodule
Simulation output:
RESULT:
Thus the OUTPUT’s of switch level design basic logic gates are verified
and simulated using the VERILOG code.

VLSI Lab Manual

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

VLSI Lab Manual

Uploaded by

Copyright:

Available Formats

VIDYA JYOTHI INSTITUTE OF TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

EMBEDDED AND VLSI LABORATORY

Regulations : R 2018 / R2020

Class : III Year II Semester (ECE)

2 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

3 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

1. Code the ARM cortex M0+ processor instruction set.

Perform any 10 Experiments from each lab:

4 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

LIST OF EXPERIMENTS WITH PROGRAM OUTCOMES

5 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

6 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

INSTRUCTIONS TO THE STUDENTS

1. Students are required to attend all labs.

2. Students should work individually in the hardware and software laboratories.

7 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

S. Date List of Experiments Page Remarks

6. Design of 4 bit comparator

8 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

Introduction to Xilinx ISE Software

1. New Project Creation

9 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

10 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

11 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

7. Then proceed to „Next‟ in the “New Project Wizard‟ to „Add Existing

12 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

9. Input your design (verilog code) within the module definition

13 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

14 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

15 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

16 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

SOFTWARE & HARDWARE:

AND GATE: OR GATE:

LOGIC DIAGRAM: TRUTH TABLE: LOGICDIAGRAM TRUTH

NOT GATE: NAND GATE:

NOR GATE: XOR GATE:

18 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

19 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

Synthesis RTL Schematic:

Thus the OUTPUT‟s of all logic gates are verified by synthesizing

20 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

21 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

// Verilog code for AND-OR-INVERT gate

module AOI (F, A, B, C, D);

22 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

SOFTWARE & HARDWARE:

Verilog source code: Structural model

23 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

24 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

SOFTWARE & HARDWARE:

Verilog source code:

module demux18df(in,s0,s1,s2,i0,d1,d2,d3,d 4,d5,d6,d7);

25 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

26 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

Verilog source code:

Module enc83df(d0,d1,d2,d3,d4,d5,d6,d7,q0,q 1,q2);

27 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

Results: Thus the OUTPUT’s of Encoder is verified by synthesizing and simulating

28 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75

LOGIC DIAGRAM & TRUTH TABLE:

LOGIC DIAGRAM: TRUTH TABLE:

module comparator(a, b, x, y, z);

29 DEPT of ECE, VIDYA JYOTHI INSTITUTE OF TECHNOLOGY, AZIZ NAGAR, HYDERABAD-75