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This paper formulates and solves some long-standing In contrast to the classical information theory (only
fundamental and applied problems in design, analysis, and two logic gates result for a single bit, e.g., identity and
optimization of nanocomputers. The fundamentals of NOT), there are an infmite number of single-qubit
nanocomputer architectronics are reported, and the basic
quantum gates (e.g., A = ( O ) + \ l ) ~ l+(io)
I -1l)~OI) due to
organizations and topologies are examined progressing
from the general system-level consideration to the the quantum superposition. The possible unitary operators
nanocomputer subsystem/unit/device-level study. for a pair of qubits are expressed as
NanoICs are examined using nanoscale field-effect lo)(ol @I+Il)(11@ U ,
transistors (NFET). where I and U are the single-qubit identity and controlled
gate.
Let a qubit evolves as lO)+lo) and ll)+eimll). For the state, we have I (t)) = e!(')l-( I ) ) such that
Then, the phase quantum logic gate is the phase change of the initial state I (0)) is given as
0 = f ( r )- f(0) '
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Tuesday. August 27. 2002 IEEE-NAN0 ZOO2
TA!% Ouantum mmputing
h, 0
III. NANOCOMPUTERARCHITECTURE AND
A single qubit density matrix is parameterized as NANACOMPUTERARCHITECTRONICS
p =+(I + s . 0 )= + s,l+s,
+is,
s, --Isy
1-s,
The critical problems in the design of nanocomputers
are focused on devising, designing, analyzing, optimizing
1"l
and fully utilizing hardware and software. The current ICs
where s is the Bloch vector, = sy . are very large scale integration circuits (VLSI). Though 90
nm fabrication technologies have been developed and
1s. J implemented by the leading computer manufacturers
Using the Rabi vector a, we have (Dell, IBM, Intel, Hewlett-Packard, Motorola, Sun
Microsystems, Texas Instruments, etc.), and billions of
H=+A(Q,I+Q.cT). transistors can be placed on a single multilayered die, the
VLSI technology approaches the physical limits.
Thus,
iA-dP = [ H , p ] , Alternative affordable, high-yield and robust
technologies are sought, and nanotechnology promises
dt further far-reaching revolutionary progress. It is
and
ds
- = ~ x s . envisioned that nanotechnology will lead to three-
dt dimensional nanocomputers with novel computer
architectures to attain the superior overall performance
The Hamiltonian is exuressed as level. Compared with the existing most advanced
computers, in nanocomputers the execution time,
switching frequency and size will be decreased by the
order of millions, while the memory capacity will be
increased by the order of millions. However, significant
challenges must be overcome. Many difficult problems
such as
The two-spin Hamiltonian with two noninteractive 1. novel nanocomputer architectures,
half-spin particles S, and S, is 2. advanced organizations and topologies,
Hu = AoJ, @Ib+AobIa @Sbz. 3. high-fidelity modeling,
4. data-intensive analysis,
5 . heterogeneous simulations,
6. optimization,
7. control, adaptation and reconfiguration,
8. self-organization,
9. robustness,
0 o,-oa 0 IO. utilization,
H, =fh
l o 0 -o,+oa O
0 I as well as other problems must be addressed, researched
and solved. Many of the above mentioned problems have
not been even addressed yet.
For interactive system,
311
A nanocomputer architecture integrates the following
major systems: input - output, memory, arithmetic and
logic, and control units. The input unit accepts information
from electronic devices or other computers through the
cards (electromechanical devices, such as keyboards, can
he also interfaced). The information received can be stored
in the memory, and then, manipulated and processed by
the arithmetic and logic unit (ALU). The results are output
using the output unit. Information flow, propagation,
manipulation, processing, and storage are coordinated by
the control unit. The arithmetic and logic unit, integrated
with control unit, is called the processor or central
processing unit (CPU). Input and output systems are called
the input-output unit (U0 unit). The memory unit, which
integrates memory systems, stores programs and data.
There are two main classes of memory calledprimary Figure 2. Nanocomputer organization
(main) and secondary memory. In nanocomputers, the
primary memory is implemented using nanoICs that can
consist of billions of nanoscale storage cells (each cell can IV. NANOCOMPUTERS
AND NANOICS
store one bit of information). These cells are accessed in PERFORMANCE
groups of fixed size called words. The main memory is
organized such that the contents of one word can be stored Current computers constantly irreversibly erase
or rehieved in one hasic operation called a memory cycle. temporary results, and thus, the entropy changes. The
To provide a consistent direct access to any word in the average instruction execution speed (in millions of
main memory in the shortest time, a distinct address instructions executed per second Ips) and cycles per
number is associated with each word location. instruction are related to the time required to execute
instructions as given by
NanoICs can he effectively used to implement the
additional memory systems to store programs and data Ti*s,=lK.lnck,
forming secondary memory. where the clock frequencyf,,oct depends mainly on the ICs
or nanoICs used and the fabrication technologies applied.
The execution of most operations is performed by the
ALU. In the ALU, the logic nanogates and nanoregisters Tbe quantum mechanics implies an upper limit on the
used to perform the hasic operations (addition, subtraction, frequency at which the system can switch from one state
multiplication, and division) of numeric operands, and the to another. This limit is found as the difference between
comparison, shifting, and alignment operations of general the total energy E of the system and ground state energy
forms of numeric and nonnumeric data. The processors EO,e.g.,
contain a number of high-speed registers. which are used 4
for temporruy storage of operands. Register, as a storage f , 2 -(E - E o ) ,
h
..
device for words, is a key sequential component, and
where h is the Planck constant, h=6.626~10"~J-sec or
registers are connected. Each register contains one word of
data and its access time at least 10 times faster than the J/HZ.
main memory access time. A register-level system
An isolated nanodevice, consisting of a single
consists of a set of registers connected by combinational
data-processing and data-processing nanoICs. electron at a potential of IV above its ground state,
contains 1 eV of energy (leV=1.602~10-~~ J) and,
Figure 2 illustrates the possible nanocomputer therefore, cannot change its state faster than
organization, and, in general, three-dimensional
nanocomuputer architectronics must he examined using 4
f , <-@-E )- 1 . 6 0 2 ~ 1 0 -=' ~I X I O ' ~ Hz.
the major units reported. h U -6.626~10~"
312
Hence, the switching frequency is 1 ~ 1 0 ' Hz. ~ In general, nanoICs ensure high density, superior
Correspondingly, the switching frequency of nanoICs can bandwidth, high switching frequency, low power, et cetera
be significantly increased compared with 'the currently [7-lo]. It is envisioned that in the near future
used CMOS ICs. nanocomputers will allow one to increase the computing
speed by a factor of millions compared with the existing
In asymptotically reversible nanocomputers, the CMOS. Three-dimensional multiple-layered high-density
generated entropy is nanoIC assemblies, shown in Figure 3, are envisioned to
be used
S=b/f,
where b is the entropy coefficient ( b varies from 1x10' to
1x106 hits/GHz for ICs, and from 1 to IO bitslGHz for
quantum FETs): f is the length of time over which the
operation is performed.
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