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DIGITAL ELECTRONICS

7 ADC & DAC

1. INTRODUCTION

Because of many advantages, digital systems are widely used for control, communication,
computers, instrumentation, etc. In many such applications of digital systems, the signals are
not available in the digital form.
An along voltage to be processed using digital techniques may be a fixed (dc) voltage or a time
varying voltage v(t). The process of converting an analog signal to a digital form involves a
sequence of four processes. These are
• Sampling
• Holding
• Quantizing
• Encoding
These processes are not performed as separate operations. Sampling and holding operations
are done simultaneously using a circuit known as sample and hold (S/H) circuit. These
operations are required to be performed for the conversion of time varying analog signals and
not for dc signals. Quantizing and encoding processes are done simultaneously using a circuit
referred to as an analog to digital converter (A/D converter or ADC). The process of conversion
of an analog signal to digital signal is referred to as an analog to digital conversion.
The output of the system may be required to be in the analog form and, therefore, the digital
output has to be converted back to the analog form. The process is referred to as a digital to
analog conversion and the system is used for this purpose is referred to as a digital to analog
converter (D/A converter or DAC).
There are following some examples where A/D and D/A converters are used:
i. A digital system can be used to monitor the ambient temperature of an oven and if it
exceeds a certain limit, it should reduce the fuel input. Here, an A/D converter is required
to convert the output of the sensor (which converts temperature to an analog electrical
signal) to digital form. If the temperature exceeds the simplified limit, some digital output
is produced which is to be converted to analog form in order to control the device which
reduces the fuel input.

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ii. A digital voltmeter is used to measure an analog voltage and display the voltage in
numerical form. In this, an A/D converter is required to convert the analog voltage into
a digital signal. The required processing consists of determining its value. The output, in
this case, is not required to be converted back to the analog form and hence a D/A
converter is not needed.
iii. A digital communication system is used to transmit messages which are in the form of
analog electrical signals. This requires an A/D converter at the transmitting end and a
D/A converter at the receiving end.
iv. In microprocessor-based process control system, A/D and D/A converters are often used
and are referred to as peripherals or I/O devices.
Since D/A converters are used as sub-systems in many A/D converters, D/A converters
will be discussed first.

2. DIGITAL TO ANALOG CONVERTER (DAC)

Digital to Analog conversion is the process of converting a value represented in digital code,
such as straight binary or BCD, into a voltage or current which is proportional to the digital
value. Figure 1 shows a block diagram of a 3-bit DAC. It has three input lines D2, D1 and D0,
and one output line which provides the analog signal.

Figure 1: Block Diagram of 3-bit DAC

A 3-bit digital signal has eight combinations. From 000 to 111. The output analog voltage level
is a function of the input combinations of 0 and 1; it is minimum for 000 and maximum for
111. Let us assume the output analog signal is in the range of 0 to 7 V and the input
combinations are 000 to 111. Then its equivalent analog can be represented in table 1.
Table 1

Digital signal Analog signal

000 0 Volts
001 1/8 Volts
010 2/4 Volts
011 3/8 Volts
100 4/8 Volts
101 5/8 Volts
110 6/8 Volts
111 7/8 Volts

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3. PARAMETERS OF D/A CONVERTER

The performance or characteristics of a D/A converter, is measured based on the following

parameters:
i. Resolution
ii. Accuracy
iii. Offset/ Zero scale error
iv. Linearity
v. Settling time
vi. Temperature sensitivity
These are discussed below:
3.1. Resolution:
The resolution of D/A converter refers to the smallest change in the analog output
voltage. It is equivalent to the value of the least significant bit (LSB). For a N–bit D/A
converter, maximum number of steps is 2 N – 1. When the reference voltage is V, the
Least significant Bit (LSB) value is

Re ference Voltage V
Resolution = = N
Number of steps 2 −1
Resolution can be expressed as

Step size
% Resolution = 100%
Full scale
3.2. Accuracy:
The output voltage of D/A converter is different from ideal case. Therefore, there is always
some error. The accuracy is measured from the difference between actual output voltage
and voltage for ideal case. Usually, it is specified in terms of its full–scale error and
linearity error, which are normally expressed as a percentage of the converter’s full –
scale output.
3.3. Offset/zero scale error:
Ideally, the output of a DAC should be zero when the binary input is zero. In practice,
however, there is a very small output voltage under this situation called the offset voltage.
3.4. Linearity:
In a D/A converter, equal increments in the numerical significance of the digital input
should result in equal increments in the analog output voltage. In an actual circuit, the
input-output relationship is not linear. This is due to the error in the resistor values and
voltage across the switches. The linearity of a converter is a measure of the precision
with which the linear input-output relationship is satisfied.

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3.5. Settling Time:
When the digital input to a D/A converter changes, the analog output voltage does not
change abruptly. Because of the presence of switches, active devices, stray capacitance,
and inductance associated with the passive circuit components, the transients appear in
the output voltage and oscillations may also occur. The time require for analog output to
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settle to within ± LSB of the final value after a change in the digital input is usually
2

specified by the manufactures and is referred to as settling time. This imposes a limit on
the frequency at which the digital input can change. If it is operated at too high a
frequency, it may not have time to settle to the correct output voltage before being
switched on to the next digital input.
3.6. Temperature Sensitivity
The analog output voltage for any fixed digital input varies with temperature. This is due
to the temperature sensitivity of the reference voltage source, resistor, OP AMP, etc. It is
specified as ± ppm/oC.
Example 1:
The full-scale output of a 8-bit DAC is 10 V. Find the resolution for this digital to analog
converter.
Solution:
For 8-bit DAC, we have
n=8
and full scale output is
Vfs = 10 V
So, we get
Number of steps = 2n – 1
= 28 – 1
= 255
Hence resolution or step size is
Vfs
Resolution =
No of steps

10
= = 0.0392V
255
= 39.2 m V
Example 2
A digital to analog converter has 8V full scale output voltage and on accuracy of ± 0.2%.
The maximum error for any output voltage will be …………. mV.

Solution:
Given that full scale output voltage is

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Vfs = 8V
And accuracy = ± 0.2%
The accuracy is defined with respect to full scale output as
Error
%accuracy =  100
Vfs
Error
0.2 =  100
8V
0.2  8V
Error =
100
= 16 mV
Example 3
A 5 bit D/A converter produce Vout = 0.2 V for a digital input of 0001. Find the value of
Vout for an input of 11111.
Solution:
Output Voltage = 0.2 V for input 0001
Decimal count of input code 0001 = 1
Output Voltage = step size × decimal count
Output voltage 0.2
Step size = =
decimal count 1

= 0.2
Now input code is 11111 (decimal ‘31’)
Therefore Vout = step size × decimal count
= 0.2 × 31
= 6.2 V
Example 4
A certain 8-bit DAC has a full-scale output of 2mA and a full-scale error of ± 0.5 % F.S.
What is the range of possible outputs for an input of 1000 0000?
Solution:
Given, Full scale output = 2mA
For 8-bit DAC, n = 8
Input = (1000 0000)2 = (128)10
2mA 2mA
Step size = = = 7.84A
28 − 1 255
Ideal Output is 128 × 7.84 μA
≈ 1004 μA
The error can be as much as
±0.5% × 2 mA = ± 10μA
Thus, the actual output can deviate by this amount from the ideal 1004 μA, so the actual
output can be anywhere from 994 to 1014 μA.
Example 5
A 10 bit DAC has a step size of 10 mV. Determine the full scale output voltage and the

percentage resolution.

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Solution:

With 10 bits, there will be 210 – 1 = 1023 steps of 10 mV each.

The full scale output will therefore 10 m V × 1023

= 10.23 V

10mV
And percentage resolution =  100%
10.23V

0.1%

4. DAC CIRCUITS

The Two types of DAC circuits are described in following sections.

4.1. Weighted Resistor Type DAC:

The diagram of the weighted resistor DAC shown in figure 2(a). The operational amplifier

is used to produce a weighted sum of the digital inputs, where the weights are

proportional to the weights of the bit positions of inputs. Since, the op-amp is connected

as an inverting amplifier, each input is amplified by a factor equal to the ratio of the

feedback resistance divided by the input resistance to which it is connected. The MSB D 3

is amplified by Rf / R, D2 is amplified by Rf/2R, D1 is amplified by Rf/4R, and D0, the LSB

is amplified by Rf/8R.

Figure 2(a): Weighted-Resistor Type DAC

The inverting terminal of the op–amp acts as a virtual ground. Since the op–amp adds

and inverts,

 D D D  R 
Vout = −  D3 + 2 + 1 + 0    f 
 2 4 8   R 

Analysis:
Let us assume an N-bit straight binary input to a resistor network (through digitally
controlled electronic switches) which produces a current I corresponding to logic 1 at the
most-significant bit, I/2 corresponding to logic 1 at the next lower bit, I/2 2 for logic 1 at
the next lower bit and so on, and I/2N–1 for logic 1 at the least-significant bit position. The
total current thus produced will be proportional to the digital input. This current can be

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converted into a corresponding voltage, by using an OP AMP, which will be proportional
to the digital input.
The circuit of figure 2(b) can be used for converting the digital input to analog output
which operates according to the above principle. This circuit is referred to as a weighted-
resistor D/A converter since the resistance values are weighted in accordance with the
binary weights.
In the circuit 2(b), the digital inputs (1 or 0) operate the switches. A switch is thrown to
position 1 or 0 for a digital input corresponding to that bit being 1 or 0, respectively. The
voltage applied to a resistor is V(1) if the switch connected to it is in position 1 and V(0)
if it is in position 0. The current, Ii is given by
Ii = IN – 1 + IN – 2 + IN – 3 + …+ I2 + I1 + I0
Where,
IN−1 = VN–1 /R 

IN−2 = VN–2 /2R 
 where Vn = V(1) if bn = 1
IN−3 = VN–3 / 22R 
 = V(0) if bn=0

I0 = V0 /2N–1R 

Figure 2(b): Weighted- Resistor D/A Converter

For straight binary input, V(0) = 0 and V(1) = –VR, and the output voltage V0 is given by
R R R R 
V0 = −(−VR )  F bN−1 + F bN−2 + 2F bN−3 + ... + N−F1 b0 
 R 2R 2 R 2 R 

Which is of the same form as equation

(
V0 = K 2N−1bN−1 + 2N−2bN−2 + 2N−3bN−3 + ... + 22b2 + 21b1 + b0 )
RF
with K= .VR
2N−1R

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The output swings in only one direction and therefore is unipolar. If it is required to
convert digital data in bipolar format such as in sign-magnitude, 1’s complement or 2’s
complement format, then V(0) ≠ 0. In such cases, V(0) is used to offset the output swing.
With V(1) and V(0) as the voltages applied to the resistor network for 1 and 0,
respectively, the output voltage V0 of figure 2(b) is given by
RF
V0 = N−1
(2N−1 VN−1 + 2N−2 VN−2 + ... + 21 V1 + 20 V0 )
2 R

An offset can also be produced in the output voltage V 0 by using the circuit of figure 2(c).
The offset voltage produced in this circuit is
RF
− .V
R off off

Figure 2(c): Circuit used to Offset the output voltage

(NOTE:
The DAC circuits we have looked at, has some practical limitations. The biggest problem
is the large difference in resistor values between the LSB and MSB, especially in high-
resolution DACs.)
4.2. R–2R Ladder Type DAC:
There are several methods and circuits for producing the D/A operation. We shall examine
several of the basic schemes, to gain an insight into the ideas used.
One of the most widely used DAC circuits that uses resistance’s fairly close in value is the
R/2R ladder network. Here the resistance values span a range of only 2 to 1. Here,
resistors are arranged in such a manner that only two different values are used, R and
2R.

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Figure 3: R-2R Ladder type DAC

Figure 3 shows R-2R ladder network which has only two resistor values, i.e. R and 2R.
VD2, VD1, VD0 are the 3-bit digital inputs voltage levels and Vout is the analog output.
Example 6
The DAC shown in figure below has step size 0.5 V. Find the value of feedback resistance
RF.

Figure 4
Solution:
For weight-resistor type DAC, the LSB is amplified by RF/8k. The step size is equivalent
to output voltage corresponding to LSB input. So, we get
RF
Step − size =  5 = 0.5
8K
Or, RF = 800 KΩ
Example 7
The circuit of DAC is given below. Switch are closed if input bit is 1, otherwise open.
(i) If Vref = 5 V, R = 20 kΩ, and RF = 10 kΩ, find the full scale voltage.
(ii) If full scale voltage is to be Vout = -2 V, then value of RF would be

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Figure 5
Solution:
(i) The step size is equivalent to output voltage corresponding to LSB input, and given by
 −R 
Step size =  F  Vref
 8R 

−10k
=  5V = −0.3125V
8  20k
Full scale voltage is equivalent to corresponding output voltage when all input bits are
high, So, we obtain the output for the input (1111) 2 = 1510 as
Full scale output Voltage = - 0.3125 V × 15
= -4.6875 V
(ii) The full scale output voltage is given by
−Rf
Vo =  Vref  15
8R
Here, R and Vref are constant, and Rf changes for both case, i.e.
V0 directly proportional to Rf
V01 Rf1
Or = ………………(i)
V02 Rf 2

We have,
V01 = - 4.6875 V for Rf1 = 10 k Ω
V02 = - 2 V for Rf2 = ?
Hence, substituting the values in question (1), we obtain
−4.6875 10k
=
−2 Rf 2

10k  2
Or, Rf 2 = = 4.27k
4.6875
Example 8
Consider the circuit shown below which is a 4-bit DAC.

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Figure 6
The input bits 0 and 1 are represented by 0 and 5 V respectively. The Op-amp is ideal,
but all the resistances and the 5V inputs have a tolerance of ± 10 %. The specification
(rounded to the nearest multiple of 5%) for the tolerance of the DAC is……………%.
Solution:
For the given 4-bit DAC, the output voltage is
R R R R 
Vout = Vi  b 0 + b1 + b2 + b3
R 2R 4R 8R 

So, we have the full scale output

 1 1 1
Vout ( Exact ) = −5 1 + + + 
 2 4 8
= −9.375V

For maximum output, we consider +10% tolerance for numerator values and -10%
tolerance for denominator values. So, we have

110 110 110 110 

Vout ( max ) = −5.5  + + + 
 90 2  90 4  90 8  90 
= −12.604

Therefore, the tolerance of the DAC is obtained as

Maxoutput − Exact output

%tolerance =  100
Exact output

−12.604 − ( −9.375)
=  100
( −9.375)
= 34.44 % rounded to 35%

Example 9

A 3-bit resistance ladder D/A (R-2R network) has resistor value of R = 10 kΩ and 20 kΩ

if Vref = 8V, Rf = 20 k Ω, then I0 for a digital input of 111 will be ……… mA.

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Solution:

A 3-bit R-2R ladder D/A converter is shown below:

Figure 7

The output voltage V0 is given by

R f  b2 b1 b0 
V0 = Vref + +
R  21 22 23 

Vref Rf
=
2 3

R
(b 2
2
2
+ b1 21 + b0 20 )

8V 20k
=   ( 7) = 14V
23 10k

Hence, the output current I0 is given by

V0 14V
I0 = = = 0.7mA
Rf 20k

5. ANALOG TO DIGITAL CONVERTER (ADC)

An analog-to-digital converter takes an analog input voltage and after a certain amount of time

produces a digital output code which represents the analog input. The A/D conversion process

is generally more complex and time-consuming than the D/A process. The techniques that are

used provide and insight into what factors determine an ADCs performance.

Figure 8: Block diagram of an ADC

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An analog to digital converter (A/D converter or ADC) produces a digital output that is

proportional to the value of the input analog signal. The ADC process includes sampling of input

analog signal and then, each sample is converted into its binary equivalent.

5.1. Sample and hold circuit:

The sample and hold circuit captures the sample after a fixed delay. The sample and hold

circuit captures the sample and holds it as shown in figure 9. The fixed delay T = 1 / f s ,

where fs is a sampling frequency.

Figure 9: Hold Discrete Signal

A sample and hold circuit is shown in figure 10. In this circuit, the voltage across the

capacitor follows the input signal voltage V i when the switch S is closed. The capacitor

holds the instantaneous value of the signal voltage attained just before the switch is

opened.

Figure 10: Sample and Hold Circuit

(NOTE: As per the sampling theorem the sampling frequency should be greater than or
equal to twice the band limited frequency of the signal.)
5.2. Quantization and Encoding
In an ADC, the input analog voltage can have any value in a range, and it is a function of
time, but the digital output can have only 2 N discrete values for an N – bit ADC. Therefore,

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the whole range of analog voltage is required to be represented suitably in 2 N intervals.
This process is known as quantization. Each interval is then assigned a unique N – bit
binary code, which is referred to as encoding.
If we are considering the analog voltage ranges from 0 to 7 V and a 3-bit digital output.
The interval of the analog voltage and their corresponding digital values assigned are
given in table 2. These levels are known as the quantization level.
Table 2: Analog voltages and their corresponding digital values

Analog voltage Digital value

0 Volts 000
1/8 Volts 001
2/8 Volts 010
3/8 Volts 011
4/8 Volts 100
5/8 Volts 101
6/8 Volts 110
7/8 Volts 111

6. PARAMETERS OF ADC

Following are some important parameters of ADC:

i. Range of Input Voltages
ii. Input Impedance
iii. Accuracy
iv. Conversion Time
v. Resolution
vi. Gain and offset errors
vii. Quantization Error
These are discussed as below.
6.1. Range of input voltages:
The range of the input voltage is defined by the maximum and minimum amplitude of an
analog signal, which can be applied to the ADC for reliable operation.
6.2. Input Impedance:
ADC is mainly used to interface the analog circuit with a digital system. To avoid the
problem of loading, the output impedance of analog circuit should be matched with the
input impedance of an ADC and hence, it is required to specify the input impedance of an
ADC.
6.3. Accuracy:
The accuracy specification describes the maximum sum of all the errors, both from
analogue sources (mainly the comparator and the ladder resistors) and from the digital
sources (quantization error) of the A/D converter.

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6.4. Conversion Time:
It is the time required to convert the analog data into its digital equivalent. Conversion
time is in milliseconds. It should be as minimum as possible.
6.5. Resolution:
It is defined as the voltage input change necessary for a 1 – bit change in out. Resolution
in terms of voltage is the full – scale input voltage divided by the total number of levels.
The resolution of an n – bit ADC is given as
V
Resolution =
( 2n − 1)
6.6. Gain and Offset Errors:
The gain error is the difference between the actual full-scale transition voltage and the
ideal full – scale transition voltage. It is expressed either as percentage of the full-scale
range (% of FSR) or in LSB’s.

6.7. Quantization Error:

An A/D converter having an n-bit output can only identify 2n output codes while there are
an infinite number of analogue input values adjacent to the LSB of the A/D converter that
are assigned the same output code. The ± ½ LSB limit to resolution is known as the
fundamental quantization error.
Example 10
Find the resolution of 4-bit analog to digital converter in percentage.
Solution:
The % resolution is given by
1
%resolution =  100
2n − 1
Where n is the number of bits. In given problem, we have
n=4
Hence, the percentage resolution is
1
%resolution =  100
24 − 1
= 6.67%
Example 11
An n bit A/D converter is required to convert an analog input in the range of 0 – 5 V to
an accuracy of 10 mV. Find the value of n.
Solution:
The resolution is given by
VFS
Resolution = = 10mV
2 −1
n

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5V
Or, = 10mV
2 −1
n

Or, 2n – 1 = 500
Or, 2n = 500
Or, n > 8
So, the required number of bits is 9.
Example 12
Consider an ADC having following characteristics
Resolution: 12-bits
Full scale errors: 0.03%
Full scale output: +5V
(i) Find the quantization error.
(ii) Find the total possible error.

Solution:
(i) The percentage resolution is given by
1
% Resolution =  100
2 −1
n

In the given problem, the number of bits is

n = 12
So, the percentage resolution is
1
% Resolution =  100 = 0.024%
212 − 1
Thus, we have the quantization error as
Quantization error = 0.024% × 5V
= 1.2 mV
(ii) The error due to 0.03% in accuracy is
Error = 0.03% × 5V
= 1.5 mV
We have obtained the quantization error as
Quantization error = 1.2 Mv
Hence, the total error is
Total error = 1.2 mV + 1.5 mV
= 2.7 mV

7. ADC CIRCUITS

The two types of ADC circuits are described in following sections.

7.1. Flash Type A/D Converter:
The flash type A/D converter is based on comparing an unknown analog input voltage
with a set of reference voltages. The block diagram of a 2-bit flash type A/D converter is
shown in figure 11.

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Figure 11: Flash Type A/D Converter

As shown in figure, here three op-amps are used as comparators. The non-inverting
inputs of all the three comparators are connected to the analog inputs voltage. The
inverting input terminal of the op–amps are connected to a set of reference voltages V/4,
2V/4 and 3V/4 respectively, which are obtained using a resistive divider network and
power supply +V. Table 3 shows the comparator outputs for different ranges of analog
voltage and their corresponding digital outputs.
Table 3: Comparator and digital outputs for a 2–bit Flash type A/D converter

Comparator Outputs Digital Outputs

Analog input voltage (Vi)
C1 C2 C3 b2 b1

0 < Vi < V/4 0 0 0 0 0

V/4 < Vi < V/2 1 0 0 0 1

V/2 < Vi < 3 V/4 1 1 0 1 0

3 V/4 < Vi < V 1 1 1 1 1

7.2. Counting A/D Converter:

It is a high-resolution ADC that uses a comparator with variable reference voltage. The
block diagram of a 4-bit counter type ADC is shown in figure 12.

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Figure 12: Counting A/D converter

The block diagram consists of a DAC, a comparator, an AND gate, and a binary counter.
The DAC converts the digital data into analog signal, which is given as one of the input
to the comparator. The output of DAC increases with time and the analog output voltage
waveform is a raising staircase, as shown in figure 13.

Figure 13: Analog Output voltage waveform of DAC

The comparator compares this analog voltage with the analog input voltage V A. When VA
< Vr, the output of comparator is high, enable the AND gate to pass the clock. When VA
> Vr, the output of comparator is low, disable the AND gate to pass the clock. The binary
counter stops counting, and the digital output of DAC represents the analog input voltage.
Analysis
If we are considering an analog input as 13/16 V and the ADC is a 4-bit counter type
ADC. We get the counter type conversion sequence as shown in table 4. In this ADC, the
counter advances by one count for every clock pulse, therefore the clock speed decides
the conversion speed.

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Table 4: Counter Type Conversion Sequence

Clock Digital Signal Vr VA Description

1 0000 0 13/16 VA < Vr Enable the AND gate to pass the clock
2 0001 1/16 13/16 VA < Vr Enable the AND gate to pass the clock
3 0010 2/16 13/16 VA < Vr Enable the AND gate to pass the clock
4 0011 3/16 13/16 VA < Vr Enable the AND gate to pass the clock
5 0100 4/16 13/16 VA < Vr Enable the AND gate to pass the clock
6 0101 5/16 13/16 VA < Vr Enable the AND gate to pass the clock
7 0110 6/16 13/16 VA < Vr Enable the AND gate to pass the clock
8 0111 7/16 13/16 VA < Vr Enable the AND gate to pass the clock
9 1000 8/16 13/16 VA < Vr Enable the AND gate to pass the clock
10 1001 9/16 13/16 VA < Vr Enable the AND gate to pass the clock
11 1010 10/16 13/16 VA < Vr Enable the AND gate to pass the clock
12 1011 11/16 13/16 VA < Vr Enable the AND gate to pass the clock
13 1100 12/16 13/16 VA < Vr Enable the AND gate to pass the clock
14 1101 13/16 13/16 VA = Vr Disable the AND gate to pass the clock

Conversion Time:
The conversion time is variable, and it is proportional to the amplitude of the analog input
voltage. The average conversion time of an n – bit ADC is

2n 1 1
TC =  = 2n −1 
2 f clock f clock
where fclock is the frequency of clock cycle.
NOTE: In counting A/D conversion process, the counter is reset for each discrete sample,
Therefore, it takes a long conversion time.
7.3. Dual Slope Type A/D Converter:
A dual-slope ADC is shown in figure 14(a). It uses an operational amplifier to integrate
the analog input.

Figure 14(a): Dual Slop ADC

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The output of the integrator is a ramp, whose slope is proportional to the input signal E in,
since the components R and C are fixed. If the ramp is allowed to continue for a fixed
time, the voltage it reaches in that time, depends on the slope of the ramp and, therefore,
on the value of Ein. The basic principle of the integrating ADC is that, the voltage reached
by the ramp controls the length of time that the binary counter is allowed to count. Thus,
a binary number proportional to the value of Ein is obtained. In the dual – slope ADC, two
integrations are performed.
Analysis:
The block diagram of a dual-slope A/D converter is shown in figure 14(b). It has four
major blocks:
i. An integrator,
ii. A comparator,
iii. A binary counter, and
iv. A switch driver.

Figure 14(b): Dual-Slope A/D Converter

The conversion process begins at t = 0 with the switch S 1 in position 0 thereby connecting
the analog voltage Va to the input of the integrator. The integrator output
t
0 = −1 /  Vadt = − ( Va /  )t .
0

This results in HIGH VC, thus enabling the AND gate and the clock pulses reach the clock
(CK) input terminal of counter which was initially clear. The counter counts from 00 ...

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00 to 111 ... 11 when 2N – 1 clock pulses are applied. At the next clock pulse 2 N, the
counter is cleared and Q becomes 1. This controls the state of S 1 which now moves to
position 1 at T1, thereby connecting – VR to the input of the integrator. The output of the
integrator now starts to move in the positive direction. The counter continues to count
until v0< 0. As soon as ν0 goes Positive at T2, VC goes LOW disabling the AND gate. The
counter will stop counting in the absence of the clock pulses. The waveforms of voltages
ν0 and VC are shown in figure 14(c).

Figure 14(c): Waveforms of Dual-Slope A/D Converters

The time T1 is given by:
T1 = 2NTC
Where Tc is the time period of the clock pulses. When the switch S 1 is in position 1, the
output voltage of the integrator is given by
Va V
0 = − T + R ( t − T1 )
 1 
ν0 = 0 at t = T2
Therefore,
Va V
T2 − T1 = T1 = a 2N TC
VR vR
Let the count recorded in the counter be n at T2. Therefore,
Va N
T2 − T1 = n  TC = 2 TC
VR
Which gives
Va N
n= 2
VR
This shows that the output of the counter is proportional to the analog voltage V a. The
count recorded in the counter is numerically equal to analog voltage V a if VR = 2N.

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This type of A/D converter is often used in digital voltmeters because of its good
conversion accuracy and low cost. The disadvantage of the dual-slope A/D converters is
its slow speed.
7.4. Successive Approximation Type ADC:
The basic principle of successive approximation type A/D converter is that the unknown
analog input voltage is approximated against an n–bit digital value by trying one bit at a
time, beginning with the MSB.
The principle of successive approximation processes for a 4-bit conversion is shown in
figure 15. This type of A/D converter operates by
Successively dividing the voltage range by half, as explained in the following steps.
i. The MSB is initially set to 1 with the remaining three bits set as 0.
The digital equivalent is compared with the unknows analog input voltage.
ii. If the analog input voltage is higher that the digital equivalent, the MSB is retained
as 1 and the second MSB is set to 1. Otherwise, the MSB is reset to 0 and the second
MSB is set to 1.
iii. Comparison is made as given in step 1 to decide whether to retain or reset the second
MSB. The third MSB is set to 1 and the operation is repeated down to LSB and by this
time, the converted digital, value is available in the successive approximation register
(SAR).

Figure 15: Successive Approximation Principle for 4-bit Digital Output

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Example 13
An 8-bit digital-ramp ADC with a 40 mV resolution uses a clock frequency of 2.5 MHz and
a comparator with VT = 1mV.Find the digital output for VA = 6.000 V.
Solution:
For 8-bit ADC, we have
n=8
Resolution = 40 mV
Comparator threshold, VT = 1mV
So, digital output and analog input for the circuit is related as
Or, (Digital value) × resolution > VA + VT
Or, (Digital value) × 40 mV > 6.000 V + 1 mV
6001mV
Or, (Digital value)  = (150.025)10
40mV
Or, 15110 = 100101112

NOTE :
In digital ramp ADC, we compare analog input with DAC output V AX until VAX reaches a
step that exceeds VA by an amount VT or greater than VT.
Example 14
A 10-bit A/D converter is used to digitise an analog signal in the 0 to 5 V range. The
maximum peak to peak ripple voltage that can be allowed in the D.C. supply voltage is
nearly equal to………..
Solution:
The smallest change in the output is one step size, given as
5V
Step size = 5mV
210 − 1
If peak to peak ripple is equal or less than step size, then it is allowed without error in
output. Hence, the maximum peak to peak ripple voltage that can be allowed in the D.C.
supply voltage is nearly equal to 5 mV.
Example 15
A dual-slope A/D converter has a resolution of 4 bits. If the clock rate is 3.2 kHz. Find the
maximum rate at which samples can be converted
Solution:
For a dual-slope converter, we have
Number of bits, n = 4
Clock rate = 3.2 kHz
The conversion time for n-bit is given by
Va n
t = 2n Tc + 2 Tc ………………(ii)
VR

Where n → number of bits

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Tc → Time period of clock pulse
Va → analog voltage
VR → reference voltage
The maximum analog voltage is given as
(Va)max = VR
So, equation (ii) becomes
t = 2n Tc + 1 × 2n × Tc = 2n+1 Tc
1
Or t = 24 +1 sec
3.2  103
Hence, the sampling frequency is given as
1 3.2  103
f =
t 25
Or f  100Hz

i.e. the maximum clock rate is f = 100 Hz = 100/sec

Example 16
Consider the following ADC that has a resolution of 10 mV/step. A fixed voltage of +5 mV
is added to the D/A output in the summing amplifier, and the result, VAY is fed to the
comparator, which has VT = 1 mV.

Figure 16
(i) Find the digital output for VA = 5.022 V

(ii) Find the range of analog input values that will produce a digital output of 0100011100

is correctly

Solution:

(i) With VA = 5.022 V, the values of VAY must be equal or exceed (VA + VT) = 5.023 V to

switch the comparator. So, the summer output is

VAY = VAX + 5 mV

Or, VAX = VAY – 5 mV

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= 5.023 V – 0.005 V

= 5.018 V

Therefore, VAX must equal or exceed 5.018 V. This requires the number of step as

5.018 V
= 501.8 = 502steps
10mV

This gives the output as

VAX = 5.02 V

The required number of steps is 502 which corresponds to the digital value 0111110110.

Hence, the digital output for VA = 5.022 V is 0111110110.

(ii) For the digital binary output, the equivalent decimal number is

(0100011100)2 = (284)10

At count of 28410, we have

VAY = VAX + 5 mV

= 2.84 V + 5 mV

= 2.845 V

At count of 28310, we have

VAY = 2.83 V + 5 mV

= 2.835 V

Thus, the correct range of analog input voltage is VA = 2.83.

Example 17

A certain 8-bit successive-approximation converter has 2.65 V full scale. The conversion

time for VA = 1.5 V is 75 μs. Find the conversion time for V A = 2V.

Solution:

The total conversion time for an N-bit successive approximation type ADC will be N-clock

cycles. The conversion time will be same regardless of the value of V A. This is because

the control logic has to process each bit to see whether a 1 is needed or not. Hence, the

conversion time for VA = 2V and for VA = 1.5 V will be same and is 75 μsec.

Example 18

Assume the following values for the ADC clock frequency = 1 MHz; V T = 0.1 mV; DAC

has F.S. output = 10.23 V and a 10-bit input.

Determine the following values.

(i) The digital equivalent obtained for VA = 3.728 V.

(ii) The conversion time.

(iii) The resolution of this converter.

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Solution:

(i) The DAC has a 10-bit input and a 10.23-V F.S. output. Thus, the number of total

possible steps is 210 - 1 = 1023, and so the step size is

10.23V
= 10 mV
1023

This means that VAX increases in steps of 10 mV as the counter counts up from zero.

Since VA = 3.728 V and VT = 0.1 mV, VAX has to reach 3.7281 V or more before the

comparator switches LOW. This will require.

3.7281V
= 372.81 373
10 mV

At the end of the conversion, then, the counter will bold the binary equivalent of 373,

which is 0101110101. This is the desired digital equivalent of V A = 3.728 V, as produced

by this ADC.

(ii) Three hundred seventy-three steps were required to complete the conversion. Thus,

373 clock pulses occurred at the rate of one per microsecond. This gives a total conversion

time of 373 µs.

(iii) The resolution of this converter is equal to step size of the DAC, which is 10mV. In

percent it is 1/1023 × 100% ≈ 0.1%.

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PRACTICE CONVENTIONAL PROBLEMS

Question1
Explain about analog to digital converters and digital to analog converters.
Question 2
Draw the schematic diagram of a 4-bit R-2R ladder digital to analog converter and explain its
working.
Question 3
Why dual slope analog to digital converter is preferred in a digital voltmeter?
Question 4
With the help of suitable diagram, describe the operation of 8-bit successive approximation
ADC.
Question 5
With the help of suitable diagram and table, explain the operation of 3-bit flash type ADC.
Question 6
(i) Explain digital ramp ADC with the help of suitable diagram.
(ii) An 8-bit digital ramp ADC with a 40 mV resolution uses a clock frequency of 2.5 MHz and
a comparator with VT= 1 mV. Find the digital output for VA= 6.0 V.

****

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