SY:IV: Microcontrollers: 1UEXC402 Module 1: Overview of Microcomputer based System Distinguish between Microprocessors and Microcontrollers Explain concept of timers and counters in 8051 Distinguish between RISC AND CISC CPU ARCHITECTURES 1 2 3 4 _ Distinguish between VON- NEUMANN & HARVARD CPU ARCHITECTURE 5 Outline the Features of 8051 microcontrollers. 6 Explain concept of Interrupts in 8051 7 Explain serial data input and output concept in 8051 Module 2: The Memory Systems 8 Classify Memory : Primary and Secondary 9 Explain different types of Semiconductor memories 10 Explain Cache Memory 11 Explain Virtual Memory Concept with Memory Management Unit with Segmentation and Paging. Module 3: 8051 Microcontroller 12 Draw and Explain Architecture of 8051 13 Discuss Pin diagram of 8051 14 Discuss Memory organization of 8051 15 Explain Internal RAM organization of 8051 16 What is stack? How is it implemented in 8051 17 Discuss Instruction Syntax 18 Comparison of 8051 family members 19 Explain The Stack and Stack pointer 20 Discuss the Special Function Registers (SFRs) of 8051. 21 Discuss CPU timing and machine cycle 22 Outline the Features of 8051 microcontrollers. 23 Explain concept of Interrupts in 8051 24 Explain serial data input and output concept in 8051 25 Explain Serial Communication in 8051 26 Explain Serial Interface in 8051 27 Explain Data Transmission in microcontrollersSA ee nt of Electr snd Telecomm ion ri SY:1V: Microcontrollers: 1UEXC402 Module 4: 8051 Assembly Language Programming and Interfacing 28 Explain Addressing modes in 8051 29 Explain 1O Port Usage in 8051 30 Explain the Need of Assembler & Cross Assemble, Assembler Directives 31 List 8051 Data types and directives 32 Explain 8051 Interrupt 33 Programs related to: arithmetic, logical 34 Programs related to: delay subroutine 35 Programs related to: output, timer, counters 36 Programs related to: port, serial communication 37 Programs related to: interrupts 38 Interfacing of 8051 with LEDs 39 Interfacing of 8051 with Seven Segment Display 40 _ Interfacing of 8051 with Relay and Keys, LCD 41 Compare between SIMP , LIMP and AMP 42 Compare Jump and call instructions in 8051 43 Block Transfer in 8051 44 What is stack? How is it implemented in 8051, 45 WAP to find EVEN nos. 46 WAP to find smallest and Largest number in series 47 WAP to sort numbers using 8051 Module 5 : ARM7 48 Explain ARM 7 Programmers Model 49. Explain ARM 7 Features 50 Explain ARM 7 CPSR and SPSR 51 Explain ARM 7 operating modes 52 Explain ARM 7 Interrupts and Exception 53 Distinguish between RISC and CISC 54 Explain ARM 7 Load Store Model 55 Distinguish between Thumb state and ARM state1) MICROPROCESSORS AND MICROCONTROLLERS: [Ccearere—] [Cine Block diagram of microprocessor Microprocessor Microcontroller ‘Arithmeti and og aw | 10 Pons nit : Interrupt — teens Circuits sige Tmteral RAM || ROM [Program Counter Suck Poiner | sek rote ca Block diagram of microcontroller Microprocessor contains ALU, General purpose registers, stack pointer, program counter, clock timing circuit, interrupt circuit Microcontroller contains the circuitry of microprocessor, and in addition it has built in ROM, RAM, I/O Devices, Timers/Counters etc. It has many instructions to move data between memory and CPU It has few instructions to move data between memory and CPU Few bit handling instruction It has many bit handling instructions Less number of pins are multifunctional More number of pins are multifunctional Single memory map for data and code (program) Separate memory map for data and code (program) Access time for memory and IO are more Less access time for built in memory and 10. Microprocessor based system requires additional hardware It requires less additional hardwares More flexible in the design point of view Less flexible since the additional circuits which is residing inside the microcontroller is fixed for a particular microcontroller| The 6051 has two 16-bit timer / Counter registers, | Timer 0 and Tim 1. Both of these can be configured |_ either as timer or as counter. | Asa timer the register is incremented ‘every machine | fycle. Thus the register counts the machine cycles. Since a machine cycle consists of 12 clock periods, the | rate of counting is 1/12 of oscillator frequency. | Asa counter the register is incremented in response to | 21 to 0 transition at its corresponding external input | pin. TO or T1. The external input is sampled during 'SSP2 of every machine cycle. When the samples show | 2 high in one cycle and low in next clock cycle, the | count is incremented. The new count value appears in | the register during $3P1 of the cycle following the one |In which transition was detected. since 2. machine cycles (24 clock periods) are required to recognize a 1 to 0 transition, the maximum count rate is 1/24 of the oscillator frequency. ‘There are no restrictions on the duty cycle of the ‘external input signal, but jt should be held atleast for ‘one machine cycle, to ensure that the input is sampled atleast once before it changes. ‘The timer or counter function is selected by control bits C/T in the Special Function Register (SFR) TMOD. In addition to Timer and Counter functions, both the timers have four operating modes. The mode of Operation is selected by the MO and M1 bits of the TMOD register. 1 Timer Mode Control (TMOD) Special Function Register 6 s 46 3 2 _ 6 Set to 1 by program to make 1/0 act as a counter by bulses from external: 2.7.2 Timer Control (TCON) Special Function Register 7 6 5 4 3 2 1 0 i | ret | ro | ro | ex [im | eo | 1 | ‘TIMER 1 ‘TIMER 0 Fig.27.2 Table 2.7.2 Timers 1/0 overflow flag. Set by hardware on Timer / Counter overflow. Cleared when processor vectors to interrupt routine. ©] ge wa] wo [core | cz [mt] v0 TIMER 1 TIMERO Fig. 2.7.4 6/4 | tR1/0 Timer 1 / 0 run control bit. Set / cleared by software to turn timer / counter on / off. 3/1 | 11/0 Interrupt 1 / edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed.‘As the count rolls over from all 1s to all US, It sets Timer interrupt flag TF1. The counted input is to the timer with TR1=1 and either Gate=0 or INT Setting GATE=1 allows the timer to be controll external input INT1 , to facilitate pulse measurement. TR1 is 2 control bit in the function register TCON. GATE is in TMOD. The 13-bit register consists of all 8-bits of THI a lower 5 bits of TL1. The upper 3 bits of TLL indeterminate and bits should be ignored. Seti run flag (TR1) does not clear the registers. Mode 0 operation is the same for timer 0 as for except that TRO, TFO and INTO replace corresponding Timer 1 signal. There are two gate bits, one for timer 1(TMOD.7) and one for o(TMOD.3) interrupt 1/0 type control bit. Set 7 cleared by software to specify falling edge / low level triggered external interrupts. DUEL Explain various timer modes for 8051. (May 19, 10 Marks) Both timers in mode 0 are 8-bit counters with a divide by 32 prescaler. In this mode, the timer is configured as a 13-bit register. Timer/Counter control logic ciT=0 (TMOD Timer Operation) Fig. 2.7.4 : Timer mode 0 13-bit timer/counter ris Tae mom Fig. 2.7.5 : Timer mode 1 16-bit timer/counter7.4 Timer Mode 1 Mode 1 is the same as Mode 0, except that the Timer er is run with all 16 bits. The clock is applied to the bined high and low registers (TL1 / TH1). As clock are received, the timer counts up : 0000H, 0001H, 2H, etc. An overflow occurs on the FFFFH to O000H flag. The overflow flag is the TF1 bit in the TCON is read or written by software. 7.5 Timer Mode 2 Mode 2 configures the Timer register as an 8-bit ter (TL1) with automatic reload. Overflow from TLi not Sets TF1, but also reloads TL1 with the contents of 11, which is preset by the software, The reload leaves TH1 anged. Mode 2 operation is same for Timer/Counter 0. 7.6 Timer Mode 3 Timer 1 in mode 3 simply holds its count. The effect is same as setting TR1=0. Timer 0 in mode 3 establishes TLO and THO as two Separate counters. The logic for Mode 3 on Timer 0 Is shown in the Fig. 2.7.7 TLO uses the Timer 0 control bits :C/T, GATE, TRO, INTO and TFO. THO is locked into _ a timer function (counting machine cycles) and over the use of TR1 and TF1 from Timer 1. Thus, THO now _ controls the timer 1 interrupt. _ Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in mode 3, 8051 can appear to have three timer / counters. When timer is in mode 3, timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as _a baud rate generator or in any application not Tequiring an interrupt.RISC AND CISC CPU ARCHITECTURES Microcontrollers with small instruction sets are called reduced instruction set computer (RISC) machines and those with complex instruction set are called complex instruction set computers (CISC). Intel 8051 is an example of a CISC machine whereas microchip PIC 18F87X is an example of RISC machine. RISC cisc Instruction takes one or two cycles Instruction takes multiple cycles Only load/store instructions are used to access memory In additions to load and store instructions, memory access is possible with other instructions also. Instructions executed by hardware Instructions executed by the micro program Fixed format instruction Variable format instructions Few addressing modes Few instructions Many addressing modes Complex instruction set Most of the have multiple register banks Single register bank Highly pipelined Less pipelined Complexity is in the compiler Complexity in the microprogramVON- NEUMANN & HARVARD CPU ARCHITECTURE Program Memory a CPU 7 Data Memory ress Bus Data Memory ‘Address Bus Program Memory Von-Neumann (Princeton architecture) Harvard architecture It uses single memory space for both instructions and data. It has separate program memory and data memory It is not possible to fetch instruction code and data Instruction code and data can be fetched simultaneously Execution of instruction takes more machine cycle Execution of instruction takes less machine cycle Uses CISC architecture Uses RISC architecture Instruction pre-fetching is a main feature Instruction parallelism is a main feature ‘Also known as control flow or control driven computers Also known as data flow or data driven computers Simplifies the chip design because of single memory space Chip design is complex due to separate memory space Eg. 8085, 8086, MC6800 &g. General purpose microcontrollers, special DSP chips etc.Features of 8051 microcontroller . - Eight bit CPU + On chip clock oscillator + Kbytes of internal program memory (code memory) [ROM] - 128 bytes of internal data memory [RAM] - 64 Kbytes of external program memory address space. + 64 Kbytes of external data memory address space. + 32 bi directional I/O lines (can be used as four 8 bit ports or 32 individually addressable 1/O lines) + Two 16 Bit Timer/Counter :TO, T1 + Full Duplex serial data receiver/transmitter - Four Register banks with 8 registers in each bank. - Sixteen bit Program counter (PC) and a data pointer (DPTR) + 8 Bit Program Status Word (PSW) + 8 Bit Stack Pointer - Five vector interrupt structure (RESET not considered as an interrupt.) + 8051 CPU consists of 8 bit ALU with associated registers like accumulator ‘A’ , B register, PSW, SP, 16 bit program counter, stack pointer. - ALU can perform arithmetic and logic functions on 8 bit variables. + 8051 has 128 bytes of internal RAM which is divided into 0 Working registers [00 — 1F] o Bit addressable memory area [20 — 2F] o General purpose memory area (Scratch pad memory) [30-7F]8051 Interrupt A computer has only two ways to determine the conditions that exist in internal and external circuits. One method uses software instructions that jump to subroutines on the status of flags and port pins. The second method responds to hardware signals, called interrupts that force the program to call a subroutine. Most applications of microcontroller involve responding to events quickly enough to control the environment that generates the events termed real-time programming. An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service. A single microcontroller can serve several devices by two ways. 1) Interrupts Whenever any device needs its service, the device notifies the microcontroller by sending it an interrupt signal. Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and serves the device. The program which is associated with the interrupt is called the interrupt service routine(ISR) or interrupt handle 2) Polling The microcontroller continuously monitors the status of a given device. When the conditions met, it performs the service. After that, it moves on to monitor the next device until everyone is serviced. Polling can monitor the status of several devices and serve each of them as certain conditions are met. The polling method is not efficient, since it wastes much of the microcontroller"s time by polling devices that do not need service. ex. JNB TEtarget. The advantage of interrupts is that the microcontroller can serve many devices (not all at the same time). Each devices can get the attention of the microcontroller based on the assigned Priority. For the polling method, it is not possible to assign priority since it checks all devices in a round-robin fashion. The microcontroller can also ignore (mask) a device request for service. This is not possible for the polling method. For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler. When an interrupt is invoked, the microcontroller runs the interrupt service routine. For every interrupt, there is a fixed location in memory that holds the address of its ISR. The group of memory locations set aside to hold the addresses of ISRs is called interrupt vector tableBasically there are Six interrupts allocated as follows 1) Reset — power-up reset 2) Two interrupts are set aside for the timers: one for timer 0 and one for timer 1 3) Two interrupts are set aside for hardware. external interrupts P3.2 and P3.3 are for the external hardware interrupts INTO (or EX1), and INT2 (or EX2). 4) Serial communication has a single interrupt that belongs to both receive and transfer. Upon reset, all interrupts are disabled (masked), meaning that none will be responded by the microcontroller if they are activated. The interrupts must be enabled by software in order for the microcontroller to respond to them. What is the difference between RET and RET! Instructions. The instruction RET is a return from a function or a subroutine while RET! is return from an interrupt. The RETI instruction is executed at the end of the interrupt subroutine. After the execution of the RET! instruction the PC address will be restored from the stack.Microcontrollers (MU) 2-24 The Nemory Management Untt (MMU) connected to th processor converts the virtual address to the eee adaress and take care of bringing the pages (block fe data) to the main memory from the extern, ‘al memory. Fig. 2.8.1 : Connection of external or virtual memory to the processor Paging Mechanism or the Memory Management Unit the paging mechanism, (6 Marks) ‘What is the use of Translational look aside butter? : (4 Marks) = The memory management unit or the paging unit is responsible to convert the virtual or the linear address tophysical address. - Fig. 2.8.2 shows how the address translation takes The ‘The address given by the processor Le. the linear or Virtual address, is broken into the page number and the Word number in that page, ‘The page number is checked for its presence in the main memory by comparing the entry for each page in the page table. If the page is present the word required \sread from the page in the main memory. ~ Ifthe page required by the processor is not in the main ‘memory, the page fault (similar to cache miss) occurs and the required page is loaded into the main memory by a special routine called as page fault routine. This technique is called as Demand Paging i.e. the page is brought from the external memory to the main ‘memory only when required. = ATTranslational Look aside Buffer (TLB) is implemented in the memory management system, which reduces the memory access time, by translating the linear to Physical address without undergoing the paging mechanism. The structure of memory management with TLB is as shown In Fig. 2.8.3. Hit Fig. 2.8.3 : Translation Look aside Buffer = As shown in the Fig, 2.8.3, TLB is placed parallel with the paging mechanism and hence if the TLB gives a hit, the paging mechanism doesn’t perform the address translation, else the paging mechanism performs the address translation, 2.9 Exam Pack (Review and University Questio Q. List and explain the characteristics of memory, (Reter Section 2.1) (4 Marks) Q. Espiain memory hierarchy. Page table (Refer Section 2.2) (6 Marks) Fig, 2.8.2 : Paging mechanism WW letonietatArchitecture of 8051 ER ke 4 + 8051 has 4 K Bytes of internal ROM. The address space is from 0000 to OFFFh. If the Program size is more than 4 K Bytes 8051 will fetch the code automatically from external memory. « Accumulator is an 8 bit register widely used for all arithmetic and logical operations. Accumulator is also used to transfer data between external memory. B register is used along with Accumulator for multiplication and division. A and B registers together is also called MATH registers.3, CLR PSW.4, MO\Pin11 | TXD. Serial asynchronous communication output or Serial synchronous communication clock output. Pin 12, | INTO.External interrupt 0 input Pin 13 | INTA. External interrupt 2 input Pin 14 | To. Counter 0 clockinput Pin15 | TA. Counter 1 clock input Pin16 | WR. Write to external (ailtional) RAM Pin 17 | RD. Read from external RAM Pin 18,19 | XTAL2, XTAL1. Internal oscillator input and output. A quartz crystal which specifies ‘operating frequency is usually connected to these pins. Pin20 | GND. Ground. Pin 21-28 | Port 2. If there is no intention to use external memory then these port pins are configured as general inputs/outputs. In case external memory is used, the higher ‘address byte, ie. addresses A8-A15 will appear on this port. Even though memory with ‘capacity of 64Kb is not used, which means that not all eight port bits are used for its addressing, the rest of them are not available as inputs/outputs. Pin 29 | PSEN. If external ROM is used for storing program then 2 logic zero (0) appears on it ‘every time the microcontroller reads a byte from memory. Pin 30 | ALE. Prior to reading from external memory, the microcontroller puts the lower address byte (A0-A7) on PO and activates the ALE output. After receiving signal from the ALE pin, the external latch latches the state of PO and uses it as a memory chip address. Immediately after that, the ALE pin is returned its previous logic state and PO is now used as a Data Bus Pin31 | EA. By applying logic zero to this pin, P2 and P3 are used for data and address transmission with no regard to whether there is internal memory or not. It means that even there isa program written to the microcontroller, it wil not be executed. Instead, the program written to external ROM will be executed. By applying logic one to the EA pin, the microcontroller will use both memories, fist internal then external if exists). KJ Somaiya Institute of Engineering and Information Technology, Sion, Mumboi-22 eS Accredited by NAAC with “A” Grade Three Programs NBA Accredited: Computer Engineering, Electronics Engineering ond Electronics and Telecommunication Engineering Permanently Affiliated to University of Mumbai Best College Award by University of Mumbai for AY. 2018-2019, Urban Region Department of Electronics and Telecommunication Engineering ECC601:Microcontrollers and Application {Question Bank and Solution_ 2021 Pin 32-39 | PORTO. Similar to P2, if external memory is not used, these pins can be used as general inputs/outputs. Otherwise, PO is configured as address output (A0-A7) when the ALE pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0) Pin4o | VCC. +5V power supply.Memory organization of 8051 8051 Memory Organization The 8051 microcontroller's memory is divided into Program Memory and Data Memory. Program Memory (ROM) is used for a permanent saving program being executed, while Data Memory (RAM) is used for temporarily storing and keeping intermediate results and variables. Program Memory (ROM) Program Memory (ROM) is used for a permanent saving program (CODE) being executed. The memory is read only. Depending on the settings made in the compiler, program memory may also be used to store constant variables. The 8051 executes programs stored in program memory only. code memory type specifier is used to refer to program memory. 8051 memory organization allows external program memory to be added. The microcontroller handles external memory depending on the pin EA logical state. ‘Address FFFF hex EA pin=0 Address FFFF hex Doe « Address 0000 he: aInternal Data Memory Up to 256 bytes of internal data memory are available depending on the 8051 derivative. Locations available to the user occupy addressing space from 0 to 7Fh, i.e. first 128 registers and this part of RAM is divided in several blocks. The first 128 bytes of internal data memory are both directly and indirectly addressable. The upper 128 bytes of data memory (from 0x80 to OxFF) can be addressed only indirectly. Since internal data memory is used for CALL stack also and there is only 256 bytes splited over few different memory areas fine utilizing of this memory is crucial for fast and compact code. See types efficiency also. Memory block in the range of 20h to 2Fh is bit-addressable, which means that each bit being there has its own address from 0 to 7Fh, Since there are 16 such registers, this block contains in total of 128 bits with separate addresses ( Bit 0 of byte 20h has the bit address 0, and bit 7 of byte 2Fh has the bit address 7Fh). Three memory type specifiers can be used to refer to the internal data memory: data, idata, and bdata.ory type specifInternal RAWhat is stack? How is it implemented in 8051. Stack: The stack is a section of RAM used by the CPU to store information temporarily information could be data or an address. 1. The register used to access the stack is called stack pointer register. 2. Stack is used to store data temporarily during any program execution, 3. The 8 bit stack pointer is used to hold an internal RAM address which is called the top of stack. 4. Generally 8051 used bank1 of internal RAM as the stack so the default stack pointer is 07H. 5. The stack pointer in the 8051 is only 8 bit wide which means that it can take a value of 00 to FFH. 6. When the 8051 is powered up the sp register contains value 07H. 7. RAM location O8H is the first location used for the stack by the 8051. 8. When data is retrieved from the stack the byte is read from the stack and then sp register increment. 9. The stack is used during PUSH, POP, CALL, RET instruction. 10. Stack pointer work on the principal of the last ID first output (LIFO). Data push into Data read from stack using push stack using pop instruction instruction ‘Data Dass ‘Data Dats Data Data Data Data Data Data DataINSTRUCTIONComparison of 8051 family members ROM [on chip program space in bytes] RAM [bytes] Timers 1/O pins Serial port Interrupt sourcesSpecial Function Registers (SFRs) The 8051 operations that do not use the internal RAM addresses from 00h to 7fh are done by a group of specific internal registers each called a specific function register (SFR) which may be addressed much like internal RAM using addresses from 80h to ffh. Some SFRs are also bit addressable as is the case for the bit area of RAM. SFR Map: The set of Special Function Registers (SFRs) contain important registers such as Accumulator, Register B, |/O Port latch registers, Stack pointer, Data Pointer, Processor Status Word (PSW) and various control registers. Some of these registers are a bit addressable. The detailed map of various registers is shown in the following figure. Fi a SP. DPTR DPL DPH PO Pi P2 P3 Tr TE TMOD TCON Fl 8 ARERR8051 Interrupt A computer has only two ways to determine the conditions that exist in internal and external circuits. One method uses software instructions that jump to subroutines on the status of flags and port pins. The second method responds to hardware signals, called interrupts that force the program to call a subroutine. Most applications of microcontroller involve responding to events quickly enough to control the environment that generates the events termed real-time programming. An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service. A single microcontroller can serve several devices by two ways. 1) Interrupts Whenever any device needs its service, the device notifies the microcontroller by sending it an interrupt signal. Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and serves the device. The program which is associated with the interrupt is called the interrupt service routine(ISR) or interrupt handle 2) Polling The microcontroller continuously monitors the status of a given device. When the conditions met, it performs the service. After that, it moves on to monitor the next device until everyone is serviced. Polling can monitor the status of several devices and serve each of them as certain conditions are met. The polling method is not efficient, since it wastes much of the microcontroller's time by polling devices that do not need service. ex. JNB TFtarget. The advantage of interrupts is that the microcontroller can serve many devices (not all at the same time). Each devices can get the attention of the microcontroller based on the assigned Priority. For the polling method, it is not possible to assign priority since it checks all devices in a round-robin fashion. The microcontroller can also ignore (mask) a device request for service. This is not possible for the polling method. For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler. When an interrupt is invoked, the microcontroller runs the interrupt service routine. For every interrupt, there is a fixed location in memory that holds the address of its ISR. The group of memory locations set aside to hold the addresses of ISRs is called interrupt vector tableBasically there are Six interrupts allocated as follows 1) Reset — power-up reset 2) Two interrupts are set aside for the timers: one for timer 0 and one for timer 1 3) Two interrupts are set aside for hardware. external interrupts P3.2 and P3.3 are for the external hardware interrupts INTO (or EX1), and INT1 (or EX2). 4) Serial communication has a single interrupt that belongs to both receive and transfer. Upon reset, all interrupts are disabled (masked), meaning that none will be responded by the microcontroller if they are activated. The interrupts must be enabled by software in order for the microcontroller to respond to them. What is the difference between RET and RETI Instructions. The instruction RET is a return from a function or a subroutine while RETI is return from an interrupt. The RETI instruction is executed at the end of the interrupt subroutine. After the execution of the RETI instruction the PC address will be restored from the stack.ze Serial communication is most commonly used either to control or to receive data from an embedded micro- processor. The advantage of serial communication is that the number of wires required is less as compared to that in parallel communication. Serial communication is a form of I/O in which the bits of a byte begin transferred appear one after the other in a timed sequence on a single wire. Figure 13.39 shows the serial communication through telephone line where P/S is parallel in serial out shift register, S/P Serial in parallel out shift register, D/A digital to analog converter and A/D is analog to digital converter. Single Wire Sender |{ P/S }| D/A ‘ADH sip }iReceiver Data Flow Fig. 13.39 Serial communication through single wire There are two methods of serial communications, such as synchronous and asynchronous communications. In synchronous communication, transfer a block of data at a time, but in asynchronous communication transfer a single byte at a time. Software can be used for synchronous and asynchronous communications, but the programs can be tedious and long. Therefore hardware such as UART and USART are developed. Usually UART (Universal Asynchronous Receiver Transmitter) or USART (Universal Synchronous Asynchronous Receiver Transmitter) are used in serial communication. The 8051 microcontroller has a build in UART. 8051 support a full duplex serial port (UART). 8051 has T x D and R x D pins for transmission and receive serial data respectively. The function of serial port is to perform parallel to serial conversion for data output and serial to parallel conversion for data input. The block diagram of UART is shown in Fig, 13.40. Stop bit Send 8-bit Ten bit Data L__/) SBUF parallel r+ B-bit to Data Serial Conversion Transmitter Buffer : is Empty “71 Stop bit aed ——+ Serial data transmit Start bit Stop bit | 8-bit Data > Fig. 13.40 (a) Transmitter half (contd.)Serial Interface The serial port of 8051 is full duplex, i.e., it can transmit and receive simultaneously. The register BUF is used to hold the data. The special function register SBUF is physically two registers. One is, write-only and is used to hold data to be transmitted out of the 8051 via TXD. The other is, read-only and holds the received data from external sources via RXD. Both mutually exclusive registers have the same address 099H. Serial Port Control Register (SCON) SCON Register Serial control register: SCON SMO, SM1 : Serial port mode specifier Register SCON controls serial data communication. Address: 098H (Bit addressable) smo sM1 sM2 RBS. TB8 REN RI Tl SM2:used for multiprocessor communication. REN: set or cleared by software to enable/disable reception. TB8: Transmitted bit 8,not widely used, RB8:Received bit 8. TI:Transmit interrupt flag ~set by the hardware at the beginning of the stop bit in mode 1, must be cleared by software. RI: Receive interrupt flag -set by the hardware halfway through the stop bit time in mode1, must be cleared by software. Programming the 8051 to transfer data serially In programming the 8051 to transfer character bytes serially, the following steps must be taken. 1, The TMOD register is loaded with the value 20H, indicating the use of Timer 1 in mode 2 (8-bit auto-reload) to set the baud rate. 2. The TH1 is loaded with one of the values in Table 10-4 to set the baud rate for serial data transfer (assuming XTAL = 11.0592 MHz). 3. The SCON register is loaded with the value 50H, indicating serial mode 1, where an 8-bit data is framed with start and stop bits. 4. TR1 is set to 1 to start Timer 1. 5. Tlis cleared by the “CLR TI” instruction. 6. The character byte to be transferred serially is written into the SBUF register.Data Transmission Transmission of serial data begins at any time when data is written to SBUF. Pin P3.1 (Alternate function bit TXD) is used to transmit data to the serial data network. TI is set to 1 when data has been transmitted. This signifies that SBUF is empty so that another byte can be sent. Data Reception Reception of serial data begins if the receive enable bit is set to 1 for all modes. Pin P3.0 (Alternate function bit RXD) is used to receive data from the serial data network. Receive interrupt flag, RI, is set after the data has been received in all modes. The data gets stored in the SBUF register from where it can be read. Serial Data Transmission Modes: Mode-0: In this mode, the serial port works like a shift register and the data transmission works synchronously with a clock frequency of fosc /12. Serial data is received and transmitted through RXD. 8 bits are transmitted/ received at a time. Pin TXD outputs the shift clock pulses of frequency fosc /12, which is connected to the external circuitry for synchronization. The shift frequency or baud rate is always 1/12 of the oscillator freq ‘SBUF ov | RXD <—® Data transmitted) received Tnternalcoch eanarater > > Shift pulses of ‘f ose/12" jon/reception in Mode-0 In mode-1, the serial port functions as a standard Universal Asynchronous Receiver Transmitter (UART) mode. 10 bits are transmitted through TXD or received through RXD, The 10 bits consist of one start bit (which is usually '0'), 8 data bits (LSB is sent first/received first), and a stop bit (which is usually '1'). Once received, the stop bit goes into RBS in the special function register SCON. The baud rate is variable. The following figure shows the way the bits are transmitted received.‘Stop bit goes to RBS for reception Bit time= I/fvoua In receiving mode, data bits are shifted into the receiver at the programmed baud rate. The data word (8-bits) will be loaded to SBUF if the following conditions are true. RI must be zero, (i.e., the previously received byte has been cleared from SBUF) Mode bit SM2 = 0 or stop bit = 1. After the data is received and the data byte has been loaded into SBUF, RI becomes one. Mode-1 baud rate generation: Timer-1 is used to generate baud rate for mode-1 serial communication by using overflow flag of the timer to determine the baud frequency. Timer-1 is used in timer mode-2 as an auto-reload 8-bit timer. The data rate is generated by timer-1 using the following formula Serial Data Mode-2 - Multiprocessor Mode : In this mode 11 bits are transmitted through TXD or received through RXD. The various bits are as follows: a start bit (usually '0'), 8 data bits (LSB first), a programmable 9 th (TB8 or RB8)bit and a stop bit (usually '1'). While transmitting, the 9 th data bit (TB8 in SCON) can be assigned the value ‘0' or '1', For example, if the information of parity is to be transmitted, the parity bit (P) in PSW could be moved into TB8. On reception of the data, the 9 th bit goes into RBS in 'SCON', while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency. Mode-3 - Multi processor mode with variable baud rate : In this mode 11 bits are transmitted through TXD or received through RXD. The various bits are: a start bit (usually '0'), 8 data bits (LSB first), a programmable 9 th bit and a stop bit (usually '1'). Mode-3 is same as mode-2, except the fact that the baud rate in mode-3 is variable (i.e., just as in mode-1). f baud = (2 SMOD /32) * ( fosc / 12 (256-TH1)) . This baud rate holds when Timer-1 is programmed in Mode-2.14.2.1 Immediate Addressing Jn immediate addressing mode, the source operand is constant rater than a variable. The constant operand «an be incorporated into te instruction as a byte of immediate address. The immediate operands ar preceded by ad signin assembly language. The operand may be a numeric constant (decimal or hexadecimal), asym bolic variable or an arithmetic expression. Example \Mov A, #FFH; This istration is used to load the immediate dats FF H 9 register MOV RO, #26; This is used to load the immediate data byte 26H to reste RO. Allinstructions using immediate addressing use an 8-bit data field. But one exceptions thata 16-bit con- stant is required for initialization ofthe Data Pointer Register (DPTR). For example, MOV DPTR, #90001 Afler execution ofthe MOV DPTR, #9000H instruction, 9000H wil be loaded into DPTR register. Table 14.1 shows some other examples of immediate addressing: ‘Table 14.1. Exomples of immediate addressing instructions fo tsrction Task 14.2.2 Register Addressing Mode In register addressing mode, the selected repister bank containing repsters RO through R7 ean be accessed ‘by certain instructions which camry a }-bit register specification within the opcode ofthe instruction. As the three least significant bits of the instruction opeade are used to specify a register, this addressing mode elim nates an address byte. When the instruction is executed, one of the eight rezisters in the selected bank will be accessed, One of four banks is selected at execution time by the two bank sles in the PSW. Example) Mov A, Ro Move the contnt of RO register into accumulator MOV RI, A Move the content of accumulator into RI register ‘Some instractons are specific ta certain register. For example, some instructions always operate on the accumulator, or data pointer and no addres bye s required to point tot. The opcode itself specifies the souree of operand and an example is INC A. In thie instruction, the acumlator itself isthe operand. The ‘examples of other register addressing instructions are given in Table 14.2. “Table 14.2 Examples of retster addressing instructions Instruction Set ond Programming ofthe 8051 Microcontroller 765 14.2.3 Direct Addressing ternal RAM Aecumutior In direct addressing mode, the operand is specified by an bit “= address fed in the insiraction. Only the Hower 128 bytes of |__22__ J ®\_ aH intemal data RAM and SFRs ean be directly addressed by S27] using a sngle-byte ares, R een fF Example) ov 4,331 This insruction is used to tansfer the content of Fig, 14.4, Direct addressing Jmernal memory (RAM) location 33H to accumulator as shown in Fig. 14.1 ‘MOV 32,R1 The coatcat of register RI moves to internal memory location 32H as depicted in Fig, 14.1 ‘Table 143 shows the some other examples of diet addressing. Table 14.3. Examples of direct addressing ADDA. Ry “Add ihe content of epister Rte accumulator :14.2.3 Direct Addressing Intemal RAM sesame Indret adressing mode, the operands specified by an it internal data RAM and SFRs can be directly addressed by hea 22 33H vsinga singlet adress. 8 wpoe en FOL EXERBIE) nov a,33H Tie inaction is wea LF] to transfer the content of Fig. 14.1. Direct addressing internal memory (RAM) location 33H to accumulator as shown in Fig. 14.1 MOV 32, RI. The content of register RI moves to internal memory location 32H as depicted in Fig. 14.1 ‘Table 14.3 shows the some other examples of direct addressing. Table 14.3 Examples of direct addressing rh i MOVR,.A 1 ___ Move data from accumulator to register Ry, 14.2.4 Indirect Addressing In indirect addressing mode, the instruction specifies a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed. In this mode, RO or RI of selected bank or the stack pointer may operate as pointer registers for 8-bit addresses. Actually, the content of RO or RL indicates an address in internal RAM where data will be stored or read. In assembly-language programming, indirect addressing is presented by a @ symbol before RO or RI Example Mov A, @R7 In this instruction, the content of R7 represents the intemal memory address. As the R7 contains 33H, the internal memory location will be 33H. After the execution of this instruction, the value of the internal memory location 34H will be loaded into the accumulator as depicted in Fig. 142. ‘The data pointer register can also be used as the address register for a 16-bit address. Some examples of indirect addressing are illustrated in Table 14.4 Internal RAM Accumulator aH R 2 \« 2 (33H 3 Fe 32H Fig. 14.2 Indirect addressing 766 Microprocessors and Microcontrollers Table 14.4 Examples of indirect addressing DEC @R. idGaechnat GhMlanek BASE eneriied GY RTE: or 410 Port Usage in 8051 The four 8-bit /0 ports PO, PA, P2 and P3 each use 8 pins. Al the ports upon RESET are configured as Input, ready to be used as input ports. When the first 0 is written to a port, it becomes an output port. To reconfigure it as an input, 1 must be sent to the port. To use any of these ports as an input port, it must be programmed. It can be used for input oF output, each pin must be connected externally toa 10K ohm pull-up resistor. This is due to the fact that PO is an open drain, unlike P3,P2, and P3. Open drain isa term used for MOS chips in the same way that open collector is used for TTL chips Port 0 with pull up registers ‘The following code will continuously send out to port 0 the alternating value SSH and AAH BACK: MOV ASH Mov POA ACALL DELAY MOV A,WOAAH MOV POA ‘ACALL DELAY SIMP BACK Port 0as input In order to make port 0 an input, the port must be programmed by writing 1 to all the bits. Port 0is configured first as an input port by writing 4s to it, and then data is received from that port and sent to Pi 4 Somaiya Institute of Engineering and information Technology, Sion, Mumbal-22 | sd Accredited by NAAC with “A” Grade Three Programs NBA Accredited: Computer Engineering, Electronics Engineering and Electronics ond Telecommunication Engineering Permanently Affiliated to University of Mumbai Best College Award by University of Mumbai for AY. 2018-2019, Urban Region Department of Electronics and Telecommunication Engineering ECC6O1:Microcontrollers and Application {Question Bank and Solution_2024, MOV AWOFFH F hex MOV POA; make PO ani/p port zby writing it all 1s, BACK: MOV A,PO _;get data from PO MOV P3,A send itto port 1 SJMP BACKDual role of Port 0 Port 0 is also designated as ADO-AD7, allowing it to be used for both address and data. Wh connecting an 8051/31 to an external memory, port 0 provides both address and data. Port 1 can used as input or output In contrast to port 0, this port does not need any pull-up resistors since already has pull-up resistors internally. Upon reset, port 1 is configured as an input port. T following code will continuously send out to port 0 the alternating value SSH and AAH MOV Aw#SSH BACK: MOV P1,A, ACALL DELAY cPLA, SIMP BACK To make port 1 an input port, it must be programmed as such by writing 1to all its bits. Port 1 configured first as an input port by writing 1s to it, then data is received from that port and saved R7 and RS. MOV A,HOFFH ;ASFF hex. MOV P1,A ;make P2 an input port ;by writing it all 1s MOV A,P1 ;get data from P1 MOV R7,A jsave it to in reg R7 ACALL DELAY ;wait MOV A\P3 ;another data from P2 MOV R5,A ;save it to in reg RS ... _ KJ Somaiya institute of Engineering and Information Technology, Sion, Mumbai-2. ESN ‘Accredited by NAAC with “A” Grade Thvee Programs NBA Accredited: Computer Engineering, Electronics Engineering ant Electronics and Telecommunication Engineering Permanently Affiliated to University of Mumbai Best College Award by University of Mumbai for AY. 2018-2019, Urban Region Department of Electronics and Telecommunication Engineering ECC601:Microcontrollers and Application, ‘Question Bank and Solution_2021 Port 2 can be used as input or output Just like P2, port 2 does not need any pullup resistors sinct already has pull-up resistors internally. Upon reset, port 2 is configured as an input port. To me port 2 an input port, it must be programmed as such by writing 1 to all its bits. In many 8051-bas systems, P2 is used as simple 1/0. In 8031-based systems, port 2 must be used along with PO provide the 16-bit address for the external memory. Port 2 is also designated as A8 - A15, indicat its dual function. Port 0 provides the lower 8 bits via AO ~A7. Port 3 can be used as input or output Port 3 does not need any pull-up resistors. Port 3 is configured as an input port upon reset. Port 3 h the additional function of providing some extremely important signals.8051 Data types and directives The 8051 microcontroller has only one data type. It is 8 bits, and the size of each register is also 8 bits. It is the job of the programmer to break down data larger than 8 bits (00 to FFH, or 0 to 255 in decimal) to be processed by the CPU. DB (define byte) The DB directive is the most widely used data directive in the assembler, It is used to define the 8-bit data. When DB is used to define data, the numbers can be in decimal, binary, hex, or ASCII formats. For decimal, the “D” after the decimal number is optional, but using “B” (binary) and "tH" (hexadecimal) for the others is required. Regardless of which is used, the assembler will convert the numbers into hex. To indicate ASCII, simply place the characters in quotation marks (,like this"). The assembler will assign the ASCII code for the numbers or characters automatically. The DB directive is the only directive that can be used to define ASCII strings larger than two characters; therefore, it should be used for all ASCII data definitions. Assembler directives The following are widely used directives of the 8051. ORG (origin) The ORG directive is used to indicate the beginning of the address. The number that comes after ORG can be either in hex or in decimal. If the number is not followed by H, it is decimal and the assembler will convert it to hex. Some assemblers use “. ORG” (notice the dot) instead of “ORG” for the origin directive. EQU (equate) This is used to define a constant without occupying a memory location. The EQU directive does not set aside storage for a data item but associates a constant value with a data label so that when the label appears in the program, its constant value will be substituted for the label. The following uses EQU for the counter constant and then the constant is used to load the R3 register. When executing the instruction “MOV R3, #COUNT”, the register R3 will be loaded with the value 25 (notice the # sign). What is the advantage of using EQU? Assume that there is a constant (a fixed value) used in many different places in the program, and the programmer wants to change its value throughout. By the use of EQU, the programmer can change it once and the assembler will change all of its occurrences, rather than search the entire program trying to find every occurrence. END directive Another important pseudocode is the END directive. This indicates to the assembler the end of the source (asm) file. The END directive is the last line of an 8051 program, meaning that in the source code anything after the END directive is ignored by the assembler. Some assemblers use “END” (notice the dot) instead of “END”.Fig. 7.3.5 : Interfacing multiple ssps This entire procedure will be rtinuowsn AREF every 2/50" of a second (Le. every 20 meee) enw an eye feels all the SSDs to be displaying Continuously. Sn Oe‘Move cursor to beginning of 1" line Move cursor to beginning of 2™ line [ate 2 ine asplay of 537 matrixInterface of relay with microcontroller: As relays have operating voltages of 6V/12V but microcontroller’s pin output voltage is 5V so we can't operate relay directly with the microcontroller's pin voltage. So we need to operate relay via transistor’s switch method. Suppose we want to operate a relay using microcontroller with the use of button. When we press button microcontroller will operate the relay. | oa | + = | | | D2 Da tea fone ' ot = ie ope JestineYiong.com } a at ee Relay is connected to the microcontroller’s pin P3.0 (Port 3 and pin 0) and button is connected to P1.0 Commented Code of MicrocontrollerFig. 7.2.2: Non- matrix type keyboord — Toiidentify the key value the followi ing three functions, should be performed : 1. Identifying a key closure 2. Debouncing the key 3. Encoding the key to an appropriate code like hexadecimal, The above three functions can be performed through hardware as well as software. As an example we will see hardware technique for identification of key Closure. The interfacing is as shown in Fig. 7.2.3. ees Fig. 7.2.3 : Hardware technique of Identification Of the keys is pressed, Sen's 0 oI NANO ete (SH eos gh rg connections is reduced. Fle 7.24 shows 16 keys arranged in 4 rows and 4 ‘Columns. No connections are there when the keys are open. if a key is pressed then there is connection between corresponding rows and columns. Such a ‘matrix requires eight lines to complete the ‘connections, fnon matrix type connection is used then 16 lines will ‘be required. So using method reduces the number of connections. ‘Column Column Column Column a ea ee Fig. 7.2.4: Matrix keyboard =Compare between SJMP , LIMP and AMP ‘SIMP MP AMP Short jump, relative address is Long jump range is 64kb Absolute jump to 8 bit it support 127 location anywhere within 2k block forward of program memory Ituses 8 bit address, Ituses 16 bit address tuses an 11 bit address 2 byte instruction. 3 byte instruction 2 byte instruction =» K4Somaiya institute of Engineering and information Technology, Sion, Mumbai-22 oe wt reece RC Acre — Three Programs NBA Accredited: Computer Engineering, Electronics Engineering and Electronics and Telecommunication Engineering Permanently Affiiated to Univesity of Mumbai Best College Award by University of Mumbai for AY. 2018-2019, Urban Region Department of Electronics and Telecommunication Engineering ECC601:Microcontrollers and Application Question Bank and Solution_ 2021 Conditional branch instruction Cannot use long JMP Cannot the JMP absolute can use relative MP. ‘Address calculation PC is equal to 11 bit PC is equal to 16 bit.What is stack? How is it implemented in 8051. Stack: The stack is a section of RAM used by the CPU to store information temporarily information could be data or an address. 1. The register used to access the stack is called stack pointer register. 2. Stack is used to store data temporarily during any program execution. 3. The 8 bit stack pointer is used to hold an internal RAM address which is called the top of stack. 4. Generally 8051 used bank1 of internal RAM as the stack so the default stack pointer is 07H. 5. The stack pointer in the 8051 is only 8 bit wide which means that it can take a value of 00 to FFH. 6. When the 8051 is powered up the sp register contains value 07H. 7. RAM location O8H is the first location used for the stack by the 8051. 8. When data is retrieved from the stack the byte is read from the stack and then sp register increment. 9. The stack is used during PUSH, POP, CALL, RET instruction. 10. Stack pointer work on the principal of the last !D first output (LIFO). Data push into Data read from stack using push stack using pop instruction instruction Data Data ‘Data Data Data Data Data Data Data Data Data Stack Stack- Remy PROGRAMMERS MO DEL A e e* | [+ | | Ro if Ro Ri Rt | | & jee { Rs R3 BS 2 1 Ry Ry | Re Rs | |_&s Rs Re Re f [ase Re - = i | ez | | Ro | ez ks | |_ Ra | ee Ra | ka | | Ra - ‘-_ Rio | | ee | Rio 4 Rut Ru | | Re Riz | Ri | | Ria | Rig-SVE Ri3- ABT Riz-IRQ | RiIZ-OND i Riy-SvC| A Ri4_ ABT Riy-1RQ| Riy_UND | L L Ris (PC) Ris cro) | Ris (PCD Ris (Pe) | Ris (°C) | Ris (Pc) ARIN — PROGRAT STATVS REGISTERS [crse__ | [case | [-eese | [_crse | Leese | [crse | [ses rig] | sese sve| ksese ast] k sese ard J sese ovo] NSHl Reoisters are of 32 bike & can told pewmess or dala FRM arctutechpune te booed ove Vor Neumano Mole . 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Fetch, decode %& Execulé - AeM UWat F Afferent operating mode ly cau be snveked 49 vartous — Prterreplt ARM ETDMIT T+ Mretudes Thumb Pnstuction Set D> Attows tbordware Debuggins Oo CLE Wa F761 interfati M = Inctuctes_lorg Pruttiply Frstracttons + Inetudes eurbedeled FC€ Pitorecett gor _b He % watch pels in program -ConctsHer Hogs Ve Overflow peg ’ __ Vel, means Stared Over} low occurred fow las Kot oceurred - V=0 , means Stoned Overt = Carry Ha C21, meaus Cary afer MsB _ — | a0 means (Ne ees lx = Keo glag tT z -| means vesult (SS AO _ -) means gesull ig KOU- KETO - [N= Negative Bled = Nel, Result & negative N=o , Resule is Posutve | = anls lag always indicale (le Correct” Sign | S ~ : q Spe 9, an averplovs uulike Gntels Sign Han, 2 Saturaton Hoo [B Hog - On € version o A2M> CoSP Ext) Hut spl pncucales % a ‘Sotuyatton las OCcurredl pritomeltc Soburavon Wat OCeured (atl 1% toa 0%) No Sabuqaton — wept ww Some Signal preceteing, y Applicarous . >FIQ Vectored IRQ Non- Vectored IRQ Fast Interrupt Request: For fast, low latency interrupt handling. FIQ have highest priority followed by interrupt vector 0-31. Only single FIQ source at a time is generally used in a system Vectored Interrupt Request: VIRQ have medium priority. Vectored Interrupt Controller has 32 vectored interrupt slots out of which 16 slots are used for vector addressing. Each slot contain vector address register & vector control register Non-Vectored Request: Non Vectored IRQ. has lowest priority. The VIC is capable of handling 16 peripherals as a vectored interrupt and at least one as an FIQ Interrupt. If in case there are more than 17 interrupt sources on chip, any extra interrupt can be serviced as a Non- Vectored Interrupt.29 views 6.2 Timer Mode Timer is type of clock which is used to measure time intervals. Timer requires clock to work and counter is similar to the timer but it works reverse of timer. Counter counts external events. LPC2148 Timer& Counter LPC2148 has two 32-bit timers/counters: Timer0/Counter0 & Timer1/Counter1 ¢ LPC2148 Timer has input of peripheral clock (PCLK) or an external clock. It counts the clock from these clock sources. LPC2148 Timer/Counter able to generate an interrupt signal at specified time value. LPC2148 has match registers that maintains count value which is continuously compared with the value of the Timer register. When the value in the Timer register matches with the value in the match register, specific action (timer reset, or timer stop, or generate an interrupt) is taken.29 views Timer0 Registers 1. TOIR (Timero Interrupt Register) «It is an 8-bit read-write register. «It consists of 4 bits for match register interrupts and 4 bits for compare register interrupts. « If interrupt is generated, then the related bit in this register will be high, otherwise it will be low. «Writing a 1 to any bit of this register will reset that interrupt. cra cra cri cro Ra mre mR Ro TOIR (Timer0 Interrupt Register) 2. TOTCR (Timer0 Timer Control Register) «It is an 8-bit read-write register. «It is used to control the operation of the timer counter. RESERVED \counter Reset| Counter Enable ‘TOTCR (Timero Timer Control Register) + Bit 0 - Counter Enable 0 =Counters are disabled 1=Timer counter and Pre scale counter are enabled for counting « Bit 1 - Counter Reset 0 =Counter not reset 1= Timer counter and Pre scale counter are synchronously reset on next positive edge of PCLK4. TOTC (Timer0 Timer Counter) It is a 32-bit timer counter. It is incremented when the Pre scale Counter (PC) reaches its maximum value held by Pre scaler Register (PR). 5. TOPR (Timer0 Prescale Register) It is a 32-bit register. It holds the maximum value of the Pre scale Counter. 6. TOMRO-TOMR3 (Timer0 Match Registers) These are 32-bit registers. The values stored in these registers are compared with the Timer Counter value. When the two values are equal, the timer can be reset or stop or an interrupt may be generated. The TOMCR controls what action should be taken on a match.