Microcontroller Architecture

The most popular 8051 Microcontroller is designed using Harvard Architecture and hence this type of
Architecture has been considered here to explain its components. The various components/modules of
Microcontroller are:

 Processor Core
 Memory
 Interrupt Controller
 Timer/Counter
 Digital I/O
 Analog I/O
 Interfaces
 Watchdog Timer

Processor Core

It is the Central Processing Unit of the Microcontroller and consists of Arithmetic Logic Unit (ALU).
This unit is responsible for the execution of arithmetical and logic operations.

Control Unit

It controls the operation of MC and is represented by STATUS Register. It helps in transfer of data to
other registers.

Memory
There are two types of data memories in a MC. They are:

 Static RAM (SRAM)

 EEPROM/Flash

Static RAM (SRAM)

SRAM consists of Special Function Registers (SFR) and General Purpose Registers (GPR). SRAM are
8 bit memory cells that provide link between the Microcontroller hardware and software.

The Write cycle (Program/Erase) of this memory is unlimited but the data stored in SRAM is lost if the
power to the controller is lost. Hence EEPROM is also used for Data storage.

Special Function Registers (SFR) controls the functional blocks whereas the General Purpose Registers
(GPR) stores the values of variables and constants.

EEPROM/Flash

It is a type of non-volatile electronic memory, which is used for storage of data. EEPROM memory is
comparatively slow and has limited number of write cycles and hence used to store the data that needs
to be saved when power supply of MC is switched off.

Counter/Timer Module

This module has Timer/Counter which measures the time and calculate the events. Usually a MC
contains 2-3 Timer/Counters and it operates in Timer or Counter mode and calculates the number of
received pulses. Timer also generates PWM Signal which is converted to DC voltage using Low Pass
Filters.

Digital Module

This module consists of Digital I/O. It helps the Microcontroller to detect and output the logic states
(High or Low).

Analog Module

This module consists of Analog I/O. It helps in converting voltage level to digital value. Most MC’s
have integrated Analog-Digital converters. To generate Analog output RC Low Pass Filters are used to
convert PWM outputs to DC voltage.

Serial Interface Module

They are designed to receive or send the digital signals to other devices. Most controllers are provided
with SPI, SCI, Ethernet, USB interfaces.

Watchdog Timer

As the name indicates, it observes the execution of the MC program. It generates ‘RESET’ signal if the
execution process fails.
General Purpose Input and Output (GPIO) using Programmable Interrupt Controllers (PIC)

System on a Chip (SoC) integrated circuits make extensive use of general-purpose I/O (GPIO) pins.
For SoC-based platforms, Windows defines a general abstraction for GPIO hardware, and this
abstraction requires support from the Advanced Configuration and Power Interface (ACPI) namespace.
The GPIO abstraction is supported by the ACPI 5.0 Specification definitions that are listed in this
article.
To verify that your GPIO controller meets all Windows platform requirements, see GPIO Controller
Requirements Checklist.
GPIO controller devices
Windows supports GPIO controllers. GPIO controllers provide a variety of functions for peripheral
devices, including interrupts, input signaling, and output signaling. GPIO capabilities are modeled as a
GPIO controller device in the namespace. The GPIO framework extension (GpioClx) models the GPIO
controller device as being partitioned into some number of banks of pins. Each pin bank has 64 or
fewer configurable pins. The banks in a GPIO controller are ordered relative to their pins' position
within the controller-relative GPIO pin space. For example, bank 0 contains pins 0-31 on the controller,
bank 1 contains pins 32-63, and so on. All banks have the same number of pins, except for the last bank,
which might have fewer. Banks are significant for the ACPI firmware because the firmware must
report the mapping of system interrupt resources to banks, as described in GPIO namespace
objects section below.
Each pin on a bank has a set of parameters (for example, output, level-sensitive interrupt, de-bounced
input, and so on) that describe how the pin is to be configured.
GPIO controllers and ActiveBoth interrupts
A feature of some GPIO controllers is the ability to generate interrupts on both edges of a signal (rising,
or ActiveHigh edges, and falling, or ActiveLow edges). This is useful in a variety of applications,
including the button interface, wherein both button-press events (one edge) and button-release events
(the opposite edge) are meaningful. This feature is referred to as "ActiveBoth".
Logically, ActiveBoth signals have both an asserted and unasserted state, whether they are momentary
assertions (for example, pushbuttons), or indefinitely long assertions (for example, headphone jack
insertions). Edge detection for ActiveBoth interrupts might be implemented in the GPIO controller
hardware (hardware ActiveBoth), or be emulated in the GPIO driver software (emulated ActiveBoth).
Windows requires that GPIO controllers that implement ActiveBoth must use emulated ActiveBoth.
This is required to ensure robust handling of double-edged interrupts for all scenarios. In support of
ActiveBoth emulation, the following hardware requirements apply:

GPIO controllers that support ActiveBoth interrupts must support level-mode interrupts, and must
support re-programming the polarity of the interrupt dynamically at runtime.

To minimize the risk of I/O errors, Windows prefers the use of memory-mapped GPIO controllers
instead of SPB-connected GPIO controllers. In fact, for the Windows Button Array device (PNP0C40),
it is required that the ActiveBoth GPIO interrupts for this device connect to a memory-mapped GPIO
controller, and not to an SPB-connected one. To determine which button interrupts must be ActiveBoth,
see the Button devices section in the Other ACPI namespace objects topic.

To establish a deterministic initial state for ActiveBoth interrupt signals, the Windows GPIO device
stack guarantees that the first interrupt generated after connection of the interrupt by the driver will
always be for the signal's asserted state. The stack further assumes that the asserted state of all
ActiveBoth interrupt lines is logic level low (the ActiveLow edge) by default. If this is not the case on
your platform, you can override the default by including the GPIO controller Device-Specific Method
(_DSM) in the controller's namespace. For more information about this method, see GPIO Controller
Device-Specific Method (_DSM).

PIO namespace objects

GPIO controllers, and the peripherals that connect to them, are enumerated by ACPI. The connection
between them is described using GPIO Connection Resource Descriptors. For more information, see
section 6.4.3.8, "Connection Descriptors", of the ACPI 5.0 specification.
Device identification and configuration objects
A GPIO controller device's ACPI namespace includes the following:
A vendor-assigned ACPI-compliant Hardware ID (_HID) object.
A set of resources consumed (_CRS) object.

A Unique ID (_UID) object, if there is more than one instance of the GPIO controller in the namespace
(that is, two or more namespace nodes that have the same device identification objects).
The GPIO controller's _CRS contains all of the resources (address space for registers, system interrupts,
and so on) consumed by all of the banks in the GPIO controller. The interrupt resource-to-bank
mapping is represented in the order in which the interrupt resources are listed in the _CRS—that is, the
first interrupt listed is assigned to bank 0, the next one listed is assigned to bank 1, and so on. Banks
can share interrupt resources, in which case the interrupt is listed once for each bank connected to it, in
bank order, and is configured as Shared.
GPIO connection resource descriptors
The relationship between peripherals and the GPIO pins to which they are connected is described to the
operating system by GPIO connection resource descriptors. These resource descriptors can define two
types of GPIO Connections: GPIO interrupt connections and GPIO I/O connections. Peripherals
include GPIO connection descriptors in their _CRS for all GPIO I/O and interrupt pins connected. If a
connected interrupt is wake-capable (capable of waking the system from a low-power idle state, then it
must be configured as ExclusiveAndWake or SharedAndWake; for more information, see Device
Power Management.
The descriptors are defined in section 6.4.3.8.1, "GPIO Connection Descriptor", of the ACPI 5.0
specification. The ASL Resource Template Macros for these descriptors are described in section
19.5.53, "GpioInt (GPIO Interrupt Connection Resource Descriptor Macro)", of the ACPI 5.0
specification.
GPIO-signaled ACPI events
ACPI defines a platform event model that enables hardware events in the platform to be signaled and
communicated to the ACPI driver. Windows provides a notification service for communicating
platform events to device drivers. A number of inbox drivers rely on this service to provide support for
ACPI-defined devices, such as Control Method Power Button, LID device, Control Method Battery,
Thermal Zone, and so on. For more information about notifications, see section 5.6.5, "GPIO-Signaled
ACPI Events", of the ACPI specification.
For SoC platforms, GPIO interrupts are used to signal platform events. Any namespace device ("ACPI
Event Source" device) that signals events to its driver using the ASL Notify operator requires the
following:

The namespace node of the GPIO controller to which the ACPI event signal is connected must include
a GpioInt resource for that pin in its ACPI Event Information (_AEI) object (see section 2.4.2.3.1,
"ACPI Event Information (_AEI) Object", below). The GpioInt resource must be configured as non-
shared (Exclusive).

The controller's node must also contain an Edge (_Exx), Level (_Lxx) or Event (_EVT) control method
for each pin listed in the _AEI object.

The ACPI driver handles the listed GPIO interrupt and evaluates the Edge, Level or Event control
method for it. The control method quiesces the hardware event, if necessary, and executes the required
Notify operator on the event source device's namespace node. Windows then sends the notification to
the device's driver. Multiple events can be signaled over the same GpioInt resource if the event control
method can query the hardware to determine which event occurred. The method must then notify the
correct device with the correct notification code.
ACPI Event Information (_AEI) object As previously mentioned, the GPIO controller's namespace
must contain the _AEI object in order to support ACPI events. The _AEI object (see section 5.6.5.2 in
the ACPI 5.0 specification) returns a Resource Template buffer containing only GpioInt descriptors
that signal ACPI events via this GPIO controller. Each descriptor corresponds to one ACPI event
source device and is dedicated to that device (not shared between devices).
GeneralPurposeIO operation regions (OpRegions)
GPIO controllers are often used by platform firmware to support any number of platform hardware
features such as controlling power and clocks, or setting modes on devices. To support the use of GPIO
I/O from ASL control methods, ACPI 5.0 defines a new OpRegion type, "GeneralPurposeIO".
GeneralPurposeIO OpRegions (see section 5.5.2.4.4 of the ACPI 5.0 specification) are declared within
the namespace scope of the GPIO controller device whose driver will handle the I/O.
GeneralPurposeIO Field declarations (see section 5.5.2.4.4.1 of the ACPI 5.0 specification) assign
names to GPIO pins that are to be accessed within a GeneralPurposeIO OpRegion. GpioIO Connection
Resources (see section 19.5.53 of the ACPI 5.0 specification) are used within the Field declaration to
specify the pin number(s) and configuration for a particular Field reference. The total number of named
field bits following a connection descriptor must equal the number of pins listed in the descriptor.

Fields in an OpRegion can be declared anywhere in the namespace and accessed from any method in
the namespace. The direction of accesses to a GeneralPurposeIO OpRegion is determined by the first
access (read or write) and cannot be changed.

General-purpose I/O (GPIO) - Windows drivers | Microsoft Docs

Analog-to-Digital and Digital-to-Analog Conversion using ATMEL microcontrollers

ADC Setup The basic steps in setting up the ADC module to do

conversions are these.

1. Configure the REFS[1:0] bits to select the high reference voltage

to use. Using AVCC is recommended.

2. Set or clear the ADLAR bit depending on whether you are want to
use 10 or 8 bit conversion results.

3. Configure the MUX[3:0] bits to select the input channel to be used.

4. Configure the ADPS[2:0] bits to select the clock prescaler value.

5. Set the ADEN bit in ADCSRA to a one. This enables the ADC and
you’re now ready to initiate a conversion. If using interrupts also
do these steps.

6. Write an interrupt service routine (ISR) for the ADC_vect

interrupt.

7. Set the ADIE bit in ADCSRA to a one to enable the module to

interrupt.

8. Enable global interrupts with the sei() function call.

ADC Conversions Using Polling To do conversions using polling, do
these steps.

1. Set the ADSC bit in ADCSRA to a one. This starts a conversion.

2. Go into a loop checking the state of the ADSC bit. As long as it

is still a one the conversion is in progress. Once that bit becomes a
zero the conversion is complete.

3. Read the result from ADCH (8-bit) or ADC (10-bit).

ADC Conversions Using Interrupts To do conversions using interrupts,

do these steps.

1. Set the ADSC bit in ADCSRA to a one. This starts the first
conversion.

2. Go into a loop doing nothing or perform some other task to wait

until the interrupt occurs.

3. In the ISR, read the result from ADCH (8-bit) or ADC (10-bit). If
you wish to start another conversion right away this can be done in
the ISR by setting the ADSC bit again

ADC.pdf (usc.edu)

Serial Communication using Arduino-based microcontrollers