4.4 EMITTER-STABILIZED BIAS CIRCUIT ‘The de bias nctwork of Fig. 417 consins an eater esstor to improve the stbilty Jove over that ofthe fixed bias coniguraion Tho improved stabi wil be damon strated trough a aumercal example later inthe secuon. The analysis wil be pot- formed by fst examining the base-emite lap ad tho using the rss 1 inte tigate the collector emit loop Lk wo 1 F fa jase-Emitter Loop ‘The base-emitter loo ofthe network of Fig 4.17 ean be tedawn a showa in Fig 44.18. Wri Kirche’ voltage Iw around the indicated oop inthe clockwise ie rection wll oul inthe flowing equate ee ~ ally Vas ~ tlle = as Recal from Chap $that t= (B+ 419) Swbstoting foe ia Eq (4.15) wil result in Yoo~ lata ~ Var ~ (B+ Disk = 0 Grouping terms wil then provide the Following lll * (B+ WR) + Voom Fax = 0 Maltpying through by (—1) we have lly +B * VR~Voo + Vas 0 with alts + (B+ VR) = Veo Vax ‘and solving for dy gives pails an SR Bt Re Now that she ony ference between this equation for Fy aed tat obi Tor he Fixed-bis cntauration isthe term (8 + 1 "Thee isan interesting result that canbe dtived ftom Eq. (4.17) ithe equation fs used to sketch a saries network that would rei inthe same equsion. Such i 153gee i9 sewnideret Lt Figs 420, Ree pte te Eg 2 cata 154 _—— the cate forthe network of Fig 4.19, Solving forthe cute Za wil esl the sxe ‘equation obaind shove. Note tit aside fom the base-emitter voltage Vp the resistor Ry Is refleced back tothe input hake ciclt by a facoe (8+ 1). her words the emiter resistor, which is par ofthe colecior-emiter Toop, “appears 35" (B+ Ike in the base-emitter lop. Since Bi ypcally 80 or sow, the emer ee- sistor appears tobe a great deal larger inthe base circuit. fn ener therefore for the configuration at Fig 420, Re (B+ Die (45) ‘Equation (4.18) 8 one tha wil prove wt ho analysis 9 follow. He ett provides fly easy way t remember Ea (4.17). Using Ohm’s lw, we know that ie eurent through @aysom it the voltage vied by the retane ofthe cru, For the base-emitter eeuit the nt voltage is Yee Vp. The resistance levels are 2 pus Ry eflced by (B+ 1). The ves Eq (417), Collector-Emitter Loop. ‘The collecor-emiter loop is redrawn in Fig. 421. Writing Kirchhof's voltage lw {rhe indicated loop inthe clockvise ction wil suit in $heRe + Ves * leo Voo 0 and growpng ers ges Ver ~ Veo feo + Ra) = 0 Substaing fe = and Veg = Voom Tele Rah 419) ‘The sngl-sabscrpt voltage Ve the voltage fom emir to grownd ad is d= venmined by aay while the voltage fom collector to ground can be determined from and Ve= Ven Ve ay o Ve= Veo heRe 422) “The voltage at the base with sespect 1 around can be determined from Va= Voo~ tok 423) o Vas Van Ve a9 Chapter 4 BC Binng BI4 For the emir bias network oP Fig. 422, detemine: EXAMPLE 44 (8) Jp ®t (0) Few Ne ay © Ve te (8) Vac eos wae owe 422 Enact Bithoc forbanpe Solution (0) Fa. (17 y= Pee tae = 28 Bet B+ DR BOR +S 193 = BY aaa ps (0) te= Bl = (50140. pay = 201 ma, (0) FQ. AIDE Vor = Voo~ fel Be) = 20V— (201 maj WM + 1 kA) = 20 —603.¥ =19Tv @ Ye= Veo tee = 20V~ 201 male ko 1598 © Wee = 1598 201V or Ve Iie= lee (2.01 mat KO) 201y Ve= Vue Ve o7v+201v =anv ©) Vac Va~ Ye =271V~1598V = 1127 Y (oversebiased a equited) 20v-4nv Yee nerv A Emer Sted Bin Cit 155Improved Bias Stability “The ation of he emiterressior to the de lak ofthe BIT proves improved st bility, thar, the de bias eurats and voltages romain clsce to where thoy Wate Sct by the eioui whan outside conditions, such a tempore, and tamssor bela, ‘change. While mathematical analysis is provided in Section 412, some comparison ‘ot the inprovement canbe obsined ax damonstraed by Example 45, EXAMPLE 45, ue 423 arming 156 Propare «able and compare ie bias voltage and eurens oF the ecu of Figs. 4.7 tnd Fig. 422 forthe given vale of B= 50 and fora new value of f= 100, Com Pare the changes in Jc and Wer forthe same increase in Solation Using the resus calculated ia Example 4.1 and then epeaing fora value of B= 100 ys the following: 2 re “Tho BFF collector eumon is sen wo ehange by 10% due co the 100% change in the value of isthe sume and Vy decreased by 7 ‘Using the raul exeulaod fo Example 44 end then sopeting fora value of| (A= 100, we ve the following: ’ oo tm Now the BFT collector cure inteases by about 81% duc to the 108% inerese in. [Notice that Jy decrease, helping mail the value of Jeo" atleast eeduing the ‘overall change in Je due tote change in. The change in Vox has dropped t aout 3590 The network of Fig. 4.22 therefore move stable than tht of Fig 4.7 fo the same change in Saturation Level “The collector saturation love of maximum collstr current for an eter bis de- sign can be determined using the same approach applic to the fne-ies configura tion: Apply short ete beoween the clletor-emiertenminals a show it 5. 4.238 and calelate the resulting collector current. For Fig. 423 ln (42) “The skdkio ofthe emit resistor reduces the collector saturation lve Below that binned with a faedebas configuration using the same collector reir Chapter 4 BC Binng BI4 Determine the saturation errent for the network of Example 4 EXAMPLE 46 Solution pepe Res ke 20v___ av Te = TRH” 3K = 667 A which is about twice the level off, for Example 4 Load-Line Analysis, ‘The lode analysis ofthe emite-bies network is oly slighty diferent fom that ‘encountered for the fxd-bias configuration. The level of Ip as determined by Ea. {GLI7) defines the level of Jy om the characterises af Fig. 424 (denoted Ip, Ty Pee fa adn re ‘The collector-emiter loop equation that dons the loud line isthe following Ver Vee lee * Re) Choosing fe = 0 mA gives Yea= Vetiemomn 426 «obtained forthe fincas configuration. Choosing Fe 0 V gives Foe. 427 HO Ret Ralrartv an 1 shonin Fig 424, Different levels of J, will of course, move the Q-polnt up or ‘down te load line. 4.5 VOLTAGE-DIVIDER BIAS Jn the previous bias configurations the bias cunt J. and vole Ve, were fae tion ofthe curtent gin (s) ofthe transistor However, since fis temperature sensi tive, especially for slcos traitors, and the actual value of beta usally not well ‘etined, i woud be desirable to develop a bis cicuit that is less dependent, or in AS. ole Dine st