722 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 49, NO.
3, AUGUST 2007
value for a reverberation chamber with an electrically large stirrer.
The method proposed in this paper suggests that the chamber can be
successfully operated below this frequency, providing some careful de-
cisions are made regarding the stirrer design and the size of the working
volume.
Additional work to address the application of this approach to cham-
bers loaded with an EUT would be potentially helpful in further as-
sessing this approach.
REFERENCES
[1] M. O. Hatfield, M. B. Slocum, E. A. Godfrey, and G. J. Freyer, “Investi-
gations to extend the lower frequency limit of reverberation chambers,” in
Proc. IEEE int. Symp. Electromagn.Compat. 24–28, 1998, vol. 1, pp. 20–
23.
[2] M. L. Crawford and G. H. Koepke, “Design, evaluation and use of
a reverberation chamber for performing electromagnetics susceptibil-
ity/vulnerability measurements,” Nat. Bur. Tech. Note, vol. 1092, Apr.
1986.
[3] L. R. Arnaut, “Operation of electromagnetic reverberation chambers with
wave diffractors at relatively low frequencies,” IEEE Trans. Electromagn.
Compat., vol. 43, no. 4, pp. 637–653, Nov. 2001.
[4] H.-J. Asander, G. Eriksson, L. Jansson, and H. Akermark, “Field unifor-
mity analysis of a mode stirred reverberation chamber using high reso-
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Compat., 2002, pp. 285–290.
[5] IEC 61000-4-21, Electromagnetic Compatibility (EMC)—Part 4-21: Test-
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[6] J. Clegg, A. C. Marvin, J. F. Dawson, and S. J. Porter, “Optimization of
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[7] D. A. Hill, “Boundary fields in reverberation chambers,” IEEE Trans.
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[8] L. R. Arnaut and P. D. West, “Electromagnetic reverberation near a per-
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[9] D. I. Wu and D. C. Chang, “The effect of an electrically large stirrer in
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no. 2, pp. 164–169, May 1989.
Analysis of Via Capacitance in Arbitrary Multilayer PCBs
Miroslav Pajovic, Jinghan Yu, and Dragan Milojkovic
Abstract—The signal layer transitions at regions of multilayer printed
circuit boards, where high-speed signal lines switch between two signal
layers, may affect the board circuit’s signal integrity and electromagnetic
compatibility. This study has been focused on the analysis and extraction of
values of parasitic capacitance of various designs of through-hole and micro
vias as signal layer-changing devices, which are common in practice. The via
capacitance is analyzed conceptually by using lumped circuit models for
electrically short vias, numerically by the computational calculations based
on the transmission line modeling method, and experimentally by labora-
tory measurements using a vector network analyzer and an LCR meter.
Index Terms—Lumped circuit models for vias, signal layer transitions
in multilayer printed circuit boards (PCBs), signal line discontinuities, via
parasitics.
Manuscript received February 3, 2006; revised December 12, 2006. This
work was supported by the EMC Compliance Engineering Group of DSSTG of
Cisco Systems, Inc.
The authors are with Cisco Systems, Inc., San Jose, CA 95134 USA
(e-mail: mpajovic@cisco.com; jinyu@cisco.com; dmilojko@cisco.com).
Digital Object Identifier 10.1109/TEMC.2007.902382
0018-9375/$25.00 © 2007 IEEE
I. INTRODUCTION
Signal integrity and electromagnetic interference (EMI) investiga-
tions of modern high-speed digital circuits present serious challenges
for multilayer printed circuit board (PCB) designs. With ever-
increasing clock frequencies, data rates, and integrated circuit densities
and decreasing signal rise/fall times, signal integrity of PCB cir-
cuits require careful considerations. The signal lines need to be well
impedance-matched to their drivers, loads, or to other signal lines in
order to have minimal effects from discontinuities. One of the typical
line discontinuities in high-density PCBs are signal layer transitions or
interlayer connections, made by the vias. Intrinsic to all vias are their
parasitic capacitances and inductances that create discontinuities in the
signal lines. These discontinuities with presence of the PCB resonance
effects may lead to additional signal delay, signal reflections, parasitic
electromagnetic propagation, and resonance effects in PCBs that con-
sequently lead to signal distortions, crosstalk, and EMI problems as
discussed in [1]–[6].
In addition to the via inductance and PCB resonances, the via ca-
pacitance may have negative impact on signal integrity of high-speed
digital signals in multilayer PCBs, especially when transmission lines
have more signal vias, as explained in [1, Ch. 5]. Other useful analyses
of via capacitance are given in [7]–[9]. In this paper, we have shown
the via capacitance models for various physical via designs, which
are common in industry, with variety of via radius, via lengths, via
clearance to the board planes, and number of stacks per via length.
Furthermore, we have used the method for the extraction of the via
capacitance values that is based on a concept of the lumped circuit
models for the signal via.
These via models and via capacitance extraction methods are con-
firmed by the transmission line modeling (TLM) and simulation
method, and by laboratory measurements using a vector network ana-
lyzer (VNA) and LCR meter.
II. PHYSICAL AND CIRCUIT MODELS FOR VIAS
For typical multilayer PCB structures with a signal line transition,
the equivalent hybrid circuit is shown in Fig. 1(a). Here, Csvt is the total
via capacitance that includes the capacitances of the signal via body,
via pads, and parts of the signal line located on the signal layers next
to the signal via. Lsvt is the inductance of the signal via including the
inductances of the signal line parts next to the signal via in the antipad
via area. The [Zpcb ] represents the distributed network associated to



the PCB, which acts as a parallel-plane resonator. The plot of the
magnitude of the impedance
Ẑ11
of the circuit in Fig. 1(a), obtained
by the TLM method (a dashed curve) and by the VNA measurements
(a solid curve), is shown in Fig. 1(b).
The simulations and laboratory measurements are performed on
the test PCB with the dimensions a × b ×H = 50 mm × 50 mm ×
2.7 mm. The signal via is one of the typical industry samples that has
the following parameters: the number of signal via pads is 3, the via
length is H = 2.7 mm, the via body radius is r = 0.15 mm, the via pads
radius is Rp = 0.29 mm, and the via antipad radius is Rap = 0.42 mm.
The relative dielectric constant and the loss tangent of the PCB substrate
at 10 GHz are 3.9 and 0.016, respectively.
The physical via model, which is formed by a signal via and a
ground via spaced by 25 mm, and the VNA setup for measuring the
S21 parameters of the open-ended signal via, are shown in Fig. 2. The
actual plot of the impedance |Ẑ11 | was obtained by measuring the
S21 parameter, and by converting this parameter to the impedance Ẑ11
using (1) as
Ŝ21 50 + jωLp
Ẑ11 ≈ . (1)
2 1 − Ŝ21
IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 49, NO. 3, AUGUST 2007
Fig. 1. (a) Hybrid via circuit model. (b) TLM-simulated (dashed curve) and
VNA-measured (solid curve) impedance magnitude of the open-ended signal
via.
Lp is the inductance of the VNA probes that is assumed to be zero
after the VNA calibration. The measurement method of the impedance
Ẑ11 of parallel plane structures is given in [10].
Propagation and cavity effects inside of the parallel-plane PCB struc-
ture produce multiple resonances inside the PCB that are shown in the
plot of Fig. 1(b). Starting from ∼ 3 GHz and going to ∼ 9.5 GHz, the
resonance peaks belong to the even resonance modes: (2, 0)/(0, 2), (2,
2), . . . , (6, 2)/(2, 6). Analysis of the PCB cavity effects on signal lines
performance will be the topic of our future work.
For low frequencies, below the PCB resonances, the PCB exhibits
the quasi-static behavior and behaves as a parallel-plane capacitor Cp .
The typical value of ground via inductance is in the order of nanohenry
or less. Consequently, the circuit model in Fig. 1(a) will look as in
Fig. 3(a). At low frequencies for common industrial PCBs, where the
via inductance and the interplane PCB capacitance dominate the via
capacitance (i.e., ωLv << 1/(ωCsvt ) and 1/(ωCp )  1/(ωCsvt ),
the equivalent circuit in Fig. 3(a) leads to the total via capacitance
Csvt , as shown in Fig. 3(c).
A. Extraction of Via Capacitance
At low frequencies, we can neglect the influence of PCB dielectric
losses on the via impedance. Therefore, below 1 GHz in the plot of
Fig. 1(b), the impedance of the signal via relates mostly to the total
signal via capacitance Csvt , and the magnitude of this impedance may
723
Fig. 2. Setup for measuring the via impedance Z 11 (the ground pins of the
probes P1 and P2 are shorted together, and are connected to the PCB top ground
plane).
Fig. 3. (a)–(c) Evolution of the quasi-static via capacitance model.
be expressed by
1
|Ẑ| = . (2)
2πf Csvt
We used this equation for extracting the total via capacitance values
from the impedance |Ẑ| below 1 GHz obtained by TLM calculations.
III. PRACTICAL VIA MODELS, VIA CAPACITANCE COMPUTATIONS,
AND LABORATORY MEASUREMENTS
To obtain the values of via capacitance from practical via models,
an experimental platform was designed specifically for this research
work. We made laboratory measurements on the platform by VNA and
LCR meter. Also, we have performed the computational calculations
of the impedance |Ẑ| by the TLM software, and using (2), we have
extracted the signal via capacitance values.
A. Measurement of Via Capacitance
We have obtained measurement of the via capacitance by the VNA,
Agilent N5230A PNA, and by the LCR meter, Protek Z9218. The via
capacitance is directly read out by the VNA, in Smith-chart-impedance
mode at 100 MHz and by the LCR meter at 100 kHz. The measurements
are performed at the experimental platform with 17 test vehicles with
dimensions 50 mm × 50 mm, and the corresponded measurement
results are given in Tables I–IV.
B. Initial Model for Signal Via
For cases of signal lines with a signal layer transition, the different
via physical models will be derived from the initial via model shown in
724 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 49, NO. 3, AUGUST 2007
TABLE I
VARIATION OF THE NUMBER OF VIA PADS AND THE VIA LENGTH
TABLE II
INDUSTRIAL VIA SAMPLES WITH THREE PADS
FOR STRIPLINE LAYER TRANSITIONS
TABLE III
VARIATION OF THE RADIUS OF THE VIA ANTIPAD R ap
TABLE IV
VARIATION OF THE NUMBER OF REFERENCE PLANES ALONG THE VIA
Fig. 4, by varying the number of pads n on the via, radiuses r, Rp , Rap ,
the via height H, and the number of reference planes N . The signal via
model, which is implemented in the PCB with dimensions 50 mm × 50
mm × 2.7 mm, is one of the typical industry samples, and has the fol-
lowing parameters: r = 0.15 mm (6 mils), Rp = 0.29 mm (11.5 mils),
Rap = 0.42 mm (16.5 mils), H = 2.7 mm (105 mils), n = 14, and
N = 12. The PCB dielectric thicknesses h and h1, are 0.254 mm
(∼10 mils) and 0.13 mm (∼5 mils), respectively. The thickness of the
reference planes, signal lines, and via pads is 0.0165 mm (0.65 mils
or 0.5 ounce). The parts of the signal line next to the signal via are
0.127 mm (∼5 mils) wide and (Rap − Rp ) = 0.13 mm long.
In our test models, relative dielectric constants and loss tangent
of the PCB substrates between reference planes differ through the
Fig. 4. PCB with the 14-pad signal via.
Fig. 5. PCB with the three-pad signal via.
PCB stackup, and the resulting average relative dielectric constant is
εavr ≈ 4, and the average loss tangent is ≈ 0.02 at 500 MHz. We used
material vendor numbers to estimate the average values of relative
dielectric constant and loss tangent for PCB models.
C. Effects of Via Physical Parameters on Via Capacitance
and Computational and Measurement Results
The effect of the via pad on via’s capacitance was analyzed by
reducing the number of pads in the via model, shown in Fig. 4, from a
total of 14 to 2 via pads, as shown in Fig. 2. All other via parameters such
as r, Rp , Rap , H, and N stayed unchanged. TLM method calculation
results and VNA and LCR measurement results of the via capacitance
for 14, 4, and 2 pads are shown in Table I.
The effect of via height on via capacitance was analyzed by reduc-
ing the height of the through-hole via in Fig. 5, while the other via
parameters stayed unchanged. After reducing the height from H =
2.7 mm (105 mil) to H1 = 0.3 mm (12 mil), the corresponding micro
via is shown in Fig. 6. TLM method calculation results and VNA and
LCR measurement results of the micro-via capacitance are presented
in Table I.
The effect of via body radius r, via pads radius Rp , and via antipad
radius, Rap , was analyzed on the via model shown in Fig. 5, with
several typically industrial via sizes for the three-pad via, by changing
the parameters r, Rp , and Rap while other model parameters stayed
unchanged. The corresponding TLM method calculation results and
VNA and LCR measurement results of via capacitance are shown in
Table II.
IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 49, NO. 3, AUGUST 2007
Fig. 6. PCB with the micro signal via.
Fig. 7. Two-layer PCB with the three-pad signal via.
The effect of via antipad radius Rap , on via’s capacitance was ana-
lyzed by changing the Rap of the 3-pad-via also in Fig. 5, with standard
parameters r = 0.15 mm (6 mils) and Rp = 0.29 mm (11.5 mils). The
corresponding TLM method calculation results and VNA and LCR
measurement results are shown in Table III.
The effect of the density of reference planes, which the via passes in
the PCB, on the via capacitance was analyzed by gradually reducing the
number of reference planes from 12 to 2 on the three-pad-via model.
After the removal of 10 reference planes, the last via model, with only
two reference planes, is shown in Fig. 7. The corresponding TLM
method calculation results and VNA and LCR measurement results for
via capacitances are shown in Table IV.
D. Analytical Estimation of Via Capacitance
In general, by increasing the number of reference planes along a
via, the via structure approaches a coaxial form. Practically, the via
structure will reach the coaxial form when the spacing between the
adjacent PCB reference planes is small and comparable to the spacing
between via and the reference planes, i.e., (Rap −r). For a numerical
comparison, the capacitance of the related coaxial structure, calculated
approximately by the coax-form (3a) and (3b), are added in Tables I–IV
H [2] C. Schuster and W. Fichtner, “Parasitic modes on PCBs and their effects on
Ccoax = 2πεr ε0  R ap  (3a)
ln Rp
H power/ground plane resonance coupling and via neck effect,” in Proc.
Ccoax = 2πεr ε0  R ap  (3b)
ln r [4] J. Kim, J. Kim, M. D. Rotaru, K. C. Chong, and M. K. Iyer, “Via and
where εr and ε0 are the relative dielectric constant of PCB substrate
and the dielectric constant in air, respectively. H, Rap , Rp , and r
are the via length, the radius of via antipad, the radius of via pad,
725
and the radius of via body. The coax-form (3a) is used when the ca-
pacitance of via pads dominates the capacitance of via body—the case
when via has a maximized number of pads. The coax-form (3b) is used
when the capacitance of via body dominates the capacitance of via
pads—the case when via has a minimized number of pads.
Also, in the last row of Table I, we added values of via capacitance
calculated by [1, Eq. (5.1), Ch. 5]. We may see that for the long via
with the maximized number of via pads (14), when the capacitance of
via pads dominates the capacitance of via body, then (5.1) in [1] gives
solid results from practical engineering standpoints. But, for the long
via with the minimized number of via pads (2 to 4), the coax-form
equation gives pretty more accurate results than (5.1) in [1]. This is
because the capacitance of via body dominates the via pad capacitance
for vias with the minimized number of via pads. For short (micro) vias,
both the equations give solid results. In this case, we used (3a) because
the capacitance of via pads dominates the capacitance of via body.
IV. CONCLUSION
In addition to the via inductance and PCB resonant cavity effects, the
signal via parasitic capacitance in high-speed signal lines may cause
signal integrity problems at high-speed PCB circuitries. This work
analyzed vias and signal layer transitions in arbitrary multilayer PCB
structures with emphases on the via capacitance that can not be ignored
in high-speed PCB design.
As it was shown in this paper, many physical and electrical parame-
ters of the PCB and signal vias have considerable influence on the via
parasitic capacitances. The negative effect of via capacitance cannot be
neglected, but it can be minimized by controlling relevant via and PCB
parameters. We analyzed a variety of via designs and their contribution
to the via capacitance. The right approach to minimize the capacitance
of the through-hole via is first to reduce the number of via pads (i.e., to
eliminate the unused via pads). Minimization of the via capacitance by
increasing clearance between the via and PCB reference planes is not
always an effective solution due to the requirement that the reference
planes should be solid planes for the associated high-speed signal lines,
which are passing between the vias. However, the most effective solu-
tion to minimize the via capacitance is using micro via constructions
(short vias), but this solution is sometimes limited by other factors such
as higher PCB production cost.
ACKNOWLEDGMENT
The authors would like to thank J. Fisher, Engineering Manager
from Cisco Systems, Inc., San Jose, CA, for supporting successful
laboratory measurements; and F. Centola, EMC Application Engineer
from Flomerics, Inc., Santa Clara, CA, for great help on the TLM
computational modeling and simulations.
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