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PERFORMANȚE
1.We execute a program on a computer with processor A, such that 40% of the
instructions are arithmetic, 30% are load/store, 20% are branches, and 10% are
compares. The CPIs are: CPI_arithmetic = 4, CPI_load/store = 3, CPI_branch = 2,
and CPI_compare = 1 [clock cycles). Processor A has a clock cycle time of 0.5 ns.
Then, we replace processor A with processor B, such that the CPI_arithmetic is
reduced to 2 clock cycles and CPI_branches is reduced to 1 clock cycle, at the
expense of degrading the clock cycle time with 50%. Check the best
approximation values for MIPS_processor_A and MIPS_processor_B.
a. MIPS_processor_A = 660.75
b. MIPS_processor_B = 670.84
C. MIPS_processor_A = 666.7
d. MIPS_processor_A = 665.3
e. MIPS_processor_B = 666.7

2.We compare two computers, A and B, both running the same workload with
3000 instructions and 1.2 memory accesses per instruction. Computers A and B
are identical (i.e., CPlideal=2 for both) except the cache (the Miss rate is 8% for A
and 5% for B) and the clock cycle time (0.5 ns for A, degraded with 5% for B). The
Miss penalty is dictated by the main memory, and is 12 ns for both computers.
Check the correct performance parameter values for computers A and B.
a. AMATB = 1.75 ns
b. CPUtimeB = 8 us
C. CPUtimeB= 5.205 us
d. AMATA = 1.46 ns
e. CPUtimeA = 6.456 us

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????3.We compare computers A and B, identical except the cache and the clock
cycle time (i.e., the CPlideal is identical, the clock cycle time is 0.5 ns for A and
0.55 ns for B, the miss rate is 8% for A and 6% for B). If the absolute miss penalty
is 10 ns and the memory references per instruction are 1.3, check the correct
statements.
a. CPUtimeA= CPUtimeB for CPlideal = 4.498
b. CPUtimeA= CPUtimeB for any CPlideal
C. AMATB = 1.177 ns ……………..AMATB=1,15NS
d. AMATA = 1.177 ns
e. CPUtimeA = CPUtimeB for CPlideal = 3.487

4.We execute a program using compiler A, such that 50% of the instructions are
arithmetic, 20% are branches, 20% are loads, 10% are stores, and the total
number of instructions is 1200. The CPIs are: CPI arithmetic = 4, CPI branch = 3,
CPI_load = 2, and CPL_store = 1 clock cycles. The machine executing the program
has a clock cycle time of 5 ns. Then, on the same machine and for the same
program, we pass to compiler B that eliminates 1/4 of load instructions. Check
the correct values for CPUtime compiler A and CPUtime_compiler_A.
a. CPUtime compiler_B = 16.3 us
b. CPUtime_compiler_A = 16 us
c. CPUtime_compiler_B = 18 us
d. CPUtime_compiler_A = 19.3 us
e. CPUtime_compiler_A = 18.6 us

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5.We execute a program on computer A and with the following statistics: 2000
instructions with 60% arithmetic instruction. 20% load/store instructions, and
20% other instructions. For this program with 2000 instructions. we measure CPI
arithmetic = 5, CPI_load/store = 3. and CPI other = 2 clock cycles. Computer A
has a clock cycle time of 0.25 ns. By changing the processor with a new one,
having a slightly different instruction set. we get computer B. When running the
same program with the same compiler, we get the same statistics as for
computer A. However, the measurement of CPL renders different results for the
arithmetic instructions, namely 2/3 of of these instructions have a reduced CPI
of 4, while the rest of 1/3 have the same CPI of 5. Also, the clock cycle time of
computer B is degraded with 20%. Check the exact values of
CPUtime_computer_A and CPUtime_computer_B.
a. CPUtime_computer_A = 4 us
b. CPUtime_computer_A = 2 us
C CPUtime_computer_B = 2.16 us
d. CPUtime_computer_B = 2.36s
e CPUtime_computer A = 3 us

6.We compare two computers, A and B, both running the same workload with
1000 instructions and 1.8 memory accesses per instruction. Computers A and B
are identical (i.e., CPI deal=4 for both) except the cache (the Miss rate is 10% for
A and 8% for B) and the clock cycle time (0.25 ns for A, degraded with 20% for
B). The Miss penalty is dictated by the main memory, and is 10 ns for both
computers. Check the correct performance parameter values for computers A
and B.
a. AMATB = 1.116 ns
b. AMATA = 1.25 ns
c. CPUtimeA = 1.8 us
d. CPUtimeB = 2.95 us
e. CPUtimeA = 1.85 us

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7.We execute a program using compiler A, such that 50% of the instructions are
arithmetic, 20% are branches, 20% are loads, and 10% are stores. The CPIs are:
CPI_arithmetic = 4, CPI_branch = 3, CPI_load = 2, and CPI_store = 1 clock cycles.
The machine executing the program has a clock cycle time of 5 ns. Then, on the
same machine and for the same program, we pass to compiler B that eliminates
1/4 of load instructions. Check the best approximation values for
MIPS_compiler_A and MIPS_compiler_A.
a. MIPS_compiler_A = 64.516
b. MIPS_compiler_A = 34.418
c. MIPS_compiler_B = 66.537
d. MIPS_compiler_B = 56.673
e. MIPS_compiler_A = 48.438

8.We compare two computers, A and B, both running the same workload with
2000 instructions and 1.5 memory accesses per instruction Computers A and B
are identical (i.e., CPI dea =5 for both) except the cache (the Miss rate is 5% for A
and 3% for B) and the clock cycle time (0.5 ns for A, degraded with 10% for B).
The Miss penalty is dictated by the main memory, and is 15 ns for both
computers. Check the correct performance parameter values for computers A
and B.
a. CPUtime = 8.5 us
b. AMATB = 1.3 ns
c. CPUtimeB = 6.886 us
d. AMATB = 1.012 ns ………………….AMATB=1 ns
e. AMATA = 1.3 ns

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9.We execute a program on a computer with processor A, such that 60% of the
instructions are arithmetic, 20% are load/store, 20% other instructions. The CPIs
are: CPI_arithmetic = 5, CPI_load/store = 3, CPI_other = 2 clock cycles. Processor
A has a clock cycle time of 0.25 ns. By changing the processor with a new one,
having a slightly different instruction set. we get computer B. When running the
same program with the same compiler, we get the same statistics as for
computer A. However, the measurement of CPI renders different results for the
arithmetic instructions, namely 2/3 of of these instructions have a reduced CPI
of 4, while the rest of 1/3 have the same CPI of 5. Also, the clock cycle time of
computer B is degraded with 20%. Check the best approximation values of
MIPS_computer_A and MIPS_computer_B.

a. MIPS_processor_B= 925,926
b. MIPS_processor_B = 1200
C. MIPS_processor_A = 1200
d. MIPS_processor_B= 925,931
e. MIPS_processor_A = 1000

10.We compare computers A and B, identical except the cache and the clock
cycle time (i.e., the CPlideal is identical, the clock cycle time is 0.25 ns for A and
0.3 ns for B, the miss rate is 10% for A and 8% for B). If the absolute miss penalty
is 6 ns and the memory references per instruction are 1.2, check the correct
statements.
a. CPUtimeA= CPUtimeB for CPlideal = 2
b. CPUtimeA= CPUtimeB for CPIideal=2.9
C. AMATB = 0,75 ns
d. AMATA = 0,85 ns
e. CPUtimeA = CPUtimeB for CPlideal = 2,88

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11.We execute a program on a computer with processor A, such that 40% of the
instructions are arithmetic, 30% are load/store, 20% are branches, and 10% are
compares. The CPIs are: CPI_arithmetic = 4, CPI_load/store = 3, CPI_branch = 2,
and CPI_compare = 1 [clock cycles). Processor A has a clock cycle time of 0.5 ns.
Then, we replace processor A with processor B, such that the CPI_arithmetic is
reduced to 2 clock cycles and CPI_branches is reduced to 1 clock cycle, at the
expense of degrading the clock cycle time with 50%. Check the best
approximation values for MIPS_processor_A and MIPS_processor_B.
a. CPUtimeB=1 us
b. CPUtimeB=1.5 us
C. CPUtimeA=1.5 us
d. CPUtimeA=1800 ns
e. CPUtimeA=1.75 us

12.We compare computers A and B, identical except the cache and the clock
cycle time (i.e., the CPlideal is identical, the clock cycle time is 2 ns for A and 1.5
ns for B, the miss rate is 5% for A and 4% for B). If the absolute miss penalty is 20
ns and the memory references per instruction are 1.5, check the correct
statements.
a. AMATB = 2.5 ns
b. CPUtimeA > CPUtimeB for any CPIideal
C. CPUtimeA = CPUtimes for CPlideal = 0.5 clock cycles
d. CPUtimeA = CPU time for CPlideal = 1.1 clock cycles
e. AMATA = 3 ns

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MEMORII
1.The main memory size is 4 GiB, the addresable unit is the byte, one word is on
64 bits, one block has 16 words. The cache is direct mapped and has a data size
of 8 KiB. Check the false statements regarding the memory system described
here:
a. Address 0013C9A1nex in the main memory maps at index 19ten in the cache.
b. Address 0013C9A1 hex in the main memory maps at index 103ten in the
cache.
C. The difference between the total cache size and the cache data size is > 0.25
kiB.
d. Address 0013C9A1 ne in the main memory maps at index 73ren in the cache.
e. The difference between the total cache size and the cache data size is < 0.25
KiB.

2.The main memory size is 16 GiB, the addresable unit is the word, one word is
on 4 bytes, one block has 8 words. The cache is 4-way set associative and has a
data size of 64 KiB. Check the true statements regarding the memory system
described here:
a. The index field has 9 bits.
b. The index field has 10 bits
c. The tag field has 20 bits.
d. The word offset field has 3 bits.
e. The byte offset field has 2 bits.

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3.The main memory size is 32 GiB, the addresable unit is the word, one word is
on 64 bits, one block has 8 words. The cache is 8-way set associative and has a
data size of 128 KiB. Check the true statements regarding the memory system
described here:
a. The word offset field has 2 bits.
b. The tag field has 21 bits.
c. The index field has 8 bits.
d. There is no byte offset
e. The tag field has 20 bits.

4.The main memory size is 16 GiB. the addresable unit is the word, one word is
on 4 bytes, one block has 8 words. The cache is 4-way set associative and has a
data size of 64 KiB. Check the true statements regarding the memory system
described here:
a. The index field has 9 bits.
b. The tag field has 20 bits.
c.The byte offset field has 2 bits.
d. The word offset field has 3 bits.
e. The index field has 10 bits

5.The main memory size is 4 GiB, the addresable unit is the byte, one word is on
64 bits, one block has 16 words. The cache is direct mapped and has a data size
of 8 KiB. Check the false statements regarding the memory system described
here:
a. The index field has 8 bits
b. The tag field has 21 bits.
c. The tag field has 20 bits
d. The tag field has ..
e. The byte offset field has 3 bits.

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6.The main memory size is 32 GiB, the addresable unit is the byte, one word is
on 64 bits, one block has 8 words. The cache is 2-way set associative and has a
data size of 32 KiB. Check the true statements regarding the memory system
described here:
a. The tag field has 21 bits.
b. The tag field has 20 bits.
c. The index field has 8 bits.
d. The byte offset has 3 bits
e. The index field has 9 bits.

7.The main memory size is 32 GiB, the addresable unit is the word, one word is
on 64 bits, one block has 8 words. The cache is 8-way set associative and has a
data size of 128 KiB. Check the false statements regarding the memory system
described here:
a. Address 014AC4B2hex in the main memory maps at index 150ten in the cache.
b. Address 014AC4B2hex in the main memory maps at index 63ten in the cache.
C. The difference between the total cache size and the cache data size is > 8 kiB.
d. Address 014AC4B2hex in the main memory maps at index 126ten in the
cache.
e. The difference between the total cache size and the cache data size is < 8KiB.

8.The main memory size is 16 GiB. the addresable unit is the word, one word is
on 4 bytes, one block has 8 words. The cache is 4-way set associative and has a
data size of 64 KiB. Check the false statements regarding the memory system
described here:
a. Address 09C3A6D2hex in the main memory maps at index 68ten in the cache.
b. Address 09C3A6D2hex in the main memory maps at index 18ten in the cache.
C. The difference between the total cache size and the cache data size is > 4 kiB.
d. Address 09C3A6D2hex in the main memory maps at index 218ten in the cache.
e. The difference between the total cache size and the cache data size is < 4 KiB.

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9. The main memory size is 32 GiB, the addresable unit is the byte, one word is
on 64 bits, one block has 8 words. The cache is 2-way set associative and has a
data size of 32 KiB. Check the false statements regarding the memory system
described here:
a. Address 1AC0004BEhex in the main memory maps at index 18ten in the cache.
b. Address 1AC0004BEhex in the main memory maps at index 12ten in the
cache.
C. The difference between the total cache size and the cache data size is > 1 kiB.
d. Address 1AC0004BEhex n the main memory maps at index 9ten in the cache.
e. The difference between the total cache size and the cache data size is < 1KiB.

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MEMORII VIRTUALE
????1.In a virtual memory system, the virtual address space size is 8 TiB, the
physical address space size is 256 GiB, and the page size is 64 KiB. If the Page
Table entry has 128 bits and the TLB is 4-way SA with a total of 64 entries, check
the true statements:
a. The Page Table size is 2 GiB.
b. The TLB tag field has 22 bits.
c. The page offset field has 16 bits.
d. The Page Table size is 1 GiB.
e. The TLB tag field has 23 bits.

2.In a virtual memory system, the virtual address space size is 4 TiB, the physical
address space size is 128 GiB, and the page size is 16 KiB. If the Page Table entry
has 64 bits and the TLB is 2-way SA with a total of 16 entries, check the true
statements: 1/1
a. The Page Table size is 2 GiB.
b. The Page Table size is 1 GiB.
c. The page offset field size is 12 bits.
d. The TLB tab field has 28 bits.
e. The TLB tab field has 25 bits.

????3.In a virtual memory system, the virtual address space size is 256 GiB, the
physical address space size is 4GİB, and the page size is 64KiB. If the Page Table
entry has 64 bits and the TLB is Full Associative with 8 entries, check the true
statements:
a. The page table size is 32 MiB.
b. The page table size is 16 MiB.
c. The TLB tag field has 22 bits.
d. The page offset has 12 bits.
e. The page offset has 16 bits.

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4.In a virtual memory system, the virtual address space size is 1 TiB, the physical
address space size is 4GiB, and the page size is 32 KiB. If the Page Table entry has
64 bits and the TLB is Direct Mapped with 16 entries, check the true statements:
a. The TLB tab field has 25 bits.
b. The page table size is 128 MiB.
c. The page offset has 12 bits.
d. The page table size is 256MiB.
e. The TLB tab field has 21 bits.

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