AMD K8 ACPI Controller

Internal Block Diagram

VDDIO_HDRV VLDT_DRV
5VSB RSMRST# VDDA 1.25Vref WD_DET
VDDIO_HSEN VLDT_SEN

COMP
POR
5VUSBDRV
Watching
VDDA 1.25Vref Dog Timer
2.8V
5VDRV

COMP

COMP
3VSBDRV

3VSBSEN

VAGPDRV
VAGPSEN COMP
PWR_OK
FP_RST#
VDDIODRV
COMP
CHIP_PWGD
VDDIOSEN Control
Logic CPU_PWGD
PLED0/AGP#
PLED1/EXTERAM
VCC3
COMP
POK1
SS
VCC5 VDD_EN
COMP
VDD_GD
TEMP_FAULT#
PSIN#
S3#
ACPI PSOUT#
Control Bandgap
S5#
PCIRST#
HDD_RST#
SCL
I2C CharPMP DEV_RST#
SDA
Oscilator SLOT_RST#
DDRTYPE

SS C1 C2 ChrPMP
 Power Function
• Support voltage regulator:
• DDR 1 or DDR 2 voltage regulator
– DDR 1 or DDR 2 voltage select by DDRTYPE (Pin 18) select pin
– External DDR standby voltage MOS is request when S3 state
– Support 2 set Linear mode or PWM mode select by PLED1/EXTRAM(Pin 48)
– The both mode support Adjust voltage through I2C bus
– DDR 1 voltage range : 2.5V,2.55V,2.6V,2.65V,2.7V,2.75V,2.8V,2.85V,2.9V,3.0V,3.1V and
default setting is 2.55V
– DDR 2 voltage range : 1.7V,1.75V, 1.8V, 1.85V,1.9V,1.95V,2.0V,2.05V,2.1V,2.2V,2.3V and
default setting is 1.8V
– Power Good Watching Dog timer register (CR0x05) can setting keep or not when power off
• AGP voltage regulator
– Support Linear mode or PWM mode
– The both mode support Adjust voltage through I2C bus
– AGP voltage range : 1.5V,1.55V,1.6V,1.65V,1.7V,1.75V,1.8V,1.85V and default setting is
1.5V
– Power Good Watching Dog timer register (CR0x05) can setting keep or not when power off
 Power Function (Cont.)
• 3VSB regulator
– Support Single or Dual mode select by PLED0 (RAC version)
– Support Dual mode select only (RBF version)
– Single mode : Used one MOS regulate from 5VSB to 3VSB
– Dual mode : Used two MOS when S3 or S5 state standby MOS regulate from
5VSB to 3VSB,When S0 state turn on VCC3 MOS to 3VSB
• 1.2VLDT regulator
– Support Hyper Transport™ I/O ring power supply
• VDD regulator
– Support core power supply
 Power Function (Cont.)
• Support 5VDUAL for USB and KB/MS voltage
• Support 9VSB for use OP-Amp extend extra voltage
• Support 1.25V reference voltage
• Support 2.5VDDA for Filtered PLL Supply Voltage
• DDR1(<1.9V), DDR2 (<1.25V), AGP(<1.1V),
1.2VLDT(<0.85V) and 3VSB(<2.45V) support power
supply shutdown when under voltage protection
 Digital Function
• Provide ATX PWR_OK and RST_ BTN input for 2 open drain output
buffer (CPU_PWROK and CHIP_PWROK)
• Provide PWR_OK1 for power sequence or standby voltage isolate
(This pin is ATX PWR_OK buffer output it can’t be RST_BTN effect)
• Provide 1 to 3 PCIRST# output buffer,The SLOT_RST# is 3.3V TTL
output else are open drain (HDDRST#, DEV_RST#)
• RSMRST# is delay 88ms from 3VSB ready
• Provide PLED0, PLED1 support S0,S1,S3,S5,under voltage, over
temperature indicator:
– Under voltage issue PLED0 and PLED1 flash by turn about 1/4Hz (If this
condition occur system can’t power on unless plug AC power core)
– Over temperature issue PLED0 and PLED1 flash by turns about 1 Hz (If
this condition occur, MS6 instantly into internal S5 state and disable ALL
LUV Function. It can press power button 4 sec to release)
 Digital Function (Cont.)
VCC3

20
DRIVER(VCC3)
2 3
SOLT_RST#(50mA)

OD
2 3 1 2
PCIRST# HDDRST#(50mA)

OD
1 2
DEV_RST#(50mA)

U2
2 3 2 3 2
PWR_OK
1
3 POK1(12mA)

AND2
2 3 2 3 OD
FP_RST#
3 2
CPU_PWROK(30mA)
2 U6
3
2 3 2 3 delay 4 1
ALL_PWR_OK
50mS 5 OD
6 3 2
CHIP_PWROK(30mA)
AND5

2 3 2 3
WATCH DOG TIMER

2 3 2 3 delay
S3#
20uS
 Circuit Design
VDIMM LINEAR OR PWM SELECT
DDR regulator: VDIMM MODE EXTRAM
LINEAR REGULATOR PULL LOW

(Linear mode for 754) EXTERNAL PWM OR LINEAR REGULATOR PULL HIGH

MS-6(DDR)

Pin 22-VDIMM_HDRV
Pin 21-VDIMM_HSEN
Pin 20-VDIMM_LDRV
Pin 19-VDIMM_LSEN
C56 VCC3

X_C1000P16X

S
G Q10

R25 R26 N-P45N02LD_TO252

EC8
1+ 2 _CD1000U6.3EL11.5

D D
100R1% 100R1%
G Q11
N-P45N02LD_TO252
VDIMM

S
EC16

+1

+1
RAC: R26=1K Ohm, R25=2.2K Ohm C57 EC15 _CD1000U6.3EL11.5
RBF: R26=100 Ohm, R25=100 Ohm X_C1000P16X

2
_CD1000U6.3EL11.5
 Circuit Design
VDIMM LINEAR OR PWM SELECT
VDIMM MODE EXTRAM
LINEAR REGULATOR PULL LOW
DDR regulator: (PWM mode) EXTERNAL PWM OR LINEAR REGULATOR PULL HIGH

P19 VDDIO_LSEN
P20 VDDIO_LDRV
P21 VDDIO_HSEN
P22 VDDIO_HDRV

P31 5V_DRV
3VSB
R103
VDIMMPWM_REF
Q45 5VSB
33R
S

N-2N7002LT1_SOT23

2
C73 G
C1000P16X-1 1 4
5VDIMM
D

C74 C75 Q44

3
N-APM2054N_SOT89
R102 X_C1000P16X X_C1000P16X

+1
1KR G EC58

2
_CD1000U6.3EL11.5

S
3VSB Q46
N-P45N02LD_TO252
VCC

R105 10R
5VDIMM
RAC:R66 Remove
RBF:R66=R71=4.7K Ohm C76 C39
U10 C2.2U16Y0805 C2.2U16Y0805
1 14
PWR_OK

S
2 POK VDDA 13
C80 C0.1U16Y 3 GND VDD 12 G Q47 CHOKE4
4 SS LDRV 11 R108 2.55KR1% CH-3.3U15A
5 COMP ISEN 10 N-P50N03LD_TO252 L04-33A7081-T15
D

6 FB PGND 9 PHASE
REFIN HDRV PHASE VDIMM
R109 C81 7 8
S

ISET BOOT

1
C78 C0.22U16X0805 EC61 EC62

+
45.3KR1% G Q48
C82 X_C220P50N MS-6+_SOP14 D2 _CD1000U6.3EL11.5

2
R110 S-1N5817_DO214AC N-P50N03LD_TO252 _CD1000U6.3EL11.5
D

C2200P16X
VDIMMPWM_REF

49.9KR1% CHOKE3
5VDIMM
1

R104 EC59 EC60

+

C77 .CD1000U10EL15
4.7KR1% CH-2.2U15A .CD1000U10EL15
2

C1U16Y L04-22A7071-Y01

R106 X_24R
C79 X_C3900P50X

R107 4.7KR1%
 Circuit Design
DDR regulator: VDIMM LINEAR OR PWM SELECT
VDIMM MODE EXTRAM

(Linear mode for 939) LINEAR REGULATOR

EXTERNAL PWM OR LINEAR REGULATOR
PULL LOW
PULL HIGH

P31 5VDRV

P19 VDDIO_LSEN
P20 VDDIO_LDRV
P21 VDDIO_HSEN
P22 VDDIO_HDRV
3VSB

N-APM2054N_SOT89
Q40
3VSB

2 FOR K8 SOCKET 939 2 DIMMS

1 4
3.3VDIMM
3.3VDIMM 3VDIMM
3

C72
X_C1000P16X

+1
D

EC54
G 2
_CD1000U6.3EL11.5
Q41
S

N-P45N02LD_TO252
Q21 : Switching MOS
3VDIMM VCC3
Q43 FOR K8 SOCKET 939 4 DIMMS
D

N-P45N02LD_TO252 9VSB
G
VDIMM 3.3VDIMM
R70 C71
S

R68 U9B
X_C1000P16X
8

1KR Q42

D
1

1.25VREF 5 N-P45N02LD_TO252
+

EC56 EC57 100R1% R100 + 7 G

_CD1000U6.3EL11.5 _CD1000U6.3EL11.5 6
2

100R1% C38 -
S

C10000P16X LM358MX_SOIC8
4

3VDIMM
RAC:R55 Remove, R53=0 Ohm R101

RBF:R55=100 Ohm, R53=100 Ohm

1.4KR1%
+1

R59
EC55
1KR1% _CD1000U6.3EL11.5
2
 Circuit Design (Cont.)
AGP regulator:

VCC2.5
C60

D
X_C1000P16X Q5
Pin 30-VAGP_DRV G N-P3057LD_TO252
VAGP

Pin 29-VAGP_SEN

+1 S
EC4

_CD1000U6.3EL11.5

2
 Circuit Design (Cont.)
3VSB regulator:
THE TWO MODE ONLY ONE MODE PRESENT
SINGLE MODE(RAC only) DUAL MODE(RAC or RBF)
THIS MODE SELECT BY PIN THIS MODE SELECT BY
47 PULL HIGH 5VSB PIN 47 PULL LOW
3VSB REGULATE BY 5VSB 3VSB REGULATE BY 5VSB AND VCC3

5VSB VCC3

D
Q8
Pin 24-3VSB_DRV G 3VSB Q9 5VSB
1 8
N-P3057LD_TO252 P31-5V_DRV 2 7
Pin 23-3VSB_SEN 3 6
S

Pin 24-3VSB_DRV 4 5
+1

+1

+1
EC9 EC10 NN-P2103HV_SO8 EC11

CD470U10EL11.5 CD470U10EL11.5 C58 _CD1000U6.3EL11.5

2

2
X_C1000P16X
 Circuit Design (Cont.)
1.2VLDT regulator:

VCC3

D
Q6
Pin 27-1.2VLDT_DRV G N-P3057LD_TO252

C59

S
X_C1000P16X 1.2VLDT

Pin 26-1.2VLDT_SEN

1 +
EC6
_CD1000U6.3EL11.5

2
 Circuit Design (Cont.)
5VDUAL regulator:

5V DUAL Power
C3 VCC5_SB

X_C2200P16X Q3
Pin 32-5VUSB_DRV 4 5 5VDUAL
3 6
Pin 31-5V_DRV 2 7
1 8
C5

1
EC2 EC3

+
D
X_C2200P16X NN-P2103HV_SO8
VCC5 FRONT G CD470U10EL11.5
X_CD470U10EL11.5

2
Q4
N-P45N02LD_TO252

S
VCC5
Power sequence for AMD K8
(Signal Sequencing)
Power sequence for AMD K8
(Power supply Sequencing)