Course Code and Title:

EEE 416: VLSI CIRCUITS & SYSTEMS

Semester and Year:

Spring – 2022

Experiment Number and Name:

Experiment-2: Layout design of a CMOS inverter

Name of Student and ID: Instructor:

Md. Abu Shayem Dr. Mohammad Mojammel Al Hakim

ID: 2019-1-80-021 Chairperson, EEE
Date of Submission: Date of Performance:

20 March, 2022 13 March, 2022

Results:
For Inverter-1:

Fig-2: Layout of Inverter-1

Fig-3: Input and output response

Fig-4: Voltage Vs Current plot

Fig-5: Communication point measuring plot

Fig-6: Rise delay for different capacitance

Fig-7: Fall delay for different capacitance

Fig-8: Power dissipation plot

Fig-9: Rise delay for different supply voltage
 For Inverter-2:

Fig-10: Layout of Inverter-2

Fig-11: Input and output response

Fig-12: Voltage Vs Current plot

Fig-13: Communication point measuring plot

Fig-14: Rise delay for different capacitance

Fig-15: Fall delay for different capacitance

Fig-16: Power dissipation plot

Fig-17: Rise delay for different supply voltage

For Inverter-3:
Fig-18: Layout of Inverter-3
Fig-19: Input and output response

Fig-20: Voltage Vs Current plot

Fig-21: Communication point measuring plot

Fig-22: Rise delay for different capacitance

Fig-23: Fall delay for different capacitance

Fig-24: Power dissipation plot

Fig-25: Rise delay for different supply voltage