Course Code and Title:

EEE 416: VLSI CIRCUITS & SYSTEMS

Semester and Year:

Spring – 2022

Experiment Number and Name:

Experiment-4: Designing a two input NAND and AND gates using DSCH and
optimizing the mask
layout diagram by compiling VERILOG codes.
Name of Student and ID: Instructor:

Md. Abu Shayem Dr. Mohammad Mojammel Al Hakim

ID: 2019-1-80-021 Chairperson, EEE
Date of Submission: Date of Performance:

17 April, 2022 11 April, 2022

Fig-3: Circuit diagram for 2-iput NAND gate.

Fig-4: Output diagram for 2-iput NAND gate.

Fig-5: Mask layout without optimization for 2-iput NAND gate.

Fig-6: Circuit diagram for 2-iput AND gate.

 Fig-7: Output diagram for 2-iput AND gate.

Fig-8: Mask layout without optimization for 2-iput AND gate.

• Verilog code:
For NAND gate:
// DSCH 2.7f
// 13-Apr-22 5:40:00 PM
// D:\EEE-416\Labs\Lab-4\NAND.sch

module NAND( A,B,A,B,out1);

input A,B,A,B;
output out1;
pmos #(24) pmos(out1,vdd,B); // 2.0u 0.12u
pmos #(24) pmos(out1,vdd,A); // 2.0u 0.12u
nmos #(24) nmos(out1,w4,A); // 1.0u 0.12u
nmos #(10) nmos(w4,vss,B); // 1.0u 0.12u
endmodule

// Simulation parameters in Verilog Format

always
#1000 A=~A;
#2000 B=~B;
#1000 A=~A;
#2000 B=~B;

// Simulation parameters
// A CLK 10.000 10.000
// B CLK 20.000 20.000
// A CLK 10.000 10.000
// B CLK 20.000 20.000

For AND gate:

// DSCH 2.7f
// 13-Apr-22 5:43:10 PM
// D:\EEE-416\Labs\Lab-4\AND.sch

module AND( A,B,A,B,out2);

input A,B,A,B;
output out2;
pmos #(31) pmos(w2,vdd,B); // 2.0u 0.12u
pmos #(31) pmos(w2,vdd,A); // 2.0u 0.12u
nmos #(31) nmos(w2,w4,A); // 1.0u 0.12u
nmos #(10) nmos(w4,vss,B); // 1.0u 0.12u
pmos #(17) pmos(out2,vdd,w2); // 2.0u 0.12u
nmos #(17) nmos(out2,vss,w2); // 1.0u 0.12u
endmodule

// Simulation parameters in Verilog Format

always
#1000 A=~A;
#2000 B=~B;
#1000 A=~A;
#2000 B=~B;

// Simulation parameters
// A CLK 10.000 10.000
// B CLK 20.000 20.000
// A CLK 10.000 10.000
// B CLK 20.000 20.000
Fig-9: Mask layout after optimization for 2-iput NAND gate.
Fig-10: Mask layout after optimization for 2-iput AND gate.