Unaligned Transfers

63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
7 6 5 4 3 2 1 0 1st transfer
Address: 0x00
Transfer size: 32 bits 7 6 5 4 3 2 1 0 2nd transfer
Burst type: incrementing F E D C B A 9 8 3rd transfer
Burst length: 4 transfers
F E D C B A 9 8 4th transfer

7 6 5 4 3 2 1 0 1st transfer
Address: 0x07
Transfer size: 32 bits F E D C B A 9 8 2nd transfer
Burst type: incrementing F E D C B A 9 8 3rd transfer
Burst length: 4 transfers
17 16 15 14 13 12 11 10 4th transfer

7 6 5 4 3 2 1 0 1st transfer

Address: 0x07 F E D C B A 9 8 2nd transfer

Transfer size: 32 bits
F E D C B A 9 8 3rd transfer
Burst type: incrementing
Burst length: 5 transfers 17 16 15 14 13 12 11 10 4th transfer

17 16 15 14 13 12 11 10 5th transfer

Figure 10-2 Aligned and unaligned word transfers on a 64-bit bus

Figure 10-3 shows a wrapping burst of 32-bit transfers on a 64-bit bus.

63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
7 6 5 4 3 2 1 0 1st transfer
Address: 0x04
Transfer size: 32 bits F E D C B A 9 8 2nd transfer
Burst type: wrapping F E D C B A 9 8 3rd transfer
Burst length: 4 transfers
7 6 5 4 3 2 1 0 4th transfer

Figure 10-3 Aligned wrapping word transfers on a 64-bit bus

10-4 Copyright © 2003, 2004 ARM Limited. All rights reserved. ARM IHI 0022B