Index

AXI protocol CACTIVE 2-8 G

features 1-2 timing example 12-4, 12-5
Channel register insertion 1-6 Global signals 2-2
Clock 11-2
B Completion signaling 1-5, 7-2, 7-4, 7-5
see also BRESP H
BID 2-5 see also RRESP
out-of-order transactions 8-2 Conventions Handshake
Big-endian data structures 9-5 signal naming xvii address channel 3-2
BREADY 2-5 timing diagram xvi read address channel 3-4
default value 3-4 typographical xv read data channel 3-2, 3-5
timing example 1-9 CSYSACK 2-8 signal dependencies 3-7
BRESP 2-5 timing example 12-4, 12-5 timing example 3-3
encoding 7-2 CSYSREQ 2-8 write address channel 3-3
in exclusive accesses 6-6 timing example 12-4, 12-5 write data channel 3-2, 3-4
timing example 1-9 write response channel 3-2, 3-4
Bufferable attribute 1-11
selecting 5-2 D
Burst I
address 4-7 Data bus
length 4-7 narrow transfers 9-4 Incrementing bursts
Burst length 4-3 width 1-5 byte lanes 4-4, 4-8
encoding 4-3 DECERR response 7-2, 7-5 increment value 4-5
Burst size 4-4 Decode error narrow 4-4
encoding 4-4 see DECERR response start address 4-7
Burst type 4-5 Direct memory access Interconnect
encoding 4-5 see DMA combining data streams 8-6
fixed 4-5 DMA, support 1-2 implementations 1-6
incrementing 4-5 locked accesses 6-7
wrapping 4-6 out-of-order transactions 1-9, 8-6
BVALID 2-5 E realigning address and data 3-6
reset requirements 11-2 Interleaved transactions
timing example 1-9 Exclusive access see Out-of-order transactions
Byte lane strobes 1-5 selecting 6-2
see also WSTRB slave support logic 6-3
Byte lanes Exclusive access response L
eight-bit transfer example 9-4 see EXOKAY response
32-bit transfer example 9-4 EXOKAY response 6-3, 6-5, 7-2, 7-4 Little-endian data structures 9-5
Byte-invariant endianness 9-5 Locked access
interconnect 6-7
F selecting 6-2
C Low-power interface
Fixed bursts 4-5 signals 2-8
Cache byte lanes 4-4, 4-8
support 5-2 start address 4-7
Cache encoding 5-3 M
Cacheable attribute 1-11
selecting 5-2 Master slave handshake 1-4, 1-7, 3-2
timing example 3-2, 3-3

Index-2 Copyright © 2003, 2004 ARM Limited. All rights reserved. ARM IHI 0022B