Designing a dual-fuel motor

management system with Zynq

Frank de Bont Cereslaan 10b

5384 VT Heesch
Trainer / Consultant
 +31 (0)412 660088
 info@core-vision.nl
www.core-vision.nl
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DEVELOPMENT 1
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 

Agenda
 Customer Requirements
 Engine Management System
 LNG Supply
 Sensors / Actuators
 AR Electronic Control Unit
 Zynq Architecture
 Design Flow and Tools
 High-Speed ADC IP-block
 Software Partitioning and Communication Channels
 Why Linux with Xenomai
 eMMC Configuration
 Who is Core|Vision

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 Customer Requirements
1
-

 Design a dual-fuel motor management system

54255**slide

with real-time control

 Hardware Platform Caterpillar 3500
 Diesel
 LNG (Liquefied Natural Gas)

 High fuel efficiency

 Start up on Diesel and then switch over to a mixture with LNG

 Lowest possible emissions

 NOx , SOx , CO2 and CH4 (methaan)

 Easy to retrofit
 Suitable for different qualities of LNG
 Still 100% Diesel as a fall back

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 Customer Requirements cont
1
-

 Focus on motor management control also called

54255**slide

ArenaRed Electronic Control Unit

 Hardware Platform Caterpillar 3500
 Diesel
 LNG (Liquefied Natural Gas)

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 Engine Management System

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 Engine Management System

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 LNG Supply

Full controlled by the AR-ECU

 A full fail-safe system
 On-board diagnostics
 Power and Temperature sensors

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 Sensors / Actuators

 Combustion in each cylinder is monitored by a set of

cylinder pressure sensors
 These allows the AR-ECU to optimize the combustion timing
and gas mixture
 In the exhaust are UEGO λ-sensors and temperature sensors
to monitor the results of each combustion cycle
Turbo
Boost Wastegate
Inlet
Wastegate Manifold
Filter Compressor Intercooler Gas

P
P P T λ
P T Diesel

Turbine

P Pressure sensor
T Temperature sensor
λ Lambda (UEGO) sensor

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 AR Electronic Control Unit

Connectors Connectors

[PWR] 16
Power Supply Units Injector P
16
Injector N

g
ia

ia
D

D
+24V Power Supply Units +24V Power Supply Units
for internal supplies for external supplies

8
8 x EMD 8 x EMD

+15V

+12V
-15V

+5V

+8V
[STOP]
Emergency stop
1
ESTOP OUT ISOLATED ISOLATED

+15V

+12V
-15V
[DL]

+5V

+8V
CAT data link

+24Vinj
+24Vinj

2 Kill / IRQ

2 Kill / IRQ
UART

UART
Fault

Fault
Fire

Fire
1 EMERGENCY Watchdog and health
ESTOP

Termination
STOP check uP

8
1

8
1
2
CAT Data Link

Internal
JTAG DDR3
8 x LED Expansion
Connector 2x 2Gb
Connectors
[DO_HC]
SPI Flash E-MMC
50 MHz Digital Output High Current
Diag
64Mb 32GB

+24V
43
32

20

16
5

2
1

2
1

General Purpose
Data Ctrl

+ Protection
I/O Controller
I/O Controller

Configuration

I/O Controller

I/O Controller

I/O Controller

I/O Controller
[CAN]
Controller

Controller

Controller

Controller

Controller

24V/5A
22
Interrupt

Interrupt

Interrupt
Memory
UART

UART

UART
JTAG

Clock

Out
SDIO
CAN interfaces 22
Digital out
4 Diag
Controller
SPIController

6 6
CAN
CAN CAN
CAN
12 14
CAN Phy
Phy Controller
Controller
MCP2551
MCP2551 MCP2515
MCP2515
[EMD]
SPI

Electromechanical Drivers [AO]

Analog Out 4-20mA

I/O Controller
Controller

4-20mA
CAN
Zynq SoC

driver
CAN

2 2 2 4
CAN Phy Analog out
MCP2551

[SHD] [POS] [AI_LS] [AI_HS] [DI] [ETH]

Remote Position interfaces Analog Input Low Speed Analog Input High Digital Input Ethernet interfaces
Shutdown Speed
Controller

+24V
CAN
CAN

2 2
CAN Phy
I/O Controller

Controller

SPI Controller
I/O Controller

I/O Controller
I/O Controller

I/O Controller

I/O Controller

I/O Controller

I/O Controller

Purpose Out
SPIController

+ Protection
24V/300mA
3

Controller
MCP2551

AR ECU x

AR ECU x

General
RGMII
3

MII
Digital out
1 Diag
SPI
SPI

1 6 3 3 6 10 1 32 2 2 15 12 [DO_LC]
10
Digital Output Low Current
Rst CA Pulse SWITCH
Synchroniser (3 ports)
2 3 3 2 4
[PWR] 6x 7
6 ADC

ADC
Power Supply Units RS422 HALL VRSensor
Sensor VR Sensor

ADS8363
Ch.ADC
HALL
6 Ch. ADC

VR RS485
MCP3903

ADS8363
RS422 4 4 4 4
6MCP3903

interrface Interface
Interface Interface
PHY
PHY interrface
Shutdown

PHY
Remote

22Ch.
Ch.
+24V

+24Vinj

Gbit Phy

42 8

Protection 40 x COND COND

0-10V
and 2x Magnetics Magnetics Magnetics
4-20mA
Vbatt

+5V

+12V

+8V

Gnd

Preamp

1 12 3 3 4 4 42 8 32 8 8 8
Shutdown

Encoder

HALL sensor

VR

ADC

OBD/Debug
RS485 RX

RS485 TX

Digital in

100Mb Link
Cascade
ADC

100Mb Link
Cascade

Connectors
PWR

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 AR Electronic Control Unit

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 AR Electronic Control Unit cont

General Interfaces
 DDR3 memory
 eMMC
 SPI Flash
 JTAG
 RS485
 CAN
 Ethernet
 …
Monitor Interfaces
 16x 12 bits ADC
 2x UARTs
 1x CAN
 10x PWM outputs

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 AR Electronic Control Unit cont

Electromechanical drivers
 High Voltage IO
 High Current IO
Digital Interfaces
 High Current IO
 Low Current IO
 Sensor Inputs
Analog Interfaces
 High Speed Inputs
 Low Speed Inputs
 Analog Outputs
Misc Interfaces
 LED bank
 Position Interface
 Expansion Connector

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 Catepillar 3500 & AR-ECU

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 Zynq Architecture

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 Zynq Architecture cont

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 Zynq Architecture cont

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 Zynq Architecture cont

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 Zynq Architecture cont

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 Design Flow and Tools

Software FPGA hardware

 Real-time OS  ADC IP Interface
 Drivers  eMMC interface
 APIs  DDR3 memory
 ...  IO
 JTAG
 ...
Tools Tools
 Vivado SDK  Vivado
 Matlab  Matlab
 ...  ModelSim
 Altium
 ...

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 High-Speed ADC IP-block

 High-Speed ADC to read

pressure sensors

 AXI streaming interface for

transmitting ADC data
completed with timestamp and
crank angle

 AXI slave interface for

configuration

 Interface to 2 ADC channels

of the ADS8363

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 High-Speed ADC IP-block cont

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 High-Speed ADC IP-block cont

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 Software Partitioning and
Communication Channels
 Zynq SoC heart of the system
 Linux with Realtime
extension Xenomai
 Licensed & custom IP
in FPGA PL
 Microprocessor for
Watchdog & Health
Monitor
 Software controlled
EMD Injector Drivers
 Communication
cascading channel

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 Cascading Channels

 Multiple AR-ECUs can be cascaded so the system can

control more than eight cyclinders.

AR-ECU
AR-ECU AR-ECU
AR-ECU AR-ECU
AR-ECU
#1 CA Pulse
Sync
#2 CA Pulse
Sync
#3 CA Pulse
Sync
Eth Eth Eth Eth Eth Eth Eth Eth Eth
100 Mb 1 Gb 100 Mb 100 Mb 1 Gb 100 Mb 100 Mb 1 Gb 100 Mb

 Since Ethernet is non real-time by nature, crucial real-

time signals will be routed over the four dedicated wires.

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 Why Linux with Xenomai

 Zynq All Programmable SoC dual core Cortex-A9

 Xilinx offers a kernel build and Linux kernel distribution by 3rd
parties

 Support Linux 3.14.17 with patches for real-time extension

Xenomai 2.6.4 within SDK, version choice is limited
 Xenomai offers greater flexibility and consistency because the
real-time tasks can share the same drivers, synchronization
primitives and memory as other non real-time tasks

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 eMMC Configuration
Initial Programming Running Bitfile Selection

Set boot mode pins of Zynq to Set boot mode pins of Zynq to
JTAG (can be forced in initial QSPI (can be forced in running Start
programming U-boot) U-boot)

Download initial programming Download running U-boot using

U-boot using JTAG QSPI
Updated Yes
bitfile
present in
eMMC?

Start initial programming U-boot Start running U-boot Program Yes

FPGA
succesful?

Download initial programming Download golden or updated No

kernel, ramdisk image and DTB bitfile using eMMC
files using TFTP

Golden Yes
Start initial programming kernel Download running kernel ramdisk image
image and DTB files using eMMC present in
eMMC?

Program Yes
FPGA
Run initial programming shell succesful?
scripts using rcS to download Start running kernel
from TFTP and program: No
• Running U-boot + FSBL to QSP
• Running kernel to eMMC
• Running ramdisk to eMMC
• Running DTB to eMMC
• Golden bitfile to eMMC Stuck in U-boot, no valid FPGA Done, FPGA loaded succesfully
• Update bitfile to eMMC image found

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 Flash Image Generation
Flash Image
Zynq
Configuration BootHeader
Wizard FSBL
(Executable)
Boot & Configuration
FSBL
Information
PS Register PL
Initialization PL
Bitstream(s)
Bitstream(s)
Flash Image
Generator
FSBL OS and/or OS and/or
(source Code) Application Application
User Created Code & data Code & data

Golden Image Golden Image

(optional) (optional)

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 Core|Vision
Our competences
Core|Vision has more than 125 man years of design experience in hard-
and software development. Our competence areas are:

 System Design
 FPGA Design
 Consultancy / Training
 Digital Signal Processing
 Embedded Real-time Software
 App development, IOS Android
 Data Acquisition, digital and analog
 Modeling & Simulation
 ASIC Conversion & Prototyping
 PCB design & Layout
 Doulos & Xilinx Training Partner

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 ?
?
Cereslaan 10b
5384 VT Heesch
 +31 (0)412 660088

www.core-vision.nl
Email : info@core-vision.nl

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 Visit our booth 28
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 Training Program
 Essentials of FPGA Design 1 day
 Designing for Performance 2 days
 Advanced FPGA Implementation 2 days
 Design Techniques for Lower Cost 1 day
 Designing with Spartan-6 and Virtex-6 Family 3 days
 Essential Design with the PlanAhead Analysis Tool 1 day
 Advanced Design with the PlanAhead Analysis Tool 2 days
 Xilinx Partial Reconfiguration Tools and Techniques 2 days
 Designing with the 7 Series Families 2 days

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 Training Program
 Vivado Essentials of FPGA Design 2 days
 Vivado Design Suite Tool Flow 1 day
 Vivado Design Suite for ISE Users 1 day
 Vivado Avanced XDC and STA for ISE Users 2 days
 Vivado Advanced Tools & Techniques 2 days
 Vivado Static Timing Analysis and XDC 2 days
 Debugging Techniques Using Vivado Logic Analyzer 1 day
 Essential Tcl Scripting for Vivado Design Suite 1 day
 Vivado FPGA Design Methodology 1 day
 Designing with the UltraScale Architecture 2 days

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 Training Program
 Designing with Multi Gigabit Serial IO 3 days
 High Level Synthesis with Vivado 2 days
 C-Based HLS Coding for Hardware Designers 1 day
 C-Based HLS Coding for Software Designers 1 day
 DSP Design Using System Generator 2 days
 Essential DSP Implementation Techniques for
Xilinx FPGAs 2 days

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 Training Program
 Embedded Systems Design 2 days
 Embedded Systems Software Design 2 days
 Advanced Features and Techniques of SDK 2 days
 Advanced Features and Techniques of EDK 2 days
 Zynq All Programmable SoC Systems Archicture 2 days
 Zynq All Programmable SoC Accelerators 1 day
 C Language Programming with SDK 2 days
 Embedded Design with PetaLinux SDK 2 days
 Embedded C/C++ SDSoC Development
Environment and Methodology 1 day

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 Training Program
 VHDL Design for FPGA 3 days
 Advanced VDHL 2 days
 Comprehensive VHDL 5 days
 Expert VHDL Verification 3 days
 Expert VDHL Design 2 days
 Expert VHDL 5 days
 Essential Digital Design Techniques 2 days

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