1869910057 eGers }} Explain techniques to improve ite perftrenance of coche by Teducing miss tate Techniques to improve the per formance of cache by seducing miss rate ') Langer block size: The simplest and abvious oy to Teduce “the ames yale i6 to increase “the block Size. By inceds: +the block size, we ane Hying to exploit the spatial locality Of -efrence in a beltey Manner and hence the reduction tn miss rates 2) Lager cache size: the nent optimization thal we consid for reducing “the mgs Tales 7S Increasing the Cache Size iE Sop This is ogi in obvious Solutisn. F ncreasing the Site of the cache will veduce The Capacity misses , gived athe same line size, SiNce nove number of blocks can be accommodated 2) highe, osseciativity: This 1S related to the mapping shakey adopted: Fully agsociative snapping has the best associa- - tivity and direct sopping “the worst. But, for all practical Purposes , 8- Woy set associakve Mapping itself ig 08 good 0S fully gssociatve mapping The flea bility offexed by higher associativity reduces the Conflict misses Hawevey, iMCvedS! NG sthe associativity saceases the moploxity of the cache ‘Scanned with CamScanner0 . zations: 0 far, xe hove discussed di Hinduore sotored techniques for rectucing the miss sates. Noos ,cao Shall discuss Some options “that the compiles _ eaaiky tay Provide to vecluce the miss rates The compiler Can easily reorganize the cede, coithout affecting the cove- ~ctness of tre prom System ith 2GB Of Main Memory hos a 64 k8 direct mapped coche which uses oO block Size of 8 cords “he word length iS 32 bits. Hoo ony oq bits ave present ? | Coche Size - 64 KB > a'® bytes Lword —> 32 bits | S Ley 4 bytes Block Size ~ Bcoords + 32 bytes >a : is 8x 4 = 32 bytes sets - Cache size Block size x associahvity 16 - a _ 9" ae xi pats etal tength 32 Yemaining —-—, + 2 - h v v Taq = 32-16 “4 aq thes offset “4 “TOG = 16 The B Tog bits are Ie write short rote an the following i) XY Routing ii) Deadlock in Noc i) XY Routing : The xy routing algovith is simple ‘0 implementation » 70 algorsthn that is proposed used in Noe Thi ‘Scanned with CamScannerThis algorithm is suitable for >egulay ; : i andj Aetwork topologies - $n onder vf one lend ‘ae Consider “the two-dimensional Axm Mesh . ‘To idenhfy Rach nace, in this mesh hos a locaton in -tho form of (44) Where x represents its posikon in the M direonsron si Yrepmesents its position in the y- dimension ii) Dead lock th NOC : 4+ Deadlock can occur in an interconnecton achunk, when a group of packets cannot make progress, because they ae eaaiing on cach other to release eSounce (buffers , channels) # No fosmid proyiess Caused by circular dependencies on yesounces % Each pocket wits fora buffer occupied by ancthen facket downstheam 4 Deadlock can accur if packels one allowed to hoki Some megources while requesting others, blocked packets holding channels remain in the Because Network. iN the working of DeBAR router coith a neat Block ciogramy 33 silver in the Cunent router may qeta but ence it reaches the adjacent router then cK it There 13 ro Guesantes thata | Scanned with CarnScanner| (2 the adpcent aouter. 80 19 -the cment souten it rr | Closer to destination but inthe adjacent router it may Silver, leading to o deflection, then if moy oon back So that if cannot quarent ee progress 7. 7 ~ons where ackhessedt by “he next router 19 M ve “that ig koown OS be BAR (cleflecton based a ph S -1 = toge conta! Buffer pool Stage 2 ry a a ne i | 1 al | Permutation! | r DIU L_—+ pefieckon | |Beu | | Network | | |] : ‘ | 1 | {Ilo UL | LPiskY} —_— | peu: priovity Fixer unit g RU: Quadrant Routing unit “Bevo: Buffer Geckon unit his 16 also a hao Stoge router that stage one consisting OF hybrid ejection unit, fit preemplon unit, and ahi -Hon unit. and herve is 0 priority Fixer, guachant south 9 umt, and as usual our Perroutakon defleckon nehoork, which 13 a panallel fort allocation unit and the buffet jection unit, So these ore the two ae and the vorious functional units op the neto Toutey DeBAR. i what is network on chip (noc)? Explain various Noc ‘topalag- 703 with Suitable diagram. O:Scuss the advantages and Hawdbacks of each network topoleqy. HEU: hybrid Ejeckonunit er FRU: Flit Preemption ut DIV< Dual Snjection unit 4p iS A-youter- based packet swit ¢ modules. Noc techoology appl — ching | 0S. Scanned with CamScannerapoloa snes the physical layout and connection pattern ocr rok: ea Channels inthe ekuotk ” ) Mesh: ¥ Coch node connected to 4 Neighbors (N,S.E,) % Cosy to layout on-chip : requla and equal-length links path diversity: many ways to get From one ode +o another. 1S not Symmehic on edges: Performance ver ve to placement op ie on ce vs middle a } avoids this problem f 4o lay out on-chip Ke lengths Scanned with CamScannerds * planar , hiewar chical topology * Goad for local ha ffic * Cosy to Layout ¥ Root can became a bottle neck * Fat hoes awid this problem (cm-5) ') Mesh tops = Advantages ‘) The arrangement of the network nades 1S Such that i+ is Possible to hansmit data from one node to many other | modes atthe same Hme ¢ 3) point-to-point contact bekween every fair of nodes, make ik easy to identify faults rawbacks: ie! ed “thus, the costs incunn Scanned with CamScanner>) Drawbacks: ) Complerity of coiving 2) cost. 3) Ring Topology : =) Advantages: }) The dato being thansmitted bekacen boo nades passes trough all the intermediate nodes. A cenhal Server is Not requived for the enanagement Of this topology 2) The confiquiation makes if easy to identify, foults +9 Nehwork nodes =) Drawbacks + 1) The Foiluve of a Single node in the nekoork con Couse the entire network to foil. . 2) Thee *s heavy cepenclency an-the wire conneck ng the. network nedes inthe tig y exPANSION able Sequirerrent Scanned with CamScannermminienally -buf ' ») roaker eo es'90) Enameinnes bufferloss doplect of 0 Small buffer, called tho “Side buffer” Eject inject’ “bang WOKING: The minBD router does not use input bu Conventional buffered outers. Snstead, a Fit that anives at fess, unlike the toute proceeds ditecHy +to the routing and arbi bation logic. This logic performs cleflecton routing, $o that chen two Fits contend for ON output Port, one of the flits is sent FO Another output instead Howovey th. unlike a buffer less - Cleftection Touter, tho MinBD routes can also buffer up to ane Flt per cycle in 0 Single FIFO- queue side buffer. the Toutes examines all Fiits at the output op the deflection outing leqic, and if any aro doflected, one of the deflect Flits is Yemeved from the router pipline and buffeted From the side buffer, fits are 1e-injected “thus Some flits hat would have been doplected in a bufferless deflection — xoutey axe Temaved from the Nehoork temporarily in bp this side buffer, and given a second chance to arbitra for a productive router output when 7e-injected - ces the nehwork deflection rate chile bupPevi fraction of —baffic ; dali ‘Scanned with CamScanner