EC T45 - DIGITAL CIRCUITS

COURSE OBJECTIVE
 To understand the fundamentals of number systems
 To understand the concepts of Boolean Algebra, Simplification of Boolean
Function
 To understand the concepts of Combinational Logic Design, Programmable
Logic Devices
 To conceptualize the working of Sequential Circuits, Synchronous Sequential
Circuits
 To gain the knowledge in Memory

UNIT- I

Number System: Binary Number Representations – Signed Numbers and

Complements, Unsigned, Fixed point, and Floating point numbers. Addition and
subtraction with 1‘s and 2‘s complements. Codes: Binary code for decimal
numbers- Gray code-Codes for detecting and correcting errors: Even and Odd
parity codes, Hamming Codes, Checksum codes, m-out–of-n-codes.

UNIT – II
Boolean Algebra: Basic theorems- Postulates- Duality – Boolean Function-
Canonical form-Standard form. Simplification of Boolean Function:Karnaugh
map method – Quine-McCluskey method -Incompletely specified functions.
Realization of logic functions - NAND gate realization - NOR gate realization -
Multilevel synthesis.

UNIT - III
Combinational Logic Design: Half adder - Full adder– Parallel Adder- Carry
Look Ahead Adder – BCD Adder – Magnitude Comparator – Encoders and
Decoders – Multiplexers – Code converters – Parity generator, Parity checker-
Combinational circuit implementation using multiplexers and decoders.
Programmable Logic Devices: PROM – EPROM – EEPROM- Programmable
Logic Array (PLA) – Programmable Array Logic (PAL) -Realization of
combinational circuits using PROM,PLA and PAL.

UNIT – IV
Sequential Circuits: General model of sequential circuits –latches – Master-slave
Configuration- Flip-Flops - Concept of State – State diagram – State Table.
Synchronous Sequential Circuits – Binary ripple counters-Design of
Synchronous counters- binary counters- Arbitrary sequence counter - BCD
counter – Shift Registers – Ring Counter – Johnson Counter – Timing diagram –
Serial Adder – PN sequence generator.
Sequential PLDs – Block diagrams of CPLD and Field programmable Gate Array
(FPGA).
UNIT – V
Memory: Classification of Memories – RAM Organization – Write Operation –
Read Operation – Memory Cycle – Timing Waveforms – Memory Decoding –
Memory Expansion – Static RAM Cell –Dynamic RAM Cell.

Text Books:
1. John F. Wakerly, ―Digital Design Principles and Practices‖, PHI Private Ltd.,
New Delhi, Fourth Edition, 2006
2. Morris Mano, ―Digital design‖, PHI Learning, Fourth Edition, 2008.

Reference Books:
1. Donald P Leach, Albert Paul Malvino and Goutam Saha, ―Digital Principles
and Applications,‖ 6thedition,Tata McGraw Hill Publishing Company Ltd.,New
Delhi,2008.
2. Thomas L. Floyd, ―Digital Fundamentals,‖ Dorling Kindersley (India) Pvt.
Limited, 8th ed., 2008.
3. Tocci R J, ―Digital systems: Principles and Applications‖, PHI learning, New
Delhi, Tenth Edition 2006.

Web References:
1. www.technologystudent.com
2. www.facstaff.bucknell.edu
3. www.chegg.com
EC P42-DIGITAL CIRCUITS LABORATORY
1. Design and implementation of the following Code convertors
i. BCD to excess-3 code and vice versa
ii. Binary to gray code and vice-versa

2. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder
using IC7483

3. Magnitude comparator
a) Study of 4-bit magnitude comparator IC
b) Realization of 8-bit magnitude comparator using 4-bit magnitude comparator
ICs

4. Multiplexers and Encoders

i. Study of an 8×1 multiplexer IC
ii. Realization of 16×1 multiplexer using 8×1 multiplexer ICs
iii. Realization of a combinational circuit using multiplexer
iv. Construction and study of a simple Priority Encoder

5. Decoders and Demultiplexers

a) Study of a 3 to 8 line decoder IC
b) Study of a 3 to 8 line decoder as demultiplexer
c) Sudy of the cascading arrangement of an 8×1 multiplexer IC and a
corresponding demultiplexer IC
d) Realization of 4 to 16 line decoder using 3 to 8 line decoder ICs
e) Realization of a combinational circuit using a decoder IC

6 Shift register
a) Study of a universal shift register IC
b) Construction of ring counter and Johnson counter using a shift register IC and
study of their timing diagrams
c) Designing a PN Sequence Generator using a shift register IC

7 Ripple Counters and their timing diagrams

a) 3-bit binary counter
b) 3-bit binary up/down counter
c) A modulo-N-counter( where n is the no. of FFs used to construct the counter)
d) BCD counter using mod-10 counter ICs

8 Design and implementation of Synchronous Counters and study of their timing

diagrams
a) Binary counter
b) Non-sequential binary counter
c) 3-bit binary up/down counter
9. Study of a Memory IC
a) READ and WRITE operations involving memory chips
b) Expansion of memory size

10. Writing Verilog code for the following circuits:

i. Ex-OR Gate
ii. Full Adder
iii. Multiplexer
iv. Binary Up-Counter
v. Binary Up-down Counter
vi. Shift Register