Register Number:

NATIONAL COLLEGE OF ENGINEERING, MARUTHAKULAM – 627151

Electronics and Communication Engineering
Sixth Semester
EC2354-VLSI Design
INTERNAL ASSESSMENT TEST---III
Time: 1 ½ hours Maximum : 50 marks
Answer all questions
PART A—(5*2=10)
1. What is IDDQ Testing ?

2. What are the technique in Ad hoc testing?

3. Write the function of Bypass register.

4. List out the I/O of TAP.

5. Briefly explain PRSG.

6. Define module.

7. Develop Verilog code for 2-1 Multiplexer.

8. What is procedural assignments.

9. Write Verilog code for CMOS inverter.

10. Differentiate blocking and non-blocking assignments.

11. Write short notes on Primitive gates.

12. Define Identifiers in Verilog HDL.

PART B (8+16+16=40 marks)

13. a) Explain Built in self test. (8)

a) Explain Serial and parallel scan design. (8)

(or)

b)Explain operators in Verilog HDL. (8)

b)Describe the 3 ways of specifying delays in continuous

 assignment statements. (8)

14. a) Discuss about Boundary scan architecture. (16)

(or)

b) Explain Design for testability. (16)

15. a) Discuss in detail about Behavioral modeling. (16)

(or)

b) Write Verilog code for Priority Encoder, D-Latch and Equality detector. (16)

(or)

c) Explain the different types of timing control present in verilog with suitable example
(16)