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Data Sheet
28/40/44-Pin, Low-Power,
High-Performance Microcontrollers
with nanoWatt XLP Technology
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
ISBN: 978-1-60932-752-1
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
ECCP (Half-Bridge)
ECCP (Full-Bridge)
Timers (8/16-bit)
10-bit ADC (ch)
CapSense (ch)
Memory Memory
Comparators
SR Latch
EUSART
Data EEPROM
Device
I/O’s(1)
MSSP
CCP
(bytes)
(bytes)
Words
SRAM
PIC16(L)F1824/1828
PDIP, SOIC, TSSOP
VDD 1 14 VSS
(1) (1)
CCP2 /P2A /T1CKI/T1OSI/OSC1/CLKIN/RA5 2 13 RA0/AN0/CPS0/C1IN+/VREF-/DACOUT/TX(1)/CK(1)/ICSPDAT
T1G(1)/P2B(1)/SDO(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 12 RA1/AN1/CPS1/C12IN0-/VREF+/SRI/RX(1)/DT(1)/ICSPCLK
PIC16F/LF1824
3
(1) (1)
MCLR/VPP/T1G /SS /RA3 4 11 RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/CCP3/FLT0
MDCIN2/DT(1)/RX(1)/CCP1/P1A/RC5 5 10 RC0/AN4/CPS4/C2IN+/SCL/SCK/P1D(1)
MDOUT/CK(1)/TX(1)/P1B/SRNQ/C2OUT/RC4 6 9 RC1/AN5/CPS5/C12IN1-/SDA/SDI/P1C(1)/CCP4
MDMIN/SS(1)/P1C(1)/CCP2(1)/P2A(1)/C12IN3-/CPS7/AN7/RC3 7 8 RC2/AN6/CPS6/C12IN2-/P1D(1)/P2B(1)/SDO(1)/MDCIN1
Preliminary
PIC16(L)F1824/1828
QFN
VDD
VSS
NC
NC
16
15
14
13
CCP2(1)/P2A(1)/T1CKI/T1OSI/OSC1/CLKIN/RA5 1 12 RA0/AN0/CPS0/C1IN+/VREF-/DACOUT/TX(1)/CK(1)/ICSPDAT/ICDDAT
T1G(1)/P2B(1)/SDO(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 2 11 RA1/AN1/CPS1/C12IN0-/VREF+/SRI/RX(1)/DT(1)/ICSPCLK/ICDCLK
PIC16F/LF1824
MCLR/VPP/T1G(1)/SS(1)/RA3 3 10 RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/CCP3//FLT0
MDCIN2/DT(1)/RX(1)/CCP1/P1A/RC5 9 RC0/AN4/CPS4/C2IN+/SCL/SCK/P1D(1)
4
8
Preliminary
RC3/AN7/CPS7/C12IN3-/P2A(1)/CCP2(1)/P1C(1)/MDMIN/SS(1)
RC4/C2OUT/SRNQ/P1B/TX(1)/CK(1)/MDOUT
RC1/AN5/CPS5/C12IN1-/SDA/SDI/P1C(1)/CCP4
RC2/AN6/CPS6/C12IN2-/P1D(1)/P2B(1)/SDO(1)/MDCIN1
2010 Microchip Technology Inc.
14-Pin PDIP/SOIC/TSSOP
Comparator
16-Pin QFN
Cap Sense
Modulator
Reference
SR Latch
EUSART
Interrupt
Pull-up
Timers
MSSP
ECCP
Basic
A/D
I/O
PIC16(L)F1824/1828
PDIP, SOIC, SSOP
VDD 1 20 VSS
(1) (1) RA0/AN0/CPS0/C1IN+/VREF-/DACOUT/ICSPDAT/ICDDAT
CCP2 /P2A /T1CKI/T1OSI/OSC1/CLKIN/RA5 2 19
T1G(1)/P2B(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 3 18 RA1/AN1/CPS1/C12IN0-/VREF+/SRI/ICSPCLK/ICDCLK
PIC16F/LF1828
MCLR/VPP/T1G(1)/RA3 4 17 RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/CCP3/FLT0
MDCIN2/DT(1)/RX(1)/P1A/CCP1/RC5 5 16 RC0/AN4/CPS4/C2IN+/P1D(1)
(1) (1)
MDOUT/CK /TX /P1B/SRNQ/C2OUT/RC4 6 15 RC1/AN5/CPS5/C12IN1-/P1C(1)
MDMIN/P2A(1)/CCP2(1)/P1C(1)/C12IN3-/CPS7/AN7/RC3 7 14 RC2/AN6/CPS6/C12IN2-/P1D(1)/P2B(1)/MDCIN1
SS/CCP4/CPS8/AN8/RC6 8 13 RB4/AN10/CPS10/SDA1/SDI1
SDO/CPS9/AN9/RC7 9 12 RB5/AN11/CPS11/RX(1)/DT(1)
(1) (1)
CK /TX /RB7 10 11 RB6/SCL1/SCK1
Preliminary
QFN
T1G(1)/P2B(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4
ICDDAT/ICSPDAT/DACOUT/VREF-/C1IN+/CPS0/AN0/RA0
CCP2(1)/P2A(1)/T1CKI/T1OS1/OSC1/CLKIN/RA5
Preliminary
VDD
Vss
20
19
18
17
16
MCLR/VPP/T1G(1)/RA3 1 15 RA1/AN1/CPS1/C12IN0-/VREF+/SRI/ICSPCLK/ICDCLK
PIC16(L)F1824/1828
MDCIN2/DT(1)/RX(1)/P1A/CCP1/RC5 2 14 RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/CCP3/FLT0
MDOUT/CK(1)/TX(1)/P1B/SRNQ/C2OUT/RC4 3 PIC16F/LF1828 13 RC0/AN4/CPS4/C2IN+/P1D(1)
MDMIN/P2A(1)/CCP2(1)/P1C(1)/C12IN3-/CPS7/AN7/RC3 4 12 RC1/AN5/CPS5/C12IN1-/P1C(1)
SS/CCP4/CPS8/AN8/RC6 5 11 RC2/AN6/CPS6/C12IN2-/P1D(1)/P2B(1)/MDCIN1
10
6
7
8
9
RC7/AN9/CPS9/SDO
RB6/SCL1/SCK1
RB5/AN11/CPS11/RX(1)/DT(1)
RB4/AN10/CPS10/SDA1/SDI1
RB7/TX(1)/CK(1)
DS41419B-page 9
20-Pin DIP/SOIC/SSOP
Comparator
20-Pin QFN
Cap Sense
Modulator
Reference
SR Latch
EUSART
Interrupt
Pull-up
Timers
Basic
CCP
SSP
A/D
I/O
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
PIC16F/LF1824
PIC16F/LF1828
Peripheral
ADC ● ●
Capacitive Sensing Module (CSM) ● ●
Data EEPROM ● ●
Digital-to-Analog Converter (DAC) ● ●
Digital Signal Modulator (DSM) ● ●
EUSART ● ●
Fixed Voltage Reference (FVR) ● ●
SR Latch ● ●
Capture/Compare/PWM Modules
ECCP1 ● ●
ECCP2 ● ●
CCP3 ● ●
CCP4 ● ●
Comparators
C1 ● ●
C2 ● ●
Master Synchronous Serial Ports
MSSP ● ●
Timers
Timer0 ● ●
Timer1 ● ●
Timer2 ● ●
Timer4 ● ●
Timer6 ● ●
Program
Flash Memory
RAM EEPROM
CLKR
Clock
Reference
OSC2/CLKOUT Timing
Generation PORTA
OSC1/CLKIN INTRC
CPU
Oscillator PORTB(3)
(Figure 2-1)
MCLR
PORTC
ADC
10-Bit Timer0 Timer1 Timer2 Timer4 Timer6 Comparators
SR MSSP
ECCP1 ECCP2 CCP3 CCP4 EUSART
Latch
15 Configuration
15 Data Bus 8
Program Counter
Flash
MUX
Program
Memory 16-Level
8 Level Stack
Stack
RAM
(13-bit)
(15-bit)
Program
14 Program Memory 12 RAM Addr
Bus
Read (PMR)
Addr MUX
Instruction
Instruction Reg
reg Indirect
Direct Addr 7 Addr
5 12 12
15 BSR
FSR Reg
reg
FSR0reg
FSR Reg
FSR1 Reg
FSR reg
15 STATUS Reg
STATUS reg
8
3 MUX
Power-up
Timer
Instruction Oscillator
Decodeand
Decode & Start-up Timer
ALU
Control
OSC1/CLKIN Power-on
Reset 8
Timing Watchdog
OSC2/CLKOUT Generation Timer W reg
Brown-out
Reset
Internal
Oscillator
Block
VDD VSS
Rollover to Page 1
7FFFh
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand.
00h
Core Registers
(12 bytes)
0Bh
0Ch
Special Function Registers
(20 bytes maximum)
1Fh
20h
6Fh
70h
Common RAM
(16 bytes)
7Fh
PIC16(L)F1824/1828
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h INDF0 080h INDF0 100h INDF0 180h INDF0 200h INDF0 280h INDF0 300h INDF0 380h INDF0
001h INDF1 081h INDF1 101h INDF1 181h INDF1 201h INDF1 281h INDF1 301h INDF1 381h INDF1
002h PCL 082h PCL 102h PCL 182h PCL 202h PCL 282h PCL 302h PCL 382h PCL
003h STATUS 083h STATUS 103h STATUS 183h STATUS 203h STATUS 283h STATUS 303h STATUS 383h STATUS
004h FSR0L 084h FSR0L 104h FSR0L 184h FSR0L 204h FSR0L 284h FSR0L 304h FSR0L 384h FSR0L
005h FSR0H 085h FSR0H 105h FSR0H 185h FSR0H 205h FSR0H 285h FSR0H 305h FSR0H 385h FSR0H
006h FSR1L 086h FSR1L 106h FSR1L 186h FSR1L 206h FSR1L 286h FSR1L 306h FSR1L 386h FSR1L
007h FSR1H 087h FSR1H 107h FSR1H 187h FSR1H 207h FSR1H 287h FSR1H 307h FSR1H 387h FSR1H
008h BSR 088h BSR 108h BSR 188h BSR 208h BSR 288h BSR 308h BSR 388h BSR
009h WREG 089h WREG 109h WREG 189h WREG 209h WREG 289h WREG 309h WREG 389h WREG
00Ah PCLATH 08Ah PCLATH 10Ah PCLATH 18Ah PCLATH 20Ah PCLATH 28Ah PCLATH 30Ah PCLATH 38Ah PCLATH
00Bh INTCON 08Bh INTCON 10Bh INTCON 18Bh INTCON 20Bh INTCON 28Bh INTCON 30Bh INTCON 38Bh INTCON
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch — 30Ch — 38Ch INLVLA
00Dh PORTB(1) 08Dh TRISB(1) 10Dh LATB(1) 18Dh ANSELB(1) 20Dh WPUB(1) 28Dh — 30Dh — 38Dh INLVLB(1)
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh — 30Eh — 38Eh INLVLC
00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh —
010h — 090h — 110h — 190h — 210h — 290h — 310h — 390h —
011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSP1BUF 291h CCPR1L 311h CCPR3L 391h IOCAP
012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSP1ADD 292h CCPR1H 312h CCPR3H 392h IOCAN
013h PIR3 093h PIE3 113h CM2CON0 193h EEDATL 213h SSP1MSK 293h CCP1CON 313h CCP3CON 393h IOCAF
014h — 094h — 114h CM2CON1 194h EEDATH 214h SSP1STAT 294h PWM1CON 314h — 394h IOCBP(1)
Preliminary
015h TMR0 095h OPTION 115h CMOUT 195h EECON1 215h SSP1CON 295h CCP1AS 315h — 395h IOCBN(1)
016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSP1CON2 296h PSTR1CON 316h — 396h IOCBF(1)
017h TMR1H 097h WDTCON 117h FVRCON 197h — 217h SSP1CON3 297h — 317h — 397h —
018h T1CON 098h OSCTUNE 118h DACCON0 198h — 218h — 298h CCPR2L 318h CCPR4L 398h —
019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h — 299h CCPR2H 319h CCPR4H 399h —
01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah — 29Ah CCP2CON 31Ah CCP4CON 39Ah CLKRCON
01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh — 29Bh PWM2CON 31Bh — 39Bh —
01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch CCP2AS 31Ch — 39Ch MDCON
01Dh — 09Dh ADCON0 11Dh APFCON0 19Dh RCSTA 21Dh — 29Dh PSTR2CON 31Dh — 39Dh MDSRC
01Eh CPSCON0 09Eh ADCON1 11Eh APFCON1 19Eh TXSTA 21Eh — 29Eh CCPTMRS0 31Eh — 39Eh MDCARL
01Fh CPSCON1 09Fh — 11Fh — 19Fh BAUDCON 21Fh — 29Fh CCPTMRS1 31Fh — 39Fh MDCARH
020h 0A0h 120h 1A0h 220h 2A0h 320h General Purpose 3A0h
General General General General General Register
Purpose Purpose Purpose Purpose Purpose 32Fh 16 Bytes(2) Unimplemented
2010 Microchip Technology Inc.
PIC16(L)F1824/1828
41Ch TMR6 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71Ch — 79Ch —
41Dh PR6 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh —
41Eh T6CON 49Eh — 51Eh — 59Eh — 61Eh — 69Eh — 71Eh — 79Eh —
41Fh — 49Fh — 51Fh — 59Fh — 61Fh — 69Fh — 71Fh — 79Fh —
420h 4A0h 520h 5A0h 620h 6A0h 720h 7A0h
PIC16(L)F1824/1828
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h INDF0 880h INDF0 900h INDF0 980h INDF0 A00h INDF0 A80h INDF0 B00h INDF0 B80h INDF0
801h INDF1 881h INDF1 901h INDF1 981h INDF1 A01h INDF1 A81h INDF1 B01h INDF1 B81h INDF1
802h PCL 882h PCL 902h PCL 982h PCL A02h PCL A82h PCL B02h PCL B82h PCL
803h STATUS 883h STATUS 903h STATUS 983h STATUS A03h STATUS A83h STATUS B03h STATUS B83h STATUS
804h FSR0L 884h FSR0L 904h FSR0L 984h FSR0L A04h FSR0L A84h FSR0L B04h FSR0L B84h FSR0L
805h FSR0H 885h FSR0H 905h FSR0H 985h FSR0H A05h FSR0H A85h FSR0H B05h FSR0H B85h FSR0H
806h FSR1L 886h FSR1L 906h FSR1L 986h FSR1L A06h FSR1L A86h FSR1L B06h FSR1L B86h FSR1L
807h FSR1H 887h FSR1H 907h FSR1H 987h FSR1H A07h FSR1H A87h FSR1H B07h FSR1H B87h FSR1H
808h BSR 888h BSR 908h BSR 988h BSR A08h BSR A88h BSR B08h BSR B88h BSR
809h WREG 889h WREG 909h WREG 989h WREG A09h WREG A89h WREG B09h WREG B89h WREG
80Ah PCLATH 88Ah PCLATH 90Ah PCLATH 98Ah PCLATH A0Ah PCLATH A8Ah PCLATH B0Ah PCLATH B8Ah PCLATH
80Bh INTCON 88Bh INTCON 90Bh INTCON 98Bh INTCON A0Bh INTCON A8Bh INTCON B0Bh INTCON B8Bh INTCON
80Ch — 88Ch — 90Ch — 98Ch — A0Ch — A8Ch — B0Ch — B8Ch —
80Dh — 88Dh — 90Dh — 98Dh — A0Dh — A8Dh — B0Dh — B8Dh —
80Eh — 88Eh — 90Eh — 98Eh — A0Eh — A8Eh — B0Eh — B8Eh —
80Fh — 88Fh — 90Fh — 98Fh — A0Fh — A8Fh — B0Fh — B8Fh —
810h — 890h — 910h — 990h — A10h — A90h — B10h — B90h —
811h — 891h — 911h — 991h — A11h — A91h — B11h — B91h —
812h — 892h — 912h — 992h — A12h — A92h — B12h — B92h —
Preliminary
PIC16(L)F1824/1828
C19h — C99h — D19h — D99h — E19h — E99h — F19h — F99h details
C1Ah — C9Ah — D1Ah — D9Ah — E1Ah — E9Ah — F1Ah — F9Ah
C1Bh — C9Bh — D1Bh — D9Bh — E1Bh — E9Bh — F1Bh — F9Bh
C1Ch — C9Ch — D1Ch — D9Ch — E1Ch — E9Ch — F1Ch — F9Ch
C1Dh — C9Dh — D1Dh — D9Dh — E1Dh — E9Dh — F1Dh — F9Dh
C1Eh — C9Eh — D1Eh — D9Eh — E1Eh — E9Eh — F1Eh — F9Eh
C1Fh — C9Fh — D1Fh — D9Fh — E1Fh — E9Fh — F1Fh — F9Fh
C20h CA0h D20h DA0h E20h EA0h F20h FA0h
Bank 1
080h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
081h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
082h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
083h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
084h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
085h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
086h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
087h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
088h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000
089h(1) WREG Working Register 0000 0000 uuuu uuuu
08Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
08Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
08Ch TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
08Dh TRISB(2) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ----
08Eh TRISC TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
08Fh — Unimplemented — —
090h — Unimplemented — —
091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
092h PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE 0000 0--0 0000 0--0
093h PIE3 — — CCP4IE CCP3IE TMR6IE — TMR4IE — --00 0-0- --00 0-0-
094h — Unimplemented — —
095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111
096h PCON STKOVF STKUNF — — RMCLR RI POR BOR 00-- 11qq qq-- qquu
097h WDTCON — — WDTPS<4:0> SWDTEN --01 0110 --01 0110
098h OSCTUNE — — TUN<5:0> --00 0000 --00 0000
099h OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 0011 1-00 0011 1-00
09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q
09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0 — CHS<4:0> GO/DONE ADON -000 0000 -000 0000
09Eh ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 0000 -000 0000 -000
09Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: PIC16F/LF1828 only.
3: PIC16F/LF1824 only.
Bank 2
100h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
101h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
102h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
103h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
104h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
105h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
106h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
107h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
108h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000
109h(1) WREG Working Register 0000 0000 uuuu uuuu
10Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
10Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
10Ch LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu
10Dh LATB(2) LATB7 LATB6 LATB5 LATB4 — — — — xxxx ---- xxxx ----
10Eh LATC LATC7(2) LATC6(2) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu
10Fh — Unimplemented — —
110h — Unimplemented — —
111h CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -100
112h CM1CON1 C1INTP C1INTN C1PCH<1:0> — — C1NCH1 C1NCH0 0000 ---0 0000 ---0
113h CM2CON0 C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 0000 -100 0000 -100
114h CM2CON1 C2INTP C2INTN C2PCH<1:0> — — C2NCH<1:0> 0000 --00 0000 --00
115h CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00
116h BORCON SBOREN — — — — — — BORRDY 1--- ---q u--- ---u
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
118h DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 000- 00-0 000- 00-0
119h DACCON1 — — — DACR<4:0> ---0 0000 ---0 0000
11Ah SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000
11Bh SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000
11Ch — Unimplemented — —
11Dh APFCON0 RXDTSEL SDOSEL(3) SSSEL(3) — T1GSEL TXCKSEL — — 000- 0000 000- 0000
11Eh APFCON1 — — — — P1DSEL P1CSEL P2BSEL CCP2SEL --00 0000 --00 0000
11Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: PIC16F/LF1828 only.
3: PIC16F/LF1824 only.
Bank 3
180h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
181h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
182h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
183h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
184h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
185h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
186h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
187h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
188h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000
189h(1) WREG Working Register 0000 0000 uuuu uuuu
18Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
18Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111
18Dh ANSELB(2) ANSB7 ANSB6 ANSB5 ANSB4 — — — — 1111 ---- 1111 ----
18Eh ANSELC ANSC7(2) ANSC6(2) — — ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111
18Fh — Unimplemented — —
190h — Unimplemented — —
191h EEADRL EEPROM/Program Memory Address Register Low Byte 0000 0000 0000 0000
192h EEADRH — EEPROM/Program Memory Address Register High Byte -000 0000 -000 0000
193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h EEDATH — — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000
196h EECON2 EEPROM control register 2 0000 0000 0000 0000
197h — Unimplemented — —
198h — Unimplemented — —
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000
19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: PIC16F/LF1828 only.
3: PIC16F/LF1824 only.
Bank 4
200h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
201h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
202h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
203h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
204h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
205h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
206h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
207h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
208h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000
209h(1) WREG Working Register 0000 0000 uuuu uuuu
20Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
20Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
20Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111
20Dh WPUB(2) WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ----
20Eh WPUC WPUC7(2) WPUC6(2) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111
20Fh — Unimplemented — —
210h — Unimplemented — —
211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
212h SSP1ADD ADD<7:0> 0000 0000 0000 0000
213h SSP1MSK MSK<7:0> 1111 1111 1111 1111
214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
218h — Unimplemented — —
219h — Unimplemented — —
21Ah — Unimplemented — —
21Bh — Unimplemented — —
21Ch — Unimplemented — —
21Dh — Unimplemented — —
21Eh — Unimplemented — —
21Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: PIC16F/LF1828 only.
3: PIC16F/LF1824 only.
Bank 5
280h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
281h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
282h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
283h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
284h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
285h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
286h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
287h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
288h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000
289h(1) WREG Working Register 0000 0000 uuuu uuuu
28Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
28Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
28Ch — Unimplemented — —
28Dh — Unimplemented — —
28Eh — Unimplemented — —
28Fh — Unimplemented — —
290h — Unimplemented — —
291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 0000 0000
294h PWM1CON P1RSEN P1DC<6:0> 0000 0000 0000 0000
295h CCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000 0000 0000
296h PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001
297h — Unimplemented — —
298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
29Ah CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000
29Bh PWM2CON P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 0000 0000
29Ch CCP2AS CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000
29Dh PSTR2CON — — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 ---0 0001
29Eh CCPTMRS C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000
29Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: PIC16F/LF1828 only.
3: PIC16F/LF1824 only.
Bank 6
300h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
301h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
302h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
303h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
304h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
305h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
306h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
307h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
308h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000
309h(1) WREG Working Register 0000 0000 uuuu uuuu
30Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
30Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
30Ch — Unimplemented — —
30Dh — Unimplemented — —
30Eh — Unimplemented — —
30Fh — Unimplemented — —
310h — Unimplemented — —
311h CCPR3L Capture/Compare/PWM Register 3 (LSB) xxxx xxxx uuuu uuuu
312h CCPR3H Capture/Compare/PWM Register 3 (MSB) xxxx xxxx uuuu uuuu
313h CCP3CON — — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000
314h — Unimplemented — —
315h — Unimplemented — —
316h — Unimplemented — —
317h — Unimplemented — —
318h CCPR4L Capture/Compare/PWM Register 4 (LSB) xxxx xxxx uuuu uuuu
319h CCPR4H Capture/Compare/PWM Register 4 (MSB) xxxx xxxx uuuu uuuu
31Ah CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 --00 0000
31Bh — Unimplemented — —
31Ch — Unimplemented — —
31Dh — Unimplemented — —
31Eh — Unimplemented — —
31Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: PIC16F/LF1828 only.
3: PIC16F/LF1824 only.
Bank 7
380h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
381h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
382h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
383h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
384h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
385h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
386h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
387h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
388h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000
389h(1) WREG Working Register 0000 0000 uuuu uuuu
38Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
38Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
38Ch INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 --00 0100 --00 0100
38Dh INLVLB(2) INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 0000 ---- 0000 ----
38Eh INLVLC INLVLC7(2) INLVLC6(2) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 11xx xxxx 11xx xxxx
38Fh — Unimplemented — —
390h — Unimplemented — —
391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000
392h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000
393h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000
394h IOCBP(2) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 0000 ---- 0000 ----
395h IOCBN(2) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 0000 ---- 0000 ----
396h IOCBF(2) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 0000 ---- 0000 ----
397h — Unimplemented — —
398h — Unimplemented — —
399h — Unimplemented — —
39Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> 0011 0000 0011 0000
39Bh — Unimplemented — —
39Ch MDCON MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT 0010 ---0 0010 ---0
39Dh MDSRC MDMSODIS — — — MDMS<3:0> x--- xxxx u--- uuuu
39Eh MDCARL MDCLODIS MDCLPOL MDCLSYNC — MDCL<3:0> xxx- xxxx uuu- uuuu
39Fh MDCARH MDCHODIS MDCHPOL MDCHSYNC — MDCH<3:0> xxx- xxxx uuu- uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: PIC16F/LF1828 only.
3: PIC16F/LF1824 only.
Bank 8
400h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
401h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
402h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
403h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
404h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
405h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
406h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
407h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
408h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000
409h(1) WREG Working Register 0000 0000 uuuu uuuu
40Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
40Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
40Ch — Unimplemented — —
40Dh — Unimplemented — —
40Eh — Unimplemented — —
40Fh — Unimplemented — —
410h — Unimplemented — —
411h — Unimplemented — —
412h — Unimplemented — —
413h — Unimplemented — —
414h — Unimplemented — —
415h TMR4 Timer4 Module Register 0000 0000 0000 0000
416h PR4 Timer4 Period Register 1111 1111 1111 1111
417h T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000 -000 0000
418h — Unimplemented — —
419h — Unimplemented — —
41Ah — Unimplemented — —
41Bh — Unimplemented — —
41Ch TMR6 Timer6 Module Register 0000 0000 0000 0000
41Dh PR6 Timer6 Period Register 1111 1111 1111 1111
41Eh T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> -000 0000 -000 0000
41Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: PIC16F/LF1828 only.
3: PIC16F/LF1824 only.
Banks 9-30
x00h/ INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
x80h(1) (not a physical register)
x00h/ INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
x81h(1) (not a physical register)
x02h/ PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h(1)
x03h/ STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
x83h(1)
x04h/ FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x84h(1)
x05h/ FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h(1)
x06h/ FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x86h(1)
x07h/ FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x87h(1)
x08h/ BSR — — — BSR<4:0> ---0 0000 ---0 0000
x88h(1)
x09h/ WREG Working Register 0000 0000 uuuu uuuu
x89h(1)
x0Ah/ PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x8Ah(1)
x0Bh/ INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
x8Bh(1)
x0Ch/ — Unimplemented — —
x8Ch
—
x1Fh/
x9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: PIC16F/LF1828 only.
3: PIC16F/LF1824 only.
Bank 31
F80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
F81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory xxxx xxxx xxxx xxxx
(not a physical register)
F82h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
F83h(1) STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
F84h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
F85h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
F86h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
F87h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
F88h(1) BSR — — — BSR<4:0> ---0 0000 ---0 0000
F89h(1) WREG Working Register 0000 0000 uuuu uuuu
F8Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
F8Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u
F8Ch — Unimplemented — —
—
FE3h
FE4h STATUS_ — — — — — Z DC C ---- -xxx ---- -uuu
SHAD
FE5h WREG_ Working Register Shadow 0000 0000 uuuu uuuu
SHAD
FE6h BSR_ — — — Bank Select Register Shadow ---x xxxx ---u uuuu
SHAD
FE7h PCLATH_ — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu
SHAD
FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FEAh FSR1L_ Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FECh — Unimplemented — —
FEDh STKPTR — — — Current Stack pointer ---1 1111 ---1 1111
FEEh TOSL Top-of-Stack Low byte xxxx xxxx uuuu uuuu
FEFh TOSH — Top-of-Stack High byte -xxx xxxx -uuu uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: PIC16F/LF1828 only.
3: PIC16F/LF1824 only.
14 PCH PCL 0
PC BRA
15
PC + OPCODE <8:0>
0x0C
0x0B
0x0A
Initial Stack Configuration:
0x09
After Reset, the stack is empty. The
0x08 empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
0x07
Overflow/Underflow Reset is enabled, the
0x06 TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
0x05 disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
0x04
0x03
0x02
0x01
0x00
Stack Reset Enabled
TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F
(STVREN = 1)
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09 This figure shows the stack configuration
after the first CALL or a single interrupt.
0x08 If a RETURN instruction is executed, the
0x07 return address will be placed in the
Program Counter and the Stack Pointer
0x06 decremented to the empty state (0x1F).
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL 0x00 Return Address STKPTR = 0x00
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
0x0B interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
0x0A will repeatedly place the return addresses
into the Program Counter and pop the stack.
0x09
0x08
0x07
TOSH:TOSL 0x06 Return Address STKPTR = 0x06
0x0000 0x0000
Traditional
Data Memory
0x0FFF 0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR Reserved
0x7FFF
Address
Range 0x8000 0x0000
Program
Flash Memory
0xFFFF 0x7FFF
Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.
0x7F
Bank 0 Bank 1 Bank 2 Bank 31
0xF20
Bank 30 0x7FFF
0xFFFF
0x29AF 0xF6F
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared P = Programmable bit
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off during an erase.
3: The entire program memory will be erased when the code protection is turned off.
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off during an erase.
3: The entire program memory will be erased when the code protection is turned off.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared P = Programmable bit
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and
programmers. For normal device operation, this bit should be maintained as a ‘1’.
4.4 User ID
Four memory locations (8000h-8003h) are designated as
ID locations where the user can store checksum or other
code identification numbers. These locations are
readable and writable during normal execution. See
Section 11.5 “User ID, Device ID and Configuration
Word Access” for more information on accessing these
memory locations. For more information on checksum
calculation, see the “PIC16F/LF182X/PIC12F/LF1822
Memory Programming Specification” (DS41390).
R R R R R R R
DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
bit 6 bit 0
External
Oscillator LP, XT, HS, RC, EC
OSC2
Sleep
4 x PLL Sleep
OSC1
Oscillator Timer1 FOSC<2:0> = 100 T1OSC CPU and
MUX
T1OSO Peripherals
T1OSCEN
Enable
T1OSI Oscillator IRCF<3:0>
Internal Oscillator
16 MHz
8 MHz
Internal
Oscillator 4 MHz
Block 2 MHz
Postscaler 1 MHz Clock
HFPLL Control
MUX
16 MHz 500 kHz
(HFINTOSC) 250 kHz
125 kHz FOSC<2:0> SCS<1:0>
500 kHz
Source 500 kHz 62.5 kHz
(MFINTOSC) 31.25 kHz Clock Source Option
31 kHz for other modules
31 kHz
Source
OSC1/CLKIN OSC1/CLKIN
C1 To Internal C1 To Internal
Logic Logic
Quartz
RF(2) Sleep RP(3)
Crystal RF(2) Sleep
C2 OSC2/CLKOUT
RS(1) OSC2/CLKOUT
C2 Ceramic RS(1)
Resonator
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M. 2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator
according to type, package and operation.
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application. 5.2.1.3 Oscillator Start-up Timer (OST)
2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS
the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts
expected for the application. 1024 oscillations from OSC1. This occurs following a
3: For oscillator design assistance, reference Power-on Reset (POR) and when the Power-up Timer
the following Microchip Applications Notes: (PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
• AN826, “Crystal Oscillator Basics and increment and program execution is suspended. The
Crystal Selection for rfPIC® and PIC® OST ensures that the oscillator circuit, using a quartz
Devices” (DS00826) crystal resonator or ceramic resonator, has started and
• AN849, “Basic PIC® Oscillator Design” is providing a stable system clock to the oscillator
(DS00849) module.
• AN943, “Practical PIC® Oscillator In order to minimize latency between external oscillator
Analysis and Design” (DS00943) start-up and code execution, the Two-Speed Clock
• AN949, “Making Your Oscillator Work” Start-up mode can be selected (see Section 5.4
(DS00949) “Two-Speed Clock Start-up Mode”).
5.2.1.4 4X PLL
The oscillator module contains a 4X PLL that can be
used with both external and internal clock sources to
provide a system clock source. The input frequency for
the 4X PLL must fall within specifications. See the PLL
Clock Timing Specifications in Section 30.0
“Electrical Specifications”.
The 4X PLL may be enabled for use by one of two
methods:
1. Program the PLLEN bit in Configuration Word 2
to a ‘1’.
2. Write the SPLLEN bit in the OSCCON register to
a ‘1’. If the PLLEN bit in Configuration Word 2 is
programmed to a ‘1’, then the value of SPLLEN
is ignored.
LFINTOSC
System Clock
LFINTOSC
System Clock
LFINTOSC HFINTOSC/MFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Start-up Time 2-cycle Sync Running
HFINTOSC/
MFINTOSC
IRCF <3:0> =0 0
System Clock
• Default system oscillator determined by FOSC The Timer1 oscillator is enabled using the T1OSCEN
bits in Configuration Word 1 control bit in the T1CON register. See Section 21.0
“Timer1 Module with Gate Control” for more
• Timer1 32 kHz crystal oscillator
information about the Timer1 peripheral.
• Internal Oscillator Block (INTOSC)
5.3.4 TIMER1 OSCILLATOR READY
5.3.1 SYSTEM CLOCK SELECT (SCS)
(T1OSCR) BIT
BITS
The user must ensure that the Timer1 Oscillator is
The System Clock Select (SCS) bits of the OSCCON
ready to be used before it is selected as a system clock
register selects the system clock source that is used for
source. The Timer1 Oscillator Ready (T1OSCR) bit of
the CPU and peripherals.
the OSCSTAT register indicates whether the Timer1
• When the SCS bits of the OSCCON register = 00, oscillator is ready to be used. After the T1OSCR bit is
the system clock source is determined by value of set, the SCS bits can be configured to select the Timer1
the FOSC<2:0> bits in the Configuration Word 1. oscillator.
• When the SCS bits of the OSCCON register = 01,
the system clock source is the Timer1 oscillator.
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
Note: Any automatic clock switch, which may
occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the
current system clock source.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These oscil-
lator delays are shown in Table 5-1.
INTOSC
TOST
OSC2
Program Counter PC - N PC PC + 1
System Clock
Sample Clock
System Oscillator
Clock Failure
Output
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: If the base clock rate is selected without 6.4 Operation During Sleep
a divider, the output clock will always
have a duty cycle equal to that of the As the reference clock module relies on the system
source clock, unless a 0% duty cycle is clock as its source, and the system clock is disabled in
selected. If the clock divider is set to base Sleep, the module does not function in Sleep, even if
clock/2, then 25% and 75% duty cycle an external clock source or the Timer1 clock source is
accuracy will be dependent upon the configured as the system clock. The module outputs
source clock. will remain in their current state until the device exits
Sleep.
For information on using the reference clock output
with the modulator module, see Section 23.0 “Data
Signal Modulator”.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.
2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%
is selected.
3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration
Word 1 = 0 will result in FOSC/4. See Section 6.3 “Conflicts with the CLKR pin” for details.
External Reset
MCLRE
MCLR
Sleep
WDT
Time-out
Device
Power-on Reset
Reset
VDD
Brown-out
Reset
BOR
Enable
PWRT
Zero
64 ms
LFINTOSC
PWRTEN
SBOREN
TBORRDY
BORRDY BOR Protection Active
VDD
VBOR
Internal
Reset TPWRT(1)
VDD
VBOR
VDD
VBOR
Internal
Reset TPWRT(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-Up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
CLKIN
FOSC
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
INTF
Interrupt to CPU
INTE
IOCIF
IOCIE
From Peripheral Interrupt
Logic (Figure 8-2)
PEIE
GIE
TMR1GIF
TMR1GIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
EEIF
EEIE
OSFIF
OSFIE
C1IF
C1IE
C2IF
C2IE
BCL1IF
BCL1IE
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt
GIE
Interrupt
GIE
Interrupt
GIE
Interrupt
GIE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF (5) Interrupt Latency (2)
GIE
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The IOCIF Flag bit is read only and cleared when all the Interrupt-on-Change flags in the IOCxF register
have been cleared by software.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
GIE bit
(INTCON reg.) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle
Executed Inst(PC - 1) Inst(0004h)
WDTE<1:0> = 01
SWDTEN
WDTE Device WDT When a WDT time-out occurs while the device is in
Config bits
SWDTEN
Mode Mode Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
WDT_ON (11) X X Active in the STATUS register are changed to indicate the
event. See Section 3.0 “Memory Organization” and
WDT_NSLEEP (10) X Awake Active The STATUS register (Register 3-1) for more
WDT_NSLEEP (10) X Sleep Disabled information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
MOVLW 0AAh ;
MOVWF EECON2 ;Write AAh
BSF EECON1, WR ;Set WR bit to begin write
BSF INTCON, GIE ;Enable Interrupts
BCF EECON1, WREN ;Disable writes
BTFSC EECON1, WR ;Wait for write to complete
GOTO $-2 ;Done
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDATL INSTR (PC + 3) INSTR (PC + 4)
RD bit
EEDATH
EEDATL
Register
EERHLT
FIGURE 11-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
7 5 0 7 0
EEDATH EEDATA
6 8
14 14 14 14
Program Memory
MOVLW 0AAh ;
Required
START_WRITE
BCF EECON1,LWLO ; No more loading latches - Actually start Flash program
; memory write
MOVLW 0AAh ;
Required
TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address Function Read Access Write Access
8000h-8003h User IDs Yes Yes
8006h Device ID/Revision ID Yes No
8007h-8008h Configuration Words 1 and 2 Yes No
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
A write operation to the LATx register has the same These bits have no effect on the values of any TRIS
affect as a write to the corresponding PORTx register. register. PORT and TRIS overrides will be routed to the
A read of the LATx register reads of the values held in correct pin. The unselected pin will be unaffected.
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
Ports with analog functions also have an ANSELx
register which can disable the digital input and save
power. A simplified model of a generic I/O port, without
the interfaces to other peripherals, is shown in
Figure 12-1.
Read LATx
TRISx
D Q
Write LATx
Write PORTx
CK VDD
Data Register
Data Bus
I/O pin
Read PORTx
To peripherals
VSS
ANSELx
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 ANSB<7:4>: Analog Select between Analog or Digital Function on pins RB<7:4>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 3-0 Unimplemented: Read as ‘0’
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external
control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: RC<7:6> available on PIC16F/LF1828 only. Otherwise, they are unimplemented and read as ‘0’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: TRISC<7:6> available on PIC16F/LF1828 only. Otherwise, they are unimplemented and read as ‘0’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
2: LATC<7:6> available on PIC16F/LF1828 only. Otherwise, they are unimplemented and read as ‘0’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively(1)
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
2: ANSELC<7:6> available on PIC16F/LF1828 only. Otherwise, they are unimplemented and read as ‘0’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
3: WPUC<7:6> available on PIC16F/LF1828 only. Otherwise, they are unimplemented and read as ‘0’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: INLVLC<7:6> available on PIC16F/LF1828 only. Otherwise, they are unimplemented and read as ‘0’.
IOCIE
IOCANx D Q IOCAFx
IOCAPx D Q
CK
Q2 Clock Cycle
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
• ADC input channel The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
• ADC positive reference
for the reference supplied to the ADC module. Refer-
• Comparator positive input ence Section 16.0 “Analog-to-Digital Converter
• Digital-to-Analog Converter (DAC) (ADC) Module” for additional information.
The FVR can be enabled by setting the FVREN bit of The CDAFVR<1:0> bits of the FVRCON register are
the FVRCON register. used to enable and configure the gain amplifier settings
for the reference supplied to the DAC and comparator
module. Reference Section 17.0 “Digital-to-Analog
Converter (DAC) Module” and Section 19.0 “Com-
parator Module” for additional information.
ADFVR<1:0>
2
X1
X2 FVR BUFFER1
X4 (To ADC Module)
CDAFVR<1:0> 2
X1
X2 FVR BUFFER2
X4 (To Comparators, DAC)
+
FVREN 1.024V Fixed
FVRRDY _ Reference
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 146
Legend: Shaded cells are unused by the Fixed Voltage Reference module.
VREF- ADNREF = 1
ADNREF = 0
VSS
VDD
ADPREF = 00
ADPREF = 11
VREF+ ADPREF = 10
AN0 00000
AN1 00001
AN2 00010
AN3 00011
AN4 00100
AN5 00101
AN6 00110
AN7 00111
AN8(2) 01000 ADC
(2)
AN9 01001 10
GO/DONE
AN10(2) 01010
AN11(2) 01011 0 = Left Justify
ADFM
1 = Right Justify
ADON 16
CHS<4:0>
ADC
ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Clock Source
Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
Fosc/4 100 125 ns (2)
200 ns (2)
250 ns (2)
500 ns (2)
1.0 s 4.0 s
Fosc/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3)
Fosc/16 101 800 ns 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3)
Fosc/32 010 1.0 s 1.6 s 2.0 s 4.0 s 8.0 s(3) 32.0 s(3)
Fosc/64 110 2.0 s 3.2 s 4.0 s 8.0 s(3) 16.0 s(3) 64.0 s(3)
FRC x11 1.0-6.0 s (1,4)
1.0-6.0 s (1,4)
1.0-6.0 s (1,4)
1.0-6.0 s (1,4)
1.0-6.0 s (1,4)
1.0-6.0 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
Note: A device Reset forces all registers to their Using the Special Event Trigger does not assure proper
Reset state. Thus, the ADC module is ADC timing. It is the user’s responsibility to ensure that
turned off and any pending conversion is the ADC timing requirements are met.
terminated. Refer to Section 24.0 “Capture/Compare/PWM
Modules” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: See Section 17.0 “Digital-to-Analog Converter (DAC) Module”for more information.
2: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.
3: PIC16F/LF1828 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a
minimum voltage specification exists. See Section 30.0 “Electrical Specifications” for details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C + Temperature - 25°C 0.05µs/°C
V AP P LI ED 1 – -------------------------- = V CHOLD
1
;[1] VCHOLD charged to within 1/2 lsb
n+1
2 –1
–TC
----------
RC
V AP P LI ED 1 – e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
– Tc
---------
V AP P LI ED 1 – e = V A PP LIE D 1 – -------------------------- ;combining [1] and [2]
RC 1
n+1
2 –1
T C = – C HOLD R IC + R SS + R S ln(1/511)
= – 10pF 1k + 7k + 10k ln(0.001957)
= 1.12 µs
Therefore:
T A CQ = 2µs + 1.12µs + 50°C- 25°C 0.05 µs/°C
= 4.42µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
VDD
Analog Sampling
Input Switch
VT 0.6V
Rs pin RIC 1k SS Rss
VA CPIN I LEAKAGE(1)
VT 0.6V CHOLD = 10 pF
5 pF
VSS/VREF-
6V
5V RSS
Legend: CHOLD = Sample/Hold Capacitance VDD 4V
3V
CPIN = Input Capacitance 2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 10 11
RIC = Interconnect Resistance
Sampling Switch
RSS = Resistance of Sampling Switch (k)
SS = Sampling Switch
VT = Threshold Voltage
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB
VREF- Zero-Scale
Transition Full-Scale
Transition VREF+
FVR BUFFER2
VSRC+
VDD DACR<4:0>
5
VREF+
R
R
DACPSS<1:0>
2
R
DACEN
DACLPS R
32-to-1 MUX
32
Steps DAC
(To Comparator, CSM and
ADC Modules)
R
R
DACOUT
R
1 DACOE
DACNSS
VREF- VSRC-
VSS
PIC® MCU
DAC
R
Module
+
Voltage DACOUT Buffered DAC Output
–
Reference
Output
Impedance
Output Clamped to Positive Voltage Source Output Clamped to Negative Voltage Source
VSRC+ VSRC+
R R
DACR<4:0> = 11111
R R
DACEN = 0 DACEN = 0
DACLPS = 1 DAC Voltage Ladder DACLPS = 0 DAC Voltage Ladder
(see Figure 17-1) (see Figure 17-1)
R R
DACR<4:0> = 00000
VSRC- VSRC-
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The output select bits are always right justified to ensure that any number of bits can be used without
affecting the register layout.
SRLEN
SRPS Pulse SRQEN
Gen(2)
SRI
SRSPE S Q
SRCLK
SRQ
SRSCKE
SYNCC2OUT(3)
SRSC2E
SYNCC1OUT(3)
SR
SRSC1E
Latch(1)
SRPR Pulse
Gen(2)
SRI
SRRPE R Q
SRCLK SRNQ
SRRCKE SRLEN
SYNCC2OUT(3) SRNQEN
SRRC2E
SYNCC1OUT(3)
SRRC1E
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared S = Bit is set only
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
det
C12IN0- 0 Set CxIF
C12IN1- 1
MUX Interrupt CxINTN
C12IN2- 2 (2) det
CXPOL
C12IN3- 3 CxVN
-
CXOUT To Data Bus
D Q
Cx(3) MCXOUT
+
CxVP
Q1 EN
CXIN+ 0
MUX CxHYS
DAC 1 (2) CxSP
To ECCP PWM Logic
FVR Buffer2 2
3
CXSYNC
VSS CxON CXOE
TRIS bit
CXOUT
CXPCH<1:0> 0
2
D Q 1
(from Timer1)
T1CLK To Timer1 or SR Latch
SYNCCXOUT
Note 1: When CxON = 0, the Comparator will produce a ‘0’ at the output
2: When CxON = 0, all multiplexer inputs are disconnected.
3: Output of comparator can be frozen during debugging.
CPIN ILEAKAGE(1)
VA VT 0.6V
5 pF
Vss
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
FOSC/4
Data Bus
0
8
T0CKI 1
0 Sync
1 2 TCY TMR0
0
From CPSCLK
1
TMR0SE TMR0CS Set Flag bit TMR0IF
8-bit on Overflow
Prescaler PSA
T0XCS
Overflow to Timer1
PS<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
000 1:2
001 1:4
010 1:8
011 1 : 16
100 1 : 32
101 1 : 64
110 1 : 128
111 1 : 256
T1GSS<1:0>
T1G 00 T1GSPM
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Cleared by
TMR1GIF Cleared by software Set by hardware on software
falling edge of T1GVAL
TMR1GE
T1GPOL
T1GSPM
T1GTM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
TMR1CS<1:0> = 0X
This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.
bit 1 Unimplemented: Read as ‘0’
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Clears Timer1 Gate flip-flop
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
Sets Flag
TMRx
bit TMRxIF
Output
Prescaler Reset
FOSC/4 TMRx
1:1, 1:4, 1:16, 1:64
2 Postscaler
Comparator
EQ 1:1 to 1:16
TxCKPS<1:0>
PRx 4
TxOUTPS<3:0>
A 4-bit counter/prescaler on the clock input allows direct Timer2 can be optionally used as the shift clock source
input, divide-by-4 and divide-by-16 prescale options. for the MSSPx modules operating in SPI mode.
These options are selected by the prescaler control bits, Additional information is provided in Section 25.0
TxCKPS<1:0> of the TxCON register. The value of “Master Synchronous Serial Port Module”.
TMRx is compared to that of the Period register, PRx, on
each clock cycle. When the two values match, the 22.4 Timer2/4/6 Operation During Sleep
comparator generates a match signal as the timer
The Timer2/4/6 timers cannot be operated while the
output. This signal also resets the value of TMRx to 00h
processor is in Sleep mode. The contents of the TMRx
on the next cycle and drives the output
and PRx registers will remain unchanged while the
counter/postscaler (see Section 22.2 “Timer2/4/6
processor is in Sleep mode.
Interrupt”).
The TMRx and PRx registers are both directly readable
and writable. The TMRx register is cleared on any
device Reset, whereas the PRx register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMRx register
• a write to the TxCON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
Note: TMRx is not cleared when TxCON is
written.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
MDBIT 0000
MDMIN 0001
CCP1 0010 0
CCP2 0011
CCP3 0100 MDCHSYNC
CCP4 0101
Comparator C1 0110 MOD
Comparator C2 0111
MSSP1 SDO1 1000 MDOUT
MSSP2 SDO2 1001
EUSART 1010 MDOE
MDOPOL
Reserved 0011
No Channel *
*
Selected 1111
D
MDCL<3:0> SYNC
Q 1
VSS 0000
MDCIN1 0001
MDCIN2 0010
CLKR 0011 0
CCP1 0100
CCP2 0101 CARL MDCLSYNC
CCP3 0110
CCP4 0111
1000
Reserved
* MDCLPOL
No Channel
Selected *
1111
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
MDCHSYNC = 1
MDCLSYNC = 1
MDCHSYNC = 0
MDCLSYNC = 0
MDCHSYNC = 0
MDCLSYNC = 1
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 0
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The modulated output frequency can be greater and asynchronous from the clock that updates this
register bit, the bit value may not be valid for higher speed modulator or carrier signals.
2: MDBIT must be selected as the modulation source in the MDSRC register for this operation.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
MDCARH MDCHODIS MDCHPOL MDCHSYNC — MDCH<3:0> 212
MDCARL MDCLODIS MDCLPOL MDCLSYNC — MDCL<3:0> 213
MDCON MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT 210
MDSRC MDMSODIS — — — MDMS<3:0> 211
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode.
TMR1H TMR1L
CCPxM<3:0>
System Clock (FOSC)
• PRx registers Table 24-9 shows the pin assignments for various
Enhanced PWM modes.
• TxCON registers
• CCPRxL registers Note 1: The corresponding TRIS bit must be
• CCPxCON registers cleared to enable the PWM output on the
CCPx pin.
The ECCP modules have the following additional PWM
registers which control Auto-shutdown, Auto-restart, 2: Clearing the CCPxCON register will
Dead-band Delay and PWM Steering modes: relinquish control of the CCPx pin.
FIGURE 24-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
DCxB<1:0> PxM<1:0> CCPxM<3:0>
Duty Cycle Registers
2 4
CCPRxL
CCPx/PxA CCPx/PxA
TRISx
CCPRxH (Slave)
PxB PxB
Output TRISx
Comparator R Q
Controller
PxC PxC
TMRx (1)
S TRISx
PxD PxD
Comparator
Clear Timer, TRISx
toggle PWM pin and
latch duty cycle
PRx PWMxCON
Note 1: The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time
base.
PxA Active
PxD Modulated
PxA Inactive
PxD Inactive
Relationships:
• Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
• Delay = 4 * TOSC * (PWMxCON<6:0>)
Pulse PRx+1
PxM<1:0> Signal 0
Width
Period
PxA Modulated
Delay Delay
10 (Half-Bridge) PxB Modulated
PxA Active
PxD Modulated
PxA Inactive
PxD Inactive
Relationships:
• Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
• Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
• Delay = 4 * TOSC * (PWMxCON<6:0>)
FET
Driver +
PxA
-
Load
FET
Driver
+
PxB
-
V+
FET FET
Driver Driver
PxA
Load
FET FET
Driver Driver
PxB
FET QA QC FET
Driver Driver
PxA
Load
PxB
FET FET
Driver Driver
PxC
QB QD
V-
PxD
PxB(2)
PxC(2)
PxD(2)
(1) (1)
Reverse Mode
Period
Pulse Width
PxA(2)
PxB(2)
PxC(2)
PxD(2)
(1) (1)
Note 1: At this time, the TMRx register is equal to the PRx register.
2: Output signal is shown as active-high.
PxA (Active-High)
PxB (Active-High)
Pulse Width
PxC (Active-High)
(2)
PxD (Active-High)
Pulse Width
Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.
2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The
modulated PxB and PxD signals are inactive at this time. The length of this time is four Timer counts.
PxA
PxB
PW
PxC
PxD PW
TON
External Switch C
TOFF
External Switch D
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Shutdown Shutdown Resumes
Event Occurs Event Clears CCPxASE
Cleared by
Firmware
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Shutdown Resumes
Event Occurs
Shutdown CCPxASE
Event Clears Cleared by
Hardware
FET
Driver +
PxA V
-
Load
FET
Driver
+
PxB V
-
V-
PORT Data
0
TRIS
STRxB
PORT Data 0
TRIS
STRxC
PxC pin
CCPxM1 1
PORT Data 0
TRIS
STRxD
PORT Data 0
TRIS
PWM Period
PWM
STRx
P1n = PWM
PWM
STRx
P1n = PWM
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
1000 = Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF)
1001 = Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF)
1010 = Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state
1011 = Compare mode: Special Event Trigger (ECCPx resets TMR1 or TMR3, sets CCPxIF bit, ECCP2 trigger
also starts A/D conversion if A/D module is enabled)(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11 and
PxM<1:0> = 00.
Data Bus
Read Write
SSP1BUF Reg
SDI
SSP1SR Reg
SDO bit 0 Shift
Clock
Edge
Select
SSP1M<3:0>
4
( TMR22Output )
SCK
Edge Prescaler TOSC
Select 4, 16, 64
Baud rate
generator
TRIS bit (SSP1ADD)
Internal
data bus [SSPM 3:0]
Read Write
Internal
Data Bus
Read Write
Shift
Clock
SSP1SR Reg
SDA MSb LSb
SSP1MSK Reg
SSP1ADD Reg
• Serial Clock (SCK) Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
• Serial Data Out (SDO)
three scenarios for data transmission:
• Serial Data In (SDI)
• Master sends useful data and slave sends dummy
• Slave Select (SS)
data.
Figure 25-1 shows the block diagram of the MSSP1 • Master sends useful data and slave sends useful
module when operating in SPI Mode. data.
The SPI bus operates with a single master device and • Master sends dummy data and slave sends useful
one or more slave devices. When multiple slave data.
devices are used, an independent Slave Select con-
Transmissions may involve any number of clock
nection is required from the master device to each
cycles. When there is no more data to be transmitted,
slave device.
the master stops sending the clock signal and it dese-
Figure 25-4 shows a typical connection between a lects the slave.
master device and multiple slave devices.
Every slave device connected to the bus that has not
The master selects only one slave at a time. Most slave been selected through its slave select line must disre-
devices have tri-state outputs so their output signal gard the clock and transmission signals and must not
appears disconnected from the bus when they are not transmit out any data of its own.
selected.
Transmissions involve two shift registers, eight bits in
size, one in the master and one in the slave. With either
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 25-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the pro-
grammed clock edge and latched on the opposite edge
of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave’s SDI input pin. The slave device transmits infor-
mation out on its SDO output pin, which is connected
to, and received by, the master’s SDI input pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polar-
ity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
During each SPI clock cycle, a full duplex data
transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on
its SDO pin) and the slave device is reading this bit and
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
General I/O
General I/O SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS
Slave Select
General I/O SS
Processor 1 (optional) Processor 2
Write to
SSP1BUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSP1IF
SSP1SR to
SSP1BUF
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSP1BUF
Shift register SSP1SR
and bit count are reset
SSP1BUF to
SSP1SR
SDI bit 0
bit 7 bit 7
Input
Sample
SSP1IF
Interrupt
Flag
SSP1SR to
SSP1BUF
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSP1BUF
Valid
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDI
bit 7 bit 0
Input
Sample
SSP1IF
Interrupt
Flag
SSP1SR to
SSP1BUF
Write Collision
detection active
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSP1BUF
Valid
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDI
bit 7 bit 0
Input
Sample
SSP1IF
Interrupt
Flag
SSP1SR to
SSP1BUF
Write Collision
detection active
SDA
SCL
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition
Sr
Change of Change of
When the SEN bit of the SSP1CON2 register is set, 1. S bit of SSP1STAT is set; SSP1IF is set if inter-
SCL will be held low (clock stretch) following each rupt on Start detect is enabled.
received byte. The clock must be released by setting 2. Matching address with R/W bit clear is clocked
the CKP bit of the SSP1CON1 register, except in. SSP1IF is set and CKP cleared after the 8th
sometimes in 10-bit mode. See Section 25.2.3 “SPI falling edge of SCL.
Master Mode” for more detail. 3. Slave clears the SSP1IF.
4. Slave can look at the ACKTIM bit of the
25.5.2.1 7-bit Addressing Reception
SSP1CON3 register to determine if the SSP1IF
This section describes a standard sequence of events was after or before the ACK.
for the MSSP1 module configured as an I2C Slave in 5. Slave reads the address value from SSP1BUF,
7-bit Addressing mode. All decisions made by hard- clearing the BF flag.
ware or software and their effect on reception. 6. Slave sets ACK value clocked out to the master
Figure 25-13 and Figure 25-14 is used as a visual by setting ACKDT.
reference for this description. 7. Slave releases the clock by setting CKP.
This is a step by step process of what typically must 8. SSP1IF is set after an ACK, not after a NACK.
be done to accomplish I2C communication. 9. If SEN = 1 the slave hardware will stretch the
1. Start bit detected. clock after the ACK.
2. S bit of SSP1STAT is set; SSP1IF is set if inter- 10. Slave clears SSP1IF.
rupt on Start detect is enabled. Note: SSP1IF is still set after the 9th falling edge
3. Matching address with R/W bit clear is received. of SCL even if there is no clock stretching
4. The slave pulls SDA low sending an ACK to the and BF has been cleared. Only if NACK is
master, and sets SSP1IF bit. sent to Master is SSP1IF not set
5. Software clears the SSP1IF bit. 11. SSP1IF set and CKP cleared after 8th falling
6. Software reads received address from edge of SCL for a received data byte.
SSP1BUF clearing the BF flag. 12. Slave looks at ACKTIM bit of SSP1CON3 to
7. If SEN = 1; Slave software sets CKP bit to determine the source of the interrupt.
release the SCL line. 13. Slave reads the received data from SSP1BUF
8. The master clocks out a data byte. clearing BF.
9. Slave drives SDA low sending an ACK to the 14. Steps 7-14 are the same for each received data
master, and sets SSP1IF bit. byte.
10. Software clears SSP1IF. 15. Communication is ended by either the slave
11. Software reads the received byte from sending an ACK = 1, or the master sending a
SSP1BUF clearing BF. Stop condition. If a Stop is sent and Interrupt on
12. Steps 8-12 are repeated for all received bytes Stop Detect is disabled, the slave will only know
from the Master. by polling the P bit of the SSTSTAT register.
13. Master sends Stop condition, setting P bit of
SSP1STAT, and the bus goes idle.
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSP1IF
SSP1IF set on 9th
Preliminary
Cleared by software Cleared by software falling edge of
SCL
BF
First byte
SSP1BUF is read of data is
available
in SSP1BUF
SSPOV
DS41419B-page 261
PIC16(L)F1824/1828
FIGURE 25-15:
DS41419B-page 262
Bus Master sends
Stop condition
SSP1IF
Preliminary
BF
First byte
of data is
SSP1BUF is read available
in SSP1BUF
SSPOV
SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
Slave software
clears ACKDT to Slave software
ACK the received sets ACKDT to
CKP byte not ACK
Preliminary
When AHEN=1:
When DHEN=1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCL is released
and SCL is stretched hardware on 8th falling
edge of SCL
ACKTIM
P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
DS41419B-page 263
PIC16(L)F1824/1828
Master sends
FIGURE 25-17:
Stop condition
Master releases
DS41419B-page 264
R/W = 0 SDA to slave for ACK sequence
Receiving Address Receive Data Receive Data ACK
SDA ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SSP1IF
Cleared by software No interrupt after
if not ACK
from Slave
PIC16(L)F1824/1828
BF
Received
address is loaded into Received data is SSP1BUF can be
SSP1BUF available on SSP1BUF read any time before
next byte is loaded
ACKDT
Preliminary
ACKDT to ACK not ACK
the received byte
CKP
When AHEN = 1; When DHEN = 1; CKP is not cleared
on the 8th falling edge on the 8th falling edge Set by software, if not ACK
of SCL of an address of SCL of a received release SCL
byte, CKP is cleared data byte, CKP is cleared
ACKTIM
P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
DS41419B-page 266
R/W = 1 Automatic
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSP1IF
Cleared by software
BF
BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSP1BUF loaded into SSP1BUF edge of SCL
PIC16(L)F1824/1828
CKP
When R/W is set CKP is not
SCL is always held for not
held low after 9th SCL Set by software ACK
falling edge
ACKSTAT
Preliminary
Masters not ACK
is copied to
ACKSTAT
R/W
R/W is copied from the
matching address byte
D/A
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
Indicates an address
has been received
DS41419B-page 268
Receiving Address R/W = 1 Automatic Transmitting Data Automatic Transmitting Data ACK
SDA ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P
SSP1IF
Cleared by software
BF BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSP1BUF loaded into SSP1BUF edge of SCL
PIC16(L)F1824/1828
ACKDT
Slave clears
ACKDT to ACK
address
Preliminary
ACKSTAT
Master’s ACK
response is copied
to SSP1STAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1; Set by software, after not ACK
after receiving matching CKP is always releases SCL
address. cleared after ACK
ACKTIM
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
R/W
D/A
DS41419B-page 270
Master sends
Stop condition
Receive First Address Byte Receive Second Address Byte Receive Data Receive Data
SDA
1 1 1 1
0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SCL is held low
while CKP = 0
PIC16(L)F1824/1828
SSP1IF
Set by hardware Cleared by software
on 9th falling edge
BF
Data is read
Preliminary
If address matches Receive address is
SSP1ADD it is loaded into read from SSP1BUF from SSP1BUF
SSP1BUF
UA
When UA = 1; Software updates SSP1ADD
SCL is held low and releases SCL
CKP
SCL S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2
BF
Preliminary
Slave software clears
ACKDT to ACK
the received byte
UA
DS41419B-page 271
PIC16(L)F1824/1828
FIGURE 25-22:
DS41419B-page 272
Master sends
Master sends Stop condition
Restart event Master sends
not ACK
Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
Sr
SSP1IF
PIC16(L)F1824/1828
BF
Preliminary
UA
High address is loaded
UA indicates SSP1ADD After SSP1ADD is back into SSP1ADD
must be updated updated, UA is cleared
CKP and SCL is released
Indicates an address
has been received
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX ‚ – 1
SCL
Master device
CKP asserts clock
Master device
releases clock
WR
SSP1CON1
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSP1IF
BF (SSP1STAT<0>)
Cleared by software
SSP1BUF is read
GCEN (SSP1CON2<7>)
’1’
Master mode is enabled by setting and clearing the The master device generates all of the serial clock
appropriate SSP1M bits in the SSP1CON1 register and pulses and the Start and Stop conditions. A transfer is
by setting the SSP1EN bit. In Master mode, the SCL ended with a Stop condition or with a Repeated Start
and SDA lines are set as inputs and are manipulated by condition. Since the Repeated Start condition is also
the MSSP1 hardware. the beginning of the next serial transfer, the I2C bus will
not be released.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con- In Master Transmitter mode, serial data is output
ditions. The Stop (P) and Start (S) bits are cleared from through SDA, while SCL outputs the serial clock. The
a Reset or when the MSSP1 module is disabled. Con- first byte transmitted contains the slave address of the
trol of the I 2C bus may be taken when the P bit is set, receiving device (7 bits) and the Read/Write (R/W) bit.
or the bus is Idle. In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
In Firmware Controlled Master mode, user code
ted, an Acknowledge bit is received. Start and Stop
conducts all I 2C bus operations based on Start and
conditions are output to indicate the beginning and the
Stop bit condition detection. Start and Stop condition
end of a serial transfer.
detection is the only active circuitry in this mode. All
other communication is done by the user software In Master Receive mode, the first byte transmitted con-
directly manipulating the SDA and SCL lines. tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
The following events will cause the SSP1 Interrupt Flag logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
bit, SSP1IF, to be set (SSP1 interrupt, if enabled): address followed by a ‘1’ to indicate the receive bit.
• Start condition detected Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
• Stop condition detected
each byte is received, an Acknowledge bit is transmit-
• Data transfer byte transmitted/received ted. Start and Stop conditions indicate the beginning
• Acknowledge transmitted/received and end of transmission.
• Repeated Start generated A Baud Rate Generator is used to set the clock fre-
Note 1: The MSSP1 module, when configured in quency output on SCL. See Section 25.7 “Baud Rate
I2C Master mode, does not allow queue- Generator” for more detail.
ing of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSP1BUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSP1BUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSP1BUF did not occur
2: When in Master mode, Start/Stop detec-
tion is masked and an interrupt is gener-
ated when the SEN/PEN bit is cleared and
the generation is complete.
SDA DX DX ‚ – 1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
TBRG
SCL
S
TBRG
DS41419B-page 280
Write SSP1CON2<0> SEN = 1 ACKSTAT in
Start condition begins SSP1CON2 = 1
From slave, clear ACKSTAT bit SSP1CON2<6>
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0 ACK
of 10-bit Address
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
responds to SSP1IF
SSP1IF
Cleared by software service routine
Cleared by software from SSP1 interrupt
Cleared by software
Preliminary
BF (SSP1STAT<0>)
PEN
R/W
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS41419B-page 282
ACK from Master
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSP1CON2<3> (RCEN = 1)
PEN bit = 1
Write to SSP1BUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave R/W = 1 Receiving Data from Slave Receiving Data from Slave
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSP1IF at end
of receive Set SSP1IF interrupt
Set SSP1IF interrupt at end of Acknow-
Set SSP1IF interrupt ledge sequence
at end of receive
PIC16(L)F1824/1828
at end of Acknowledge
SSP1IF sequence
Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSP1STAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSP1IF
responds to SSP1IF
BF
Preliminary
(SSP1STAT<0>) Last bit is shifted into SSP1SR and
contents are unloaded into SSP1BUF
SSPOV
ACKEN
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
RCEN
Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSP1CON2<3> (RCEN = 1) automatically SDA\ = ACKDT = 0 automatically
SCL 8 9
SSP1IF
Cleared in
SSP1IF set at software
the end of receive Cleared in
software SSP1IF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to set up Stop condition
SDA
BCL1IF
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 SSP1 module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCL1IF.
S bit and SSP1IF set because
BCL1IF SDA = 0, SCL = 1.
SSP1IF and BCL1IF are
cleared by software
SSP1IF
TBRG TBRG
SDA
FIGURE 25-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSP1IF
Less than TBRG
TBRG
SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCL1IF ‘0’
SSP1IF
SDA = 0, SCL = 1, Interrupts cleared
set SSP1IF by software
SDA
SCL
RSEN
BCL1IF
Cleared by software
S ‘0’
SSP1IF ‘0’
TBRG TBRG
SDA
SCL
S ‘0’
SSP1IF
PEN
BCL1IF
P ‘0’
SSP1IF ‘0’
SDA
PEN
BCL1IF
P ‘0’
SSP1IF ‘0’
SSP1M<3:0> SSP1ADD<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set
bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSP1SR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCK Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only)
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSP1BUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
REGISTER 25-6: SSP1ADD: MSSP1 ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ADD<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Master mode:
bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care.” Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care.”
10-Bit Slave mode — Least Significant Address byte:
TXEN
TRMT SPEN
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SPBRGH SPBRGL BRGH X 1 1 0 0
BRG16 X 1 0 1 0
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPBRGH SPBRGL BRGH FIFO
X 1 1 0 0 FERR RX9D RCREG Register
BRG16 X 1 0 1 0
8
Data Bus
RCIF Interrupt
RCIE
The EUSART transmitter block diagram is shown in The TXIF interrupt can be enabled by setting the TXIE
Figure 26-1. The heart of the transmitter is the serial interrupt enable bit of the PIE1 register. However, the
Transmit Shift Register (TSR), which is not directly TXIF flag bit will be set whenever the TXREG is empty,
accessible by software. The TSR obtains its data from regardless of the state of TXIE enable bit.
the transmit buffer, which is the TXREG register. To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
26.1.1.1 Enabling the Transmitter TXIE interrupt enable bit upon writing the last character
The EUSART transmitter is enabled for asynchronous of the transmission to the TXREG.
operations by configuring the following three control
bits:
• TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral, the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.
Note 1: The TXIF Transmitter Interrupt flag is set
when the TXEN enable bit is set.
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Word 1
TRMT bit
Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)
Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Transmit Buffer
Reg. Empty Flag) 1 TCY
• CREN = 1 Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
• SYNC = 0
to the EUSART receive FIFO and the RCIF interrupt
• SPEN = 1 flag bit of the PIR1 register is set. The top character in
All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the
their default state. RCREG register.
Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional
receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun
of the TXSTA register configures the EUSART for condition is cleared. See Section 26.1.2.5
asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more
RCSTA register enables the EUSART. The programmer information on overrun errors.
must set the corresponding TRIS bit to configure the
TX/CK I/O pin as an input. 26.1.2.3 Receive Interrupts
Note 1: If the RX/DT function is on an analog pin, The RCIF interrupt flag bit of the PIR1 register is set
the corresponding ANSEL bit must be whenever the EUSART receiver is enabled and there is
cleared for the receiver to function. an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE interrupt enable bit of the PIE1 register
• PEIE peripheral interrupt enable bit of the
INTCON register
• GIE global interrupt enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
TABLE 26-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 310
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 309
SPBRGL BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 311*
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 311*
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 308
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303
1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575
2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215
1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303
2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151
9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287
10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264
19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143
57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47
115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —
BRG Clock
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’ ‘1’
TXEN bit
Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RCREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Upon waking from Sleep, the instruction following the 26.5.3 ALTERNATE PIN LOCATIONS
SLEEP instruction will be executed. If the Global Inter-
This module incorporates I/O pins that can be moved to
rupt Enable (GIE) bit of the INTCON register is also set,
other locations with the use of the alternate pin function
then the Interrupt Service Routine at address 004h will
registers, APFCON0 and APFCON1. To determine
be called.
which pins can be moved and what their default
locations are upon a Reset, see Section 12.1
“Alternate Pin Function” for more information.
Timer0 Module
Set
TMR0CS TMR0IF
T0XCS
FOSC/4 0
Overflow
T0CKI 0 TMR0
1
CPSCH<3:0> 1
CPSON(2) CPSRNG<1:0>
CPSON
Capacitive
Sensing Timer1 Module
CPS0 Oscillator
T1CS<1:0>
CPS1 CPSOSC
CPS2 FOSC
FOSC/4
CPS3 CPSCLK
0 Int.
CPS4 Ref- Ref. T1OSC/ TMR1H:TMR1L
EN
CPSOUT T1CKI
CPS5 1 DAC
CPS6 0 T1GSEL<1:0>
Ref+
CPS7 T1G
1 FVR
CPS8(1) Timer1 Gate
SYNCC1OUT Control Logic
CPS9(1)
CPS10(1) SYNCC2OUT
CPS11(1)
CPSRM
Note 1: Reference CPSCON1 register (Register 27-2) for channels implemented on each device.
2: If CPSON = 0, disabling capacitive sensing, no channel is selected.
Oscillator Module
VDD
(1)
(2)
+
-
S Q CPSCLK
CPSx
Internal
References
0 0
Ref- Ref+
1 DAC 1 FVR
CPSRM
Note 1: Module Enable and Power mode selections are not shown.
2: Comparators remain active in Noise Detection mode.
When Timer0 is chosen as the timer resource, the The value of the timer resource is the number of
capacitive sensing oscillator will be the clock source for oscillations of the capacitive sensing oscillator for the
Timer0. Refer to Section 20.0 “Timer0 Module” for given time base. The frequency of the capacitive
additional information. sensing oscillator is equal to the number of counts on
in the timer divided by the period of the fixed time base.
27.6.2 TIMER1
27.7.2 REDUCED FREQUENCY
To select Timer1 as the timer resource for the (ADDITIONAL CAPACITIVE LOAD)
capacitive sensing module, set the TMR1CS<1:0> of
the T1CON register to ‘11’. When Timer1 is chosen as The extra capacitive load will cause the frequency of the
the timer resource, the capacitive sensing oscillator will capacitive sensing oscillator to decrease. To determine
be the clock source for Timer1. Because the Timer1 the reduced frequency of the capacitive sensing
module has a gate control, developing a time base for oscillator:
the frequency measurement can be simplified by using • Add a typical capacitive load on the selected
the Timer0 overflow flag. CPSx pin
It is recommend that the Timer0 overflow flag, in con- • Use the same fixed time base as the nominal
junction with the Toggle mode of the Timer1 Gate, be frequency measurement
used to develop the fixed time base required by the • At the start of the fixed time base, clear the timer
software portion of the capacitive sensing module. resource
Refer to Section 21.12 “Timer1 Gate Control Regis- • At the end of the fixed time base save the value in
ter” for additional information. the timer resource
The value of the timer resource is the number of oscil-
TABLE 27-2: TIMER1 ENABLE FUNCTION
lations of the capacitive sensing oscillator with an addi-
TMR1ON TMR1GE Timer1 Operation tional capacitive load. The frequency of the capacitive
0 0 Off sensing oscillator is equal to the number of counts on
in the timer divided by the period of the fixed time base.
0 1 Off This frequency should be less than the value obtained
1 0 On during the nominal frequency measurement.
1 1 Count Enabled by input
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
RJ11-6PIN
® R1
To MPLAB ICD 2 To Target Board
270 Ohm
LM431BCMX
2 A 1
K
3 A U1
6 A NC 4
7 A NC 5
VREF
8
R2 R3
10k 1% 24k 1%
Pin 1 Indicator
Pin Description*
1 1 = VPP/MCLR
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
External
Programming VDD Device to be
Signals Programmed
VDD VDD
VPP MCLR/VPP
VSS VSS
Data ICSPDAT
Clock ICSPCLK
* * *
To Normal Connections
OPCODE only
13 0
OPCODE
CONTROL OPERATIONS
BRA k Relative Branch 2 11 001k kkkk kkkk
BRW – Relative Branch with W 2 00 0000 0000 1011
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CALLW – Call Subroutine with W 2 00 0000 0000 1010
GOTO k Go to address 2 10 1kkk kkkk kkkk
RETFIE k Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 0100 kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
NOP – No Operation 1 00 0000 0000 0000
OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010
RESET – Software device Reset 1 00 0000 0000 0001
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register with W 1 00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk
MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3
modifier, mm kkkk
k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk 1nmm Z 2
MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 kkkk 2, 3
modifier, mm
k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk 2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
C register f 0 Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
LSRF Logical Right Shift
W = value in FSR register
Syntax: [ label ] LSLF f {,d} Z = 1
Operands: 0 f 127
d [0,1]
Operation: 0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
0 register f C
MOVWF Move W to f
Description: This instruction is used to move data
Syntax: [ label ] MOVWF f
between W and one of the indirect
registers (INDFn). Before/after this Operands: 0 f 127
move, the pointer (FSRn) is updated by Operation: (W) (f)
pre/post incrementing/decrementing it.
Status Affected: None
Note: The INDFn registers are not Description: Move data from W register to register
physical registers. Any instruction that ‘f’.
accesses an INDFn register actually Words: 1
accesses the register at the address
specified by the FSRn. Cycles: 1
Example: MOVWF OPTION
FSRn is limited to the range 0000h -
Before Instruction
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to wrap OPTION = 0xFF
around. W = 0x4F
After Instruction
OPTION = 0x4F
MOVLB Move literal to BSR W = 0x4F
Description: The W register is loaded with the eight Description: The contents of register ‘f’ are rotated
bit literal ‘k’. The program counter is one bit to the left through the Carry
loaded from the top of the stack (the flag. If ‘d’ is ‘0’, the result is placed in
return address). This is a two-cycle the W register. If ‘d’ is ‘1’, the result is
instruction. stored back in register ‘f’.
Words: 1 C Register f
Cycles: 2
Words: 1
Example: CALL TABLE;W contains table
;offset value Cycles: 1
• ;W now has table value Example: RLF REG1,0
TABLE •
Before Instruction
•
REG1 = 1110 0110
ADDWF PC ;W = offset
C = 0
RETLW k1 ;Begin table
After Instruction
RETLW k2 ;
REG1 = 1110 0110
•
W = 1100 1100
•
C = 1
•
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2.5
1.8
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies.
3.6
2.5
1.8
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies.
125
± 5%
85
± 3%
Temperature (°C)
60
25 ± 2%
0
-20 ± 5%
-40
1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
TVLOW(2) TPOR(3)
— 32 60 A 5.0
— 24 55 A 1.8 FOSC = 32 kHz
— 30 60 A 3.0 LP Oscillator mode, -40 TA +125°C
— 32 65 A 5.0
D011 — 60 110 A 1.8 FOSC = 1 MHz
— 111 A 3.0 XT Oscillator mode
190
D011 — 82 130 A 1.8 FOSC = 1 MHz
— 141 A 3.0 XT Oscillator mode
220
— 200 290 A 5.0
D012 — 145 290 A 1.8 FOSC = 4 MHz
— 260 A 3.0 XT Oscillator mode
480
D012 — 165 300 A 1.8 FOSC = 4 MHz
XT Oscillator mode
— 290 500 A 3.0
— 368 700 A 5.0
D013 — 34 160 A 1.8 FOSC = 1 MHz
EC Oscillator mode, Medium-power mode
— 59 230 A 3.0
D013 — 60 180 A 1.8 FOSC = 1 MHz
EC Oscillator mode
— 92 240 A 3.0
Medium-power mode
— 126 320 A 5.0
D014 — 118 250 A 1.8 FOSC = 4 MHz
EC Oscillator mode,
— 210 430 A 3.0
Medium-power mode
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: 8 MHz internal RC oscillator with 4x PLL enabled.
4: 8 MHz crystal oscillator with 4x PLL enabled.
5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k.
— 22 45 61 A 5.0
D023 — .2 1.5 3.0 A 1.8 LPWDT Current (Note 1)
— .5 2.0 3.5 A 3.0
D023 — 18 38 44 A 1.8 LPWDT Current (Note 1)
— 21 43 48 A 3.0
— 22 46 65 A 5.0
D023A — 4.8 22 25 A 1.8 FVR current (Note 1)
— 4.8 24 27 A 3.0
D023A — 26 62 65 A 1.8 FVR current (Note 1)
— 33 72 75 A 3.0
— 61 115 120 A 5.0
D024 — 7.0 14 16 A 3.0 BOR Current (Note 1)
D024 — 24 47 50 A 3.0 BOR Current (Note 1)
— 29 55 66 A 5.0
D025 — 1.0 3.5 4.0 A 1.8 T1OSC Current (Note 1)
— 1.2 4.0 4.5 A 3.0
D025 — 19 39 45 A 1.8 T1OSC Current (Note 1)
— 21 43 49 A 3.0
— 23 46 65 A 5.0
D026 — .03 1.5 3.0 A 1.8 A/D Current (Note 1, Note 3), no
— .04 2.0 3.5 A 3.0 conversion in progress
— 22 46 65 A 5.0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
— 280 — — A 5.0
D027 — 2.0 5.0 6.0 A 1.8 Cap Sense Low Power
— 4.0 6.0 8.0 A 3.0 Oscillator mode (Note 1)
— 24 53 68 A 5.0
D027A — 5.0 8.0 10 A 1.8 Cap Sense Medium Power
— 7.9 11 12 A 3.0 Oscillator mode (Note 1)
— 24 57 71 A 5.0
D027B — 13 22 24 A 1.8 Cap Sense High Power
— 35 42 44 A 3.0 Oscillator mode (Note 1)
— 24 95 110 A 5.0
D028 — 7.3 16 17 A 1.8 Comparator Current, Low Power
— 7.4 18 19 A 3.0 mode, one comparator enabled
(Note 1)
D028 — 28 45 50 A 1.8 Comparator Current, Low Power
— 30 56 61 A 3.0 mode, one comparator enabled
(Note 1)
— 32 60 80 A 5.0
D028A — 7.5 17 18 A 1.8 Comparator Current, Low Power
— 7.6 19 20 A 3.0 mode, two comparators enabled
(Note 1)
D028A — 29 47 52 A 1.8 Comparator Current, Low Power
— 31 58 63 A 3.0 mode, two comparators enabled
(Note 1)
— 33 62 82 A 5.0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
TH01 JA Thermal Resistance Junction to Ambient TBD C/W 8-pin PDIP package
TBD C/W 8-pin SOIC package
TBD C/W 8-pin DFN 3X3mm package
TBD C/W 14-pin PDIP package
TBD C/W 14-pin SOIC package
TBD C/W 14-pin TSSOP 4x4mm package
TBD C/W 16-pin QFN 4X4mm package
TH02 JC Thermal Resistance Junction to Case TBD C/W 8-pin PDIP package
TBD C/W 8-pin SOIC package
TBD C/W 8-pin DFN 3X3mm package
TBD C/W 14-pin PDIP package
TBD C/W 14-pin SOIC package
TBD C/W 14-pin TSSOP 4x4mm package
TBD C/W 16-pin QFN 4X4mm package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Legend: TBD = To Be Determined
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDIx sc SCKx
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
Pin CL
VSS
Q4 Q1 Q2 Q3 Q4 Q1
OSC1/CLKIN
OS02
OS04 OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz EC Oscillator mode (low)
DC — 4 MHz EC Oscillator mode (medium)
DC — 32 MHz EC Oscillator mode (high)
Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode
0.1 — 4 MHz XT Oscillator mode
1 — 4 MHz HS Oscillator mode, VDD 2.7V
1 — 20 MHz HS Oscillator mode, VDD > 2.7V
DC — 4 MHz RC Oscillator mode
OS02 TOSC External CLKIN Period(1) 27 — s LP Oscillator mode
250 — ns XT Oscillator mode
50 — ns HS Oscillator mode
31.25 — ns EC Oscillator mode
Oscillator Period(1) — 30.5 — s LP Oscillator mode
250 — 10,000 ns XT Oscillator mode
50 — 1,000 ns HS Oscillator mode
250 — — ns RC Oscillator mode
OS03 TCY Instruction Cycle Time(1) 200 — DC ns TCY = FOSC/4
OS04* TosH, External CLKIN High, 2 — — s LP oscillator
TosL External CLKIN Low 100 — — ns XT oscillator
20 — — ns HS oscillator
OS05* TosR, External CLKIN Rise, 0 — ns LP oscillator
TosF External CLKIN Fall 0 — ns XT oscillator
0 — ns HS oscillator
* These parameters are characterized but not tested.
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
MFINTOSC
Wake-up from Sleep Start-up Time — — 20 30 s
*These parameters are characterized but not tested.
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
3: By design.
FOSC
OS11 OS12
OS20
CLKOUT OS21
OS19 OS16 OS18
OS13 OS17
I/O pin
(Input)
OS15 OS14
I/O pin Old Value New Value
(Output)
OS18, OS19
FIGURE 30-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
VDD
VBOR and VHYST
VBOR
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word 1 is programmed to ‘0’.
2 ms delay if PWRTE = 0 and VREGEN = 1.
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
CC01 CC02
CC03
BSF ADCON0, GO
1 TCY
AD134 (TOSC/2(1))
AD131
Q4
AD130
A/D CLK
A/D Data 7 6 5 4 3 2 1 0
ADIF 1 TCY
GO DONE
Sampling Stopped
Sample AD132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
BSF ADCON0, GO
AD134 (TOSC/2 + TCY(1)) 1 TCY
AD131
Q4
AD130
A/D CLK
A/D Data 7 6 5 4 3 2 1 0
ADIF 1 TCY
GO DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage(3) — ±7.5 ±60 mV
CM02 VICM Input Common Mode Voltage 0 — VDD V
CM03 CMRR Common Mode Rejection Ratio — 50 — dB
CM04A Response Time Rising Edge — 400 800 ns High Power Mode, Note 1
CM04B Response Time Falling Edge — 200 400 ns High Power Mode, Note 1
TRESP
CM04C Response Time Rising Edge — 1200 — ns Low Power Mode, Note 1
CM04D Response Time Falling Edge — 550 — ns Low Power Mode, Note 1
CM05 TMC2OV Comparator Mode Change to — — 10 s
Output Valid*
CM06 CHYSTER Comparator Hysteresis — 45 — mV Note 2
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions
from VSS to VDD.
2: Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.
3: High Power mode.
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
DAC01* CLSB Step Size — VDD/32 — V
DAC02* CACC Absolute Accuracy — — 1/2 LSb
DAC03* CR Unit Resistor Value (R) — 5K —
DAC04* CST Settling Time(1) — — 10 s
* These parameters are characterized but not tested.
Legend: TBD = To Be Determined
Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.
CK
US121 US121
DT
US120 US122
Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US120 TCKH2DTV SYNC XMIT (Master and Slave) 3.0-5.5V — 80 ns
Clock high to data-out valid 1.8-5.5V — 100 ns
US121 TCKRF Clock out rise time and fall time 3.0-5.5V — 45 ns
(Master mode) 1.8-5.5V — 50 ns
US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns
1.8-5.5V — 50 ns
CK
US125
DT
US126
SSx
SP70
SCKx
(CKP = 0)
SP71 SP72
SP78 SP79
SCKx
(CKP = 1)
SP79 SP78
SP80
SP75, SP76
SP74
SP73
SSx
SP81
SCKx
(CKP = 0)
SP71 SP72
SP79
SP73
SCKx
(CKP = 1)
SP80
SP78
SP75, SP76
SP74
SSx
SP70
SCKx SP83
(CKP = 0)
SP71 SP72
SP78 SP79
SCKx
(CKP = 1)
SP79 SP78
SP80
SP74
SP73
SP82
SSx
SP70
SCKx SP83
(CKP = 0)
SP71 SP72
SCKx
(CKP = 1)
SP80
SP77
SP75, SP76
SDIx
MSb In bit 6 - - - -1 LSb In
SP74
SCLx
SP91 SP93
SP90 SP92
SDAx
Start Stop
Condition Condition
SCLx
SP90
SP106
SP107
SP91 SP92
SDAx
In
SP110
SP109
SP109
SDAx
Out
VCTH
VCTL
ISRC ISNK
Enabled Enabled
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Note 1: This device has been designed to perform to the parameters of its data sheet. It has been tested to an
electrical specification designed to determine its conformance with these parameters. Due to process dif-
ferences in the manufacture of this device, this device may have different performance characteristics than
its earlier version. These differences may cause this device to perform differently in your application than
the earlier version of this device.
Note 1: The user should verify that the device oscillator starts and performs as expected. Adjusting the loading
capacitor values and/or the oscillator mode may be required.
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 378
Requirements, Synchronous Transmission ...... 378
Timing Diagram, Synchronous Receive ........... 378
Timing Diagram, Synchronous Transmission ... 377
V
VREF. SEE ADC Reference Voltage
W
Wake-up on Break ............................................................ 317
Wake-up Using Interrupts ................................................. 101
Watchdog Timer (WDT) ...................................................... 82
Modes ....................................................................... 104
Specifications............................................................ 373
WCOL ....................................................... 276, 279, 281, 283
WCOL Status Flag .................................... 276, 279, 281, 283
WDTCON Register ........................................................... 105
WPUA Register ................................................................. 128
WPUB Register ................................................................. 133
WPUC Register................................................................. 138
Write Protection .................................................................. 55
WWW Address.................................................................. 417
WWW, On-Line Support ..................................................... 12
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08/04/10