Computer Architecture HW #1

Due: Friday, Jan. 27 (3 PM in ITT 305 mailbox or under my office door, ITT 313)
1. Compare zero-, one-, two-, three-address, and the load-store machines by writing programs to compute
X = C* B - B * C * D;
Y = (X + A * D) / (B - X );
for each of the five machines (3-address, 2-address, 1-address, 0-address, and load-store). The instructions
available for use are as follows. Each program should contain code for both of the above assignment statement and
should not wipe out the values in A, B, C, or D.

3 Address 2 Address 1 Address 0 Address Load-Store Machine

(Accumulator (Stack machine)
machine)
MOVE (X b Y) MOVE (X b Y) LOAD M PUSH M LOAD R#, M
STORE M POP M STORE R#, M
ADD (X b Y + Z) ADD (X b X + Y) ADD M ADD ADD R#d,R#sL,R#sR
SUB (X b Y - Z) SUB (X b X - Y) SUB M SUB SUB R#d,R#sL,R#sR
MUL (X b Y * Z) MUL (X b X * Y) MUL M MUL MUL R#d,R#sL,R#sR
DIV (X b Y / Z) DIV (X b X / Y) DIV M DIV DIV R#d,R#sL,R#sR
Notes: Notes: Notes:
“SUB M” performs “SUB” performs “SUB R4, R2, R3”
AC = AC - M POP T performs
POP T2 R4 = R2 - R3
“DIV M” performs T3 = T2 - T
AC = AC / M PUSH T3

“DIV” performs
POP T
POP T2
T3 = T2 / T
PUSH T3

2. Assume 8-bit opcodes, 32-bit absolute addressing, 5-bit register numbers (used only for Load-Store Machine),
and 32-bit (data) operands. Compute the number of bits needed during program execution for each programs from
question 2. Complete the following table.
3 Address 2 Address 1 Address 0 Address Load & Store
Number of program
bits read during 832 864 640 544 454
program execution
Number of bits of
data transferred to 768 1,024 512 384 192
and from memory
Total number of bits
read and written
1,600 1,888 1,152 928 646
during program
execution
3. You are to assume the same 5-stage pipeline discussed in class when answering these questions.
Assume that the first register in an arithmetic operation is the destination register, e.g., in “ADD R3, R2, R1”
register R3 receives the result of adding registers R2 and R1.

a. What would the timing be without bypass-signal paths/forwarding (use “stalls” to solve the data hazard)?
(This code might require more or less that 15 cycles)

Time d
Instructions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
ADD R3, R2, R1 F D E M W
STORE R3, 8(R4) F - - - D E M W
LOAD R4, 16(R3) F D E M W
SUB R3, R4, R1 F - - - D E M W
MUL R6, R3, R4 F - - - D E M W
STORE R6, 4(R5) F - - - D E M W
(Assume that a register cannot be written and the new value read in the same stage.)

b. What would the timing be with bypass-signal paths?

(This code might require more that 15 cycles)

Time d
Instructions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
ADD R3, R2, R1 F D E M W
STORE R3, 8(R4) F D E M W
LOAD R4, 16(R3) F D E M W
SUB R3, R4, R1 F D - E M W
MUL R6, R3, R4 F - D E M W
STORE R6, 4(R5) F D E M W
(Assume that a register cannot be written and the new value read in the same stage.)

c. Draw ALL the bypass-signal paths needed for the above example.

Fetch Decode Execute Memory Write

F/D D/E E/M M/W
latch latch latch latch

Decoder
Instr.
Memory M Data Register
Register M
U Memory File
File U
ALU

X
X
M Result Result
U Value Value
X
High-level language program:
X = C* B - B * C * D;
Y = (X + A * D) / (B - X );

3-Address Machine: // COULD AVOID RE-MULTIPLYING B*C

MUL X, C, B
MUL T, B, C
MUL T, T, D
SUB X, X, T
MUL T, A, D
ADD Y, X, T
SUB T, B, X
DIV Y, Y, T

AL Program ML Instruction Size Data Transferred During

Execution
MUL X, C, B 8+32+32+32 = 104 bits 32+32+32 = 96 bits
MUL T, B, C 104 bits 96 bits
MUL T, T, D 104 bits 96 bits
SUB X, X, T 104 bits 96 bits
MUL T, A, D 104 bits 96 bits
ADD Y, X, T 104 bits 96 bits
SUB T, B, X 104 bits 96 bits
DIV Y, Y, T 104 bits 96 bits
Subtotal # Bits 8 x 104 = 832 bits 8 x 96 = 768 bits
Overall Total # Bits 832 + 768 = 1600 bits
High-level language program:
X = C* B - B * C * D;
Y = (X + A * D) / (B - X );

2-Address Machine:

MOVE X, C
MUL X, B
MOVE T, B
MUL T, C
MUL T, D
SUB X, T
MOVE Y, A
MUL Y, D
ADD Y, X
MOVE T, B
SUB T, X
DIV Y, T

AL Program ML Instruction Size Data Transferred During

Execution
MOVE X, C 8+32+32 = 72 bits 32+32 = 64 bits
MUL X, B 72 bits 32+32+32 = 96 bits
MOVE T, B 72 bits 64 bits
MUL T, C 72 bits 96 bits
MUL T, D 72 bits 96 bits
SUB X, T 72 bits 96 bits
MOVE Y, A 72 bits 64 bits
MUL Y, D 72 bits 96 bits
ADD Y, X 72 bits 96 bits
MOVE T, B 72 bits 64 bits
SUB T, X 72 bits 96 bits
DIV Y, T 72 bits 96 bits
Subtotal # Bits 12 x 72 = 864 bits 4 x 64 + 8 x 96 = 1024 bits
Overall Total # Bits 864 + 1024 = 1888 bits
High-level language program:
X = C* B - B * C * D;
Y = (X + A * D) / (B - X );

1-Address Machine:

LOAD B
MUL C
MUL D
STORE X
LOAD C
MUL B
SUB X
STORE X
LOAD B
SUB X
STORE Y
LOAD A
MUL D
ADD X
DIV Y
STORE Y

AL Program ML Instruction Size Data Transferred During

Execution
LOAD B 8+32 = 40 bits 32 bits
MUL C 40 bits 32 bits
MUL D 40 bits 32 bits
STORE X 40 bits 32 bits
LOAD C 40 bits 32 bits
MUL B 40 bits 32 bits
SUB X 40 bits 32 bits
STORE X 40 bits 32 bits
LOAD B 40 bits 32 bits
SUB X 40 bits 32 bits
STORE Y 40 bits 32 bits
LOAD A 40 bits 32 bits
MUL D 40 bits 32 bits
ADD X 40 bits 32 bits
DIV Y 40 bits 32 bits
STORE Y 40 bits 32 bits
Subtotal # Bits 16 x 40 = 640 bits 16 x 32 = 512 bits
Overall Total # Bits 640 + 512 = 1152 bits
High-level language program:
X = C* B - B * C * D;
Y = (X + A * D) / (B - X );

- /

* * + -

C B * D X * B X

B C A D

Postorder: C B * B C * D * - Postorder: X A D * + B X - /

0-Address Machine:

AL Program ML Instruction Size Data Transferred During

Execution
PUSH C 8+32 = 40 bits 32 bits
PUSH B 40 bits 32 bits
MUL 8 bits 0 bits
PUSH B 40 bits 32 bits
PUSH C 40 bits 32 bits
MUL 8 bits 0 bits
PUSH D 40 bits 32 bits
MUL 8 bits 0 bits
SUB 8 bits 0 bits
POP X 40 bits 32 bits
PUSH X 40 bits 32 bits
PUSH A 40 bits 32 bits
PUSH D 40 bits 32 bits
MUL 8 bits 0 bits
ADD 8 bits 0 bits
PUSH B 40 bits 32 bits
PUSH X 40 bits 32 bits
SUB 8 bits 0 bits
DIV 8 bits 0 bits
POP Y 40 bits 32 bits
Subtotal # Bits 12 x 40 + 8 x 8 = 544 bits 12 x 32 = 384 bits
Overall Total # Bits 544 + 384 = 928 bits
High-level language program:
X = C* B - B * C * D;
Y = (X + A * D) / (B - X );
LOAD-STORE Machine:

LOAD R1, C
LOAD R2, B
MUL R6, R1, R2
LOAD R3, D
MUL R5, R2, R1
MUL R5, R5, R3
SUB R6, R6, R5
STORE R6, X
LOAD R4, A
MUL R5, R4, R3
ADD R5, R6, R5
SUB R2, R2, R6
DIV R1, R5, R2
STORE R1, Y

AL Program ML Instruction Size Data Transferred During

Execution
LOAD R1, C 8+5+32 = 45 bits 32 bits
LOAD R2, B 45 bits 32 bits
MUL R6, R1, R2 8+5+5+5 = 23 bits 0 bits
LOAD R3, D 45 bits 32 bits
MUL R5, R2, R1 23 bits 0 bits
MUL R5, R5, R3 23 bits 0 bits
SUB R6, R6, R5 23 bits 0 bits
STORE R6, X 45 bits 32 bits
LOAD R4, A 45 bits 32 bits
MUL R5, R4, R3 23 bits 0 bits
ADD R5, R6, R5 23 bits 0 bits
SUB R2, R2, R6 23 bits 0 bits
DIV R1, R5, R2 23 bits 0 bits
STORE R1, Y 45 bits 32 bits
Subtotal # Bits 6 x 45 + 8 x 23 = 454 bits 6 x 32 = 192 bits
Overall Total # Bits 454 + 192 = 646 bits