Midterm Solutions

1. Compare 0,1,2 and 3 address machines by writing a program to compute:

X=(A+BxC)/(D-ExF-GxH)

0-address 1-address 2-assress 3-address

PUSH A LOAD H MOV R1,B MUL R1,B,C
PUSH B MUL G MUL R1,C ADD R1,R1,A
PUSH C STORE X ADD R1,A MUL R2,G,H
MUL LOAD F MOV R2,G MUL R3,E,F
ADD MUL E MUL R2,H SUB R3,D,R3
PUSH D SUB X MOV R3,E SUB R3,R3,R2
PUSH E STORE X MUL R3,F DIV R1,R1,R3
PUSH F LOAD D MOV R4,D
MUL SUB X SUB R4,R3
SUB STORE X SUB R4,R2
PUSH G LOAD C DIV R1,R4
PUSH H MUL B
MUL MUL A
SUB DIV X
DIV STORE X
POP X

2. Given is a Branch instruction BR

0 7
BR Offset

The address of the target instruction is specified in the instruction (in the IAR-relative
mode) Providing 24-bit displacement from the IAR.
(a) List cycle by cycle all the steps of this instruction.

1. Instruction fetch step

Fetch the instruction from memory by sending the PC to memory as the
address, performing a read and writing the instruction into the Instruction
register (IR). Also it computes the address of the next sequential instruction
by incrementing PC by four

2. Instruction decode and register fetch step

The value of two registers (rs and rt) are read from register file and the values
are stored into the temporary registers A and B. They are used in R format
instructions. The type of the instruction is recognized to continue the next
step.

3. Execution
 The offset is shifted left two bits and the 26 bit result is concatenated with the
upper 6 bits of PC to form the target address.

(b) Fill in all the necessary paths(busses)in the CPU diagram provided.

In
IAR MAR MDR

W
IR

Write Address
RA Address
RB Address
RA RB

Control
Unit
ALU

CC
3. Fill in the missing entries of the following table.

Binary Octal Decimal Hexadecimal

110101 65 53 35
11100110 346 230 E6
101100100 01344 740 2E4
110110110 666 438 1B6
1100011 143 99 63
1001001 111 73 49
10100011 243 163 A3
111111010010 7722 4050 FD2

4. Given is the Store instruction

ST R5 R7 F6

The register file has 8 (32-bit)registers containing the following values:

R5=FFA1
R7=FF00
The memory is Byte addressable
(a) What are the address locations in memory that will be affected by this instruction?

The 16-bit offset(I) is sign-extended and added to the contents of R5 to form a 32-bit
unsigned effective address. The contents of R7 are stored at this effective address.
FFA1+FFF6=1FF97
Affected memory locations: 1FF97, 1FF98, 1FF99, 1FF9A

(b) List the values in those locations after the STORE instruction is executed?

Address Content
1FF97 00000000
1FF98 00000000
1FF99 11111111
1FF9A 00000000