FQP13N50C / FQPF13N50C — N-Channel QFET® MOSFET

November 2013

FQP13N50C / FQPF13N50C
N-Channel QFET® MOSFET
500 V, 13 A, 480 mΩ

Description Features
These N-Channel enhancement mode power field effect • 13 A, 500 V, RDS(on) = 480 mΩ (Max.) @ VGS = 10 V,
transistors are produced using Fairchild’s proprietary, ID = 6.5 A
planar stripe, DMOS technology. This advanced • Low Gate Charge (Typ. 43 nC)
technology has been especially tailored to minimize on- • Low Crss (Typ. 20 pF)
state resistance, provide superior switching performance,
• 100% Avalanche Tested
and withstand high energy pulse in the avalanche and
commutation mode. These devices are well suited for high
efficiency switched mode power supplies, active power
factor correction, electronic lamp ballasts based on half
bridge topology.

G G
D G
S TO-220 D
S TO-220F

Absolute Maximum Ratings T C

o
= 25 C unless otherwise noted.

Symbol Parameter FQP13N50C FQPF13N50C Units

VDSS Drain-Source Voltage 500 V
ID Drain Current - Continuous (TC = 25°C) 13 13 * A
- Continuous (TC = 100°C) 8 8* A
IDM Drain Current - Pulsed (Note 1) 52 52 * A
VGSS Gate-Source Voltage ± 30 V
EAS Single Pulsed Avalanche Energy (Note 2) 860 mJ
IAR Avalanche Current (Note 1) 13 A
EAR Repetitive Avalanche Energy (Note 1) 19.5 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V/ns
PD Power Dissipation (TC = 25°C) 195 48 W
- Derate above 25°C 1.56 0.39 W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C
Maximum lead temperature for soldering purposes,
TL 300 °C
1/8" from case for 5 seconds
* Drain current limited by maximum junction temperature

Thermal Characteristics
Symbol Parameter FQP13N50C FQPF13N50C Units
RθJC Thermal Resistance, Junction-to-Case, Max. 0.64 2.58 °C/W
RθJS Thermal Resistance, Case-to-Sink, Typ. 0.5 -- °C/W
RθJA Thermal Resistance, Junction-to-Ambient, Max. 62.5 62.5 °C/W

©2003 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com

FQP13N50C / FQPF13N50C Rev. C0
 FQP13N50C / FQPF13N50C — N-Channel QFET® MOSFET
Package Marking and Ordering Information
Part Number Top Mark Package Packing Method Reel Size Tape Width Quantity
FQP13N50C_F105 FQP13N50C TO-220 Tube N/A N/A 50 units
FQPF13N50C_F105 FQPF13N50C TO-220F Tube N/A N/A 50 units

Electrical Characteristics T C
o
= 25 C unless otherwise noted.

Symbol Parameter Test Conditions Min Typ Max Unit

Off Characteristics
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 500 -- -- V
∆BVDSS Breakdown Voltage Temperature
ID = 250 µA, Referenced to 25°C -- 0.5 -- V/°C
/ ∆TJ Coefficient
IDSS VDS = 500 V, VGS = 0 V -- -- 1 µA
Zero Gate Voltage Drain Current
VDS = 400 V, TC = 125°C -- -- 10 µA
IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA
IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA

On Characteristics
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 2.0 -- 4.0 V
RDS(on) Static Drain-Source
VGS = 10 V, ID = 6.5 A -- 0.39 0.48 Ω
On-Resistance
gFS Forward Transconductance VDS = 40 V, ID = 6.5 A -- 15 -- S

Dynamic Characteristics
Ciss Input Capacitance VDS = 25 V, VGS = 0 V, -- 1580 2055 pF
Coss Output Capacitance f = 1.0 MHz -- 180 235 pF
Crss Reverse Transfer Capacitance -- 20 25 pF

Switching Characteristics
td(on) Turn-On Delay Time -- 25 60 ns
VDD = 250 V, ID = 13 A,
tr Turn-On Rise Time -- 100 210 ns
RG = 25 Ω
td(off) Turn-Off Delay Time -- 130 270 ns
(Note 4)
tf Turn-Off Fall Time -- 100 210 ns
Qg Total Gate Charge VDS = 400 V, ID = 13 A, -- 43 56 nC
Qgs Gate-Source Charge VGS = 10 V -- 7.5 -- nC
Qgd Gate-Drain Charge (Note 4) -- 18.5 -- nC

Drain-Source Diode Characteristics and Maximum Ratings

IS Maximum Continuous Drain-Source Diode Forward Current -- -- 13 A
ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 52 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 13 A -- -- 1.4 V
trr Reverse Recovery Time VGS = 0 V, IS = 13 A, -- 410 -- ns
Qrr Reverse Recovery Charge dIF / dt = 100 A/µs -- 4.5 -- µC


1. Repetitive rating : pulse-width limited by maximum junction temperature.
2. L = 6 mH, IAS = 13 A, VDD = 50 V, RG = 25 Ω, starting TJ = 25oC.
3. ISD ≤ 13 A, di/dt ≤ 200 A/μs, VDD ≤ BVDSS, starting TJ = 25oC.
4. Essentially independent of operating temperature.

©2003 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com

FQP13N50C / FQPF13N50C Rev. C0
 FQP13N50C / FQPF13N50C — N-Channel QFET® MOSFET
 !   

VGS
Top : 15.0 V
10.0 V
8.0 V
7.0 V
1 6.0 V 1
10 5.5 V 10
o
5.0 V 150 C
Bottom : .5 V

ID, Drain Current [A]

ID, Drain Current [A]

o
-55 C
o
25 C
0 0
10 10

※ Notes :
1. 250μ s Pulse Test ※ Notes :
2. TC = 25℃ 1. VDS = 40V
2. 250μ s Pulse Test
-1 -1
10 10
-1 0 1 2 4 6 8 10
10 10 10
VDS, Drain-Source Voltage [V] VGS, Gate-Source Voltage [V]

Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics

1.5
1
10
Drain-Source On-Resistance

VGS = 10V
IDR, Reverse Drain Current [A]
RDS(ON) [Ω ],

1.0

0
10

VGS = 20V
150℃
※ Notes :
0.5
25℃ 1. VGS = 0V
※ Note : TJ = 25℃ 2. 250μ s Pulse Test

-1
10
0 5 10 15 20 25 30 35 0.2 0.4 0.6 0.8 1.0 1.2 1.4
ID, Drain Current [A] VSD, Source-Drain voltage [V]

Figure 3. On-Resistance Variation vs Figure 4. Body Diode Forward Voltage

Drain Current and Gate Voltage Variation with Source Current
and Temperature

12
3000
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd VDS = 100V
Crss = Cgd 10
2500 VDS = 250V
VGS, Gate-Source Voltage [V]

Ciss VDS = 400V

8
2000
Capacitance [pF]

Coss 6
1500

※ Notes ; 4
1000
1. VGS = 0 V
2. f = 1 MHz
Crss
2
500
※ Note : ID = 13A

0
0 0 10 20 30 40 50
-1 0 1
10 10 10
QG, Total Gate Charge [nC]
VDS, Drain-Source Voltage [V]

Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics

©2003 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com

FQP13N50C / FQPF13N50C Rev. C0
 FQP13N50C / FQPF13N50C — N-Channel QFET® MOSFET
 !    (continued)

1.2 3.0

2.5
Drain-Source Breakdown Voltage

1.1

Drain-Source On-Resistance
BV DSS , (Normalized)

RDS(ON) , (Normalized)
2.0

1.0 1.5

1.0

0.9 ※ Notes :
1. VGS = 0 V ※ Notes :
2. ID = 250 μ A 0.5 1. VGS = 10 V
2. ID = 6.5 A

0.8 0.0
-100 -50 0 50 100 150 200 -100 -50 0 50 100 150 200
o
o TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]

Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation

vs Temperature vs Temperature

2
Operation in This Area
Operation in This Area 10 is Limited by R DS(on)
2
is Limited by R DS(on)
10 10 µs
10 µs
100 µs
100 µs 10
1
1 ms
ID, Drain Current [A]

ID, Drain Current [A]

1 ms 10 ms
1
10 10 ms 100 ms
100 ms DC
0
DC 10

0
10 ※ Notes :
※ Notes : -1
o
10 o
1. TC = 25 C
1. TC = 25 C o
2. TJ = 150 C
o 2. TJ = 150 C
3. Single Pulse
3. Single Pulse

-1 -2
10 10
0 1 2 3 0 1 2 3
10 10 10 10 10 10 10 10
VDS, Drain-Source Voltage [V] VDS, Drain-Source Voltage [V]

Figure 9-1. Maximum Safe Operating Area Figure 9-2. Maximum Safe Operating Area
for FQP13N50C for FQPF13N50C

14

12

10
ID, Drain Current [A]

0
25 50 75 100 125 150
TC, Case Temperature [℃]

Figure 10. Maximum Drain Current

vs Case Temperature

©2003 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com

FQP13N50C / FQPF13N50C Rev. C0
 FQP13N50C / FQPF13N50C — N-Channel QFET® MOSFET
 !    (continued)

0
10

ZθJC(t), Thermal Response [oC/W]

D = 0 .5

0 .2
-1 ※ N o te s :
10 1 . Z θ J C ( t) = 0 .6 4 ℃ /W M a x .
0 .1 2 . D u t y F a c to r , D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C ( t)
0 .0 5

0 .0 2
0 .0 1 PDM
-2
10 s in g le p u ls e t1
t2

-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10
t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]

Figure 11-1. Transient Thermal Response Curve for FQP13N50C

ZθJC(t), Thermal Response [oC/W]

D = 0 .5
0
10

0 .2
※ N o te s :
1 . Z θ J C (t) = 2 .5 8 ℃ /W M a x .
0 .1 2 . D u ty F a c to r, D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C (t)
0 .0 5
-1
10
0 .0 2
0 .0 1 PDM
t1
-2
s in g le p u ls e t2
10

-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10
t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]

Figure 11-2. Transient Thermal Response Curve for FQPF13N50C

©2003 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com

FQP13N50C / FQPF13N50C Rev. C0
 FQP13N50C / FQPF13N50C — N-Channel QFET® MOSFET
VGS
Same Type
50KΩ
as DUT Qg
12V 200nF
300nF 10V
VDS
VGS Qgs Qgd

DUT
IG = const.
3mA

Charge

Figure 12. Gate Charge Test Circuit & Waveform

RL VDS
VDS 90%

VGS VDD
RG

10%
VGS
V
10V
GS
DUT
td(on) tr td(off)
tf
t on t off

Figure 13. Resistive Switching Test Circuit & Waveforms

L 1 BVDSS
VDS EAS = ---- L IAS2 --------------------
2 BVDSS - VDD
BVDSS
ID
IAS
RG
VDD ID (t)

V
10V
GS
GS DUT VDD VDS (t)
tp
tp Time

Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms

©2003 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com

FQP13N50C / FQPF13N50C Rev. C0
 FQP13N50C / FQPF13N50C — N-Channel QFET® MOSFET
DUT +

VDS

I SD
L

Driver
RG
Same Type
as DUT VDD

VGS • dv/dt controlled by RG

• ISD controlled by pulse period

Gate Pulse Width

VGS D = --------------------------
Gate Pulse Period 10V
( Driver )

IFM , Body Diode Forward Current

I SD
( DUT ) di/dt

IRM

Body Diode Reverse Current

VDS
( DUT ) Body Diode Recovery dv/dt

VSD VDD

Body Diode
Forward Voltage Drop

Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms

©2003 Fairchild Semiconductor Corporation 7 www.fairchildsemi.com

FQP13N50C / FQPF13N50C Rev. C0
 FQP13N50C / FQPF13N50C — N-Channel QFET® MOSFET
Mechanical Dimensions

Figure 16. TO220, Molded, 3-Lead, Jedec Variation AB

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif-
ically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TO220-003

©2003 Fairchild Semiconductor Corporation 8 www.fairchildsemi.com

FQP13N50C / FQPF13N50C Rev. C0
 FQP13N50C / FQPF13N50C — N-Channel QFET® MOSFET
Mechanical Dimensions

Figure 17. TO220, Molded, 3-Lead, Full Pack, EIAJ SC91, Straight Lead
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif-
ically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TF220-003

©2003 Fairchild Semiconductor Corporation 9 www.fairchildsemi.com

FQP13N50C / FQPF13N50C Rev. C0
 FQP13N50C / FQPF13N50C — N-Channel QFET® MOSFET
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Definition of Terms
Datasheet Identification
Advance Information
Product Status Definition
Datasheet contains the design specifications for product development. Specifications
Formative / In Design
may change in any manner without notice.

Datasheet contains preliminary data; supplementary data will be published at a later

Preliminary First Production date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.

Datasheet contains final specifications. Fairchild Semiconductor reserves the right to

No Identification Needed Full Production
make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fairchild

Obsolete Not In Production
Semiconductor. The datasheet is for reference information only.
Rev. I66

©2003 Fairchild Semiconductor Corporation 10 www.fairchildsemi.com

FQP13N50C / FQPF13N50C Rev. C0