Instruction Byte 1 Byte 2 Control lines

Mnemonic Description Opcode Operands Halt Update flags ALU Writeback A byte 1 A byte 2 B Immediate
NOP No-op No No No No No No No No
HLT Halt Yes [1] No No No No No No No
STS Settings Setting [2] Immediate No No No No No No No No
Conditional load Immediate Destination Condition Sign ext. immediate
CLI [3] [4] [5] [6] No No Yes Yes No No No Yes [7]
JMP Jump Location Yes [8] No No No No No No No
CAL Call Location Yes [9] No No No No No No No
RET Return Yes [10] No No No No No No No
T
Condition [12
BRH Branch [11] ] Location in page No No No No No No No No
E
[13
POI Pointer ] Source B No Yes Yes No Yes No Yes No
Register
SLD Special register load Destination [14] No Yes Yes Yes No No No No
PST Port store Source Port address No Yes Yes No Yes No No No
PLD Port load Destination Port address Yes [15] Yes Yes Yes No No No No
U W
[17 [18 Sometimes
PSH Push stack [16] Source ] ] Sign extend offset [19] Yes Yes No Yes No No No
U W
[21 [22 Sometimes
POP Pop stack [20] Destination ] ] Sign extend offset [23] Yes Yes Yes No No No No
Sometimes
MST Memory store Source Address [24] [25] Yes Yes No Yes No No No
Sometimes
MLD Memory load Destination Address [26] [27] Yes Yes Yes No No No No
Destination
LIM Load immediate [28] Immediate No No Yes Yes No No No Yes [29]
AIM AND immediate [30] Source/dest Immediate No Yes Yes Yes Yes No No Yes [31]
CMP Compare [32] Source Immediate No Yes Yes No Yes No No Yes [33]
CMA Compare AND [34] Source Immediate No Yes Yes No Yes No No Yes [35]
MOV Move [36] Destination Source A No No Yes Yes No Yes Yes No
Type
ADD Add Destination Source A [37] Source B No Yes Yes Yes No Yes Yes No
Type
SUB Subtract Destination Source A [38] Source B No Yes Yes Yes No Yes Yes No
Sign ext. immediate
ADI Add immediate Destination Source A [39] No Yes Yes Yes No Yes No Yes [40]
Type
BIT Bitwise logic Destination Source A [41] Source B No Yes Yes Yes No Yes Yes No
Type
BNT Inverse bitwise logic Destination Source A [42] Source B No Yes Yes Yes No Yes Yes No
Type
SHF Barrel shift Destination Source A [43] Source B No Yes Yes Yes No Yes Yes No
Type
SFI Barrel shift immediate Destination Source A [44] Immediate No Yes Yes Yes No Yes No Yes [45]
Type
MUL Multiply/divide Destination Source A [46] Source B Yes [47] Yes No Yes No Yes Yes No
UDH User defined hardware Destination Source A Type Source B Yes [48] Yes No Yes No Yes Yes No
UDH User defined hardware Destination Source A Type Source B Yes [49] Yes No Yes No Yes Yes No
Type
BCT Bit count Destination Source A [50] Immediate Yes [51] Yes No Yes No Yes No Yes [52]
 Screen function Opcode
Load x1 64 Port load on any operation stalls until the screen is finished processing queue
Load y1 65 Maximum queue size is 16 and it processes requests slower than the CPU can send them so you may need to use this
Load x2 66
Load y2 67 Port 0 maps to input controller:
Control
Clear screen 68 Bit Description
Buffer screen 69 7 Unused
Clear char display 70 6 Select
Load pixel 71 5 B button
Write character 1 72 4 A button
Write character 2 73 3 Left button pressed
Toggle integer display 1 74 2 Up button pressed
Toggle integer display 2 75 1 Down button pressed
Top bar
Display signed integer 1 76 0 Right button pressed
Display signed integer 2 77 Port 1 maps to pseudo RNG (3 bit)
Display unsigned integer 1 78
Display unsigned integer 2 79
Draw pixel 80
Draw rectangle 81
Draw pixel + load x1 82
Draw pixel + load y1 83
Draw
Draw rectangle + load x1 84
Draw rextangle + load y1 85
Draw rectangle + load x2 86
Draw rectangle + load y2 87
Erase pixel 88
Erase rectangle 89
Erase pixel + load x1 90
Erase pixel + load y1 91
Erase
Erase rectangle + load x1 92
Erase rextangle + load y1 93
Erase rectangle + load x2 94
Erase rectangle + load y2 95
Load byte 1 Sprite 96
Load byte 2 Sprite 104
Sprite operations
Draw sprite Sprite 112
NOP Sprite
 Screen layout Tile (0-6) Binary data Register allocation
01000100 01000100 R1 Temporary (counter?)
00000000 00001111 R2 Temporary (tile x?)
01000100 01000100 R3 Temporary (tile y?)
Playing area 00000000 00001111 R4 Temporary
01100000 00000110 R5 Temporary (direction?)
01100000 00000110 R6 Current tile x
01100000 00000110 R7 Current tile y
01100000 00000110 RAM allocation
01000000 00000111 0-55 Rotation data
Space for 00100010 00000110 56-57 Current tile data ?
tile here 11100000 00000010 58 Current tile rotation
01100000 01000100 59 Current tile ID
00100000 00001110 60 Score
01100000 00100010 61 Next tile ID
01110000 00000100 62 Full row count
01000100 00000110 62 ?
11000000 00000110 64-71 Permanent coordinates (x, y) pairs
01100010 00000100 72-79 Temporary coordinates (x, y) pairs
11000000 00000110 80-83 Temporary tile data split
01100010 00000100 84-88 Points for number of rows
00110000 00000110
01100100 00000010
00110000 00000110
01100100 00000010
01110000 00000010
00110010 00000010
01110010 00000000
01100010 00000010
Screen layout Register allocation
R1 Temporary
R2 Temporary (calculate x?)
R3 Temporary (calculate y?)
R4 x velocity
R5 y velocity
R6 Ball x
R7 Ball y
RAM allocation
0 Score
1 Paddle x
2 Has bounced this frame
26-73 Paddle bounce LUT
Screen layout Register allocation
R1 Temporary
R2 Temporary
R3 Temporary
R4 Temporary
R5 Temporary
R6 x
R7 y
RAM allocation
0-31 Board
32-63 state LUT
64-95 Board copy
Screen layout Register allocation
R1 Temporary
R2 Temporary
R3 Temporary
R4 Temporary
R5 Temporary
R6 Turn (X = 1, O = 0)
R7 Pointer index (1-7)
RAM allocation
0 ?
1-7 Number of pieces in each column
8-63 Board
Screen layout Register allocation
R1 Temporary
R2 Intermediate result byte 0
R3 Intermediate result byte 1
R4 Current result byte 0
R5 Current result byte 1
R6 Current x
R7 Current y
RAM allocation
0-204 Bitmap of + (0) or - (1)
 Fibonacci Prime numbers Cellular automata Sorting algorithms
Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Comment
Regular fibonacci Check if n is prime 1-dimensional (8 bit) Bubble sort
0 Setup LIM R1, 1 10000001 00000001 81 00 0 Setup PLD R1, 0 01011001 00000000 Get n 0 Setup PLD R7, 0 01011111 00000000 Get rule
1 LIM R2, 0 10000010 00000000 82 00 Setup registers 1 CMA R1, 1 10011001 00000001 Check if n is even 1 PLD R6, 1 01011110 00000001 Get genereation count
2 LOOPCNT 7 00010010 00000111 12 07 2 BRN ZERO, 0x11 00100100 01010001 (hence not prime) 2 PLD R5, 2 01011101 00000010 Get first generation
3 LOOPSRC 0x07 00010011 00000111 13 07 Setup loop 3 CMP R1, 1 10010001 00000001 Check if n is one 3 Main loop MOV R1, R5 10100001 10100000 Output last generation and
4 Loop ADD R1, R1, R2 10101001 00100010 A9 22 Output next fibonacci 4 BRN ZERO, 0x11 00100100 01010001 (hence not prime) 4 PST R1, 0 01010001 00000000 reset next generation
5 PST R1, 0 01010001 00000000 51 00 number 5 CMP R1, 6 10010001 00000110 Check if n is 2, 3 or 5 5 ADI R6, R6, -1 10111110 11011111
6 ADD R2, R1, R2 10101010 00100010 AA 22 Output next fibonacci 6 BRN LESS, 0x0E 00100011 01001110 (hence prime) 6 BRN NEG, 0x17 00100001 01010111 Check if finished
7 PST R2, 0 01010010 00000000 52 00 number 7 SQRT R2, R1 11111010 00100000 Max divisor to check 7 Loop setup BSLI R2, R1, 1 11011010 00100001
8 Halt HLT 00001000 00000000 08 00 Halt 8 LIM R3, 3 10000011 00000011 Setup divisor 8 AIM R2, 7 10001010 00000111 Get neighbours of first cell
n'th fibonacci 9 Loop MOD R4, R1, R3 11100100 00111011 Check if divisor 9 BSR R5, R7, R2 11010101 11101010 Get first cell of new
0 Setup PLD R3, 0 01011011 00000000 5B 00 Get n 10 BRN ZERO, 0x11 00100100 01010001 divides n 10 AIM R5, 1 10001101 00000001 generation
1 LIM R1, 0 10000001 00000000 81 00 11 ADI R3, R3, 2 10111011 01100010 Next divisor 11 LOOPCNT 7 00010010 00000111
2 LIM R2, 1 10000010 00000001 82 01 Setup registers 12 SUB R0, R3, R2 10110000 01100010 Check if divisor > 12 LOOPSRC 0x12 00010011 00010010 Setup loop
3 ADI R3, R3, -1 10111011 01111111 BB 7F Check if f_0 or f_1, in 13 BRT LESSEQ, 0x09 00100111 10001001 sqrt(n) (finished) 13 Loop ROTI R5, R5, 1 11011101 10110001 Rotate generation
4 BRN LESSEQ, 0x09 00100111 01001001 27 49 which case already done 14 Exit LIM R1, 1 10000001 00000001 14 AIM R2, 7 10001010 00000111 Get neighbours of cell
5 Loop ADD R1, R1, R2 10101001 00100010 A9 22 Get next 2 fibonacci 15 PST R1, 0 01010001 00000000 15 BSR R2, R7, R2 11010010 11101010
6 ADD R2, R1, R2 10101010 00100010 AA 22 numbers 16 HLT 00001000 00000000 n is prime: output 1 16 AIM R2, 1 10001010 00000001 Get cell in new generation
7 ADI R3, R3, -2 10111011 01111110 BB 7E 17 LIM R1, 0 10000001 00000000 17 ADD R5, R5, R2 10101101 10100010 Add to new generation
8 BRT GRTR, 0x05 00100010 10000101 22 85 Check if done 18 PST R1, 0 01010001 00000000 n is composite: 18 BSRI R1, R1, 1 11011001 00101001 Shift last generation
9 Exit BRH ZERO, 0x0C 00100100 00001100 24 0C Check if even or odd n 19 HLT 00001000 00000000 output 0 19 Loop end ROTI R5, R5, 1 11011101 10110001 Fix new generation
10 PST R1, 0 01010001 00000000 51 00 20 BRT TRUE, 0x03 00100000 10000011 Loop back
11 HLT 00001000 00000000 08 00 Output f_n if even n 21 Halt HLT 00001000 00000000 Halt
12 PST R2, 0 01010010 00000000 52 00 Conway's game of life (8x8 cells)
13 HLT 00001000 00000000 08 00 Output f_n if odd n
Recursive fibonacci PLD R7, 0
PLD R6, 1
PLD R5, 2
LIM R4, 7
MOV R1, R5
POI R6
PST R1, 0
ADI R6, R6, -1
BRN NEG, 0x17
BSLI R2, R1, 1
AIM R2, 7
BSR R5, R7, R2
AIM R5, 1
LOOPCNT 7
LOOPSRC 0x12
ROTI R5, R5, 1
AND R2, R4, R1
BSR R2, R7, R2
AIM R2, 1
ADD R5, R5, R2
BSRI R1, R1, 1
ROTI R5, R5, 1
BRT TRUE, 0x03
HLT
 Fibonacci Prime numbers Cellular automata Sorting algorithms
Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Comment
 Fibonacci Prime numbers Cellular automata Sorting algorithms
Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Comment
 Fibonacci Prime numbers Cellular automata Sorting algorithms
Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Comment
 Fibonacci Prime numbers Cellular automata Sorting algorithms
Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Comment
 Fibonacci Prime numbers Cellular automata Sorting algorithms
Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Comment
 Fibonacci Prime numbers Cellular automata Sorting algorithms
Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Comment
 Fibonacci Prime numbers Cellular automata Sorting algorithms
Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Bin Hex Comment Line Label Assembly Comment
[1] Halts the CPU.

[2] 000: Use alternate branch conditions

001: Force flags to not update
010: Set loop counter
011: Set loop source
100: Set stack pointer to immediate
101: unused
110: unused
111: unused

[3] Loads immediate if condition met, otherwise loads 0.

[4] Using register 0 does not store to any register, but uses the immediate as operands for the next
instruction if register 0 is chosen.

[5] 000: True

001: Even
010: Higher / Less Equal
011: Lower / Greater Equal
100: Zero / Equal
101: Not Zero / Not Equal
110: Higher Same / Less
111: Lower Same / Greater

Alternate = use alternate branch conditions (in STS)

[6] Between -16 and 15

[7] Lower immediate

[8] 1 clock cycle, or until new page fetched from memory

[9] 1 clock cycle, or until new page fetched from memory

[10] 1 clock cycle, or until new page fetched from memory

[11] 000: True

001: Even
010: Higher / Less Equal
011: Lower / Greater Equal
100: Zero / Equal
101: Not Zero / Not Equal
110: Higher Same / Less
111: Lower Same / Greater

Alternate = use alternate branch conditions (in STS)

[12] Bit T being 1 assumes branch taken.

[13] If bit E is 1, keep pointer until overwritten.

[14] 001: Branch offset

010:
011:
100: Flags register
101: Stack pointer
110: Memory / Port pointer
111: Loop pointer

Note: Program counter and flags register are read-only.

[14] 001: Branch offset
010:
011:
100: Flags register
101: Stack pointer
110: Memory / Port pointer
111: Loop pointer

Note: Program counter and flags register are read-only.

Writing to memory pointer replaces offset operand for next memory access.

[15] Halts until input fetched.

[16] Address = stack base pointer + stack pointer - offset.

If bit U is 0, decrement stack pointer after memory access.

[17] If bit U is 1, don't update stack pointer.

[18] If bit W is 1, do not push to memory (only update the SP)

[19] Halts on cache miss.

[20] Address = stack base pointer + stack pointer - offset.

If bit U is 0, increment stack pointer before memory access.

[21] If bit U is 1, don't update stack pointer.

[22] If bit W is 1, do not pop memory (only update the SP)

[23] Halts on cache miss.

[24] Address = pointer + offset.

[25] Halts on cache miss.

[26] Address = pointer + offset.

[27] Halts on cache miss.

[28] Using register 0 does not store to any register, but uses the immediate as operands for the next
instruction if register 0 is chosen.

[29] Lower + upper immediate

[30] Reg = reg AND immediate

[31] Lower + upper immediate

[32] Subtract immediate; updates flags but does not writeback

[33] Lower + upper immediate

[34] AND immediate; updates flags but does not writeback

[35] Lower + upper immediate

[36] Does not update flags.

[37] 00: regular addition

01: use previous carry
10: use vector byte mode
11: use both of the above
[37] 00: regular addition
01: use previous carry
10: use vector byte mode
11: use both of the above

[38] 00: regular subtraction

01: use previous carry
10: use vector byte mode
11: use both of the above

[39] Between -16 and 15

[40] Lower immediate

[41] 00: IMPLIES

01: XOR
10: AND
11: OR

[42] 00: NIMPLIES

01: XNOR
10: NAND
11: NOR

[43] 00: left shift

01: right shift
10: rotate right
11: sign extend right shift

[44] 00: left shift

01: right shift
10: rotate right
11: sign extend right shift

[45] Lower immediate

[46] 00 = multiply (lower 8 bits)

01 = multiply (upper 8 bits)
10 = divide
11 = mod

[47] Halts until finishes calculating.

[48] Halts until finishes calculating.

[49] Halts until finishes calculating.

[50] 00 = square root

01 = leading zero count
10 = trailing zero count
11 = count ones

[51] Halts until finishes calculating.

[52] Lower immediate